PAGE CPU OVERVIEW DIAGRAM. Power Supply PCI MOXP UAA UAA(2) [0-7] AUP1S (A-wire) NOT RDR NOT. Right Reg. Left Reg RDR [2-3] ALU Reg [4-7]

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1 PAGE CPU OVERVIEW DIAGRAM Power Supply PC MOXP PCI IR UAA UAA(2) RAM [0-7] RDR RDR R0 R1 A-out MUX AUP1S (A-wire) Right Reg Left Reg [2-3] SE ALU Reg izbiz REG (0,1) [4-7]

2 Button CLK From WAM Haltwire On/Off Reg CU BZO REG Biz wire SEO AddrO WAM Reg B Reg IR/W Reg Math Reg AUP1S BZO R/W ALUCU M C S ALU Data Memory Ov iz SEL Mem Reg Stable Reg iz R/W Reg SS BZO

3 Multiple Wire Circuit Representation Multiple Wire Black Box Representation

4 2.1.3 FETCH HARDWARE CIRCUIT DIAGRAMS Normal Register NOR CLK NOR Normal Register Black Box Representation Flip Flop

5 Continuous Stream Register NOR NOR Continuous Stream Register Black Box Representation CSR

6 Intermediate View of a Generic 1-Bit Register Flip Flop List of Major 1-Bit Registers BZO Reg Math Reg Internal R/W Reg R/W Reg B Reg is-zero? (iz) Overflow? (Ov) Intermediate View of a Continuous Stream Register List of Major 1-Bit CS Registers WAM Reg ON/OFF Reg CSR

7 Intermediate view of an n-bit register with a single thick wire input. 1 2 Flip Flip n..... Flip Black Box Representation of an n-bit register receiving input from a single thick wire List of Major (Non-trivial) Registers PC Counter RIGHT Reg LEFT Reg izbiz (5 Bit) Reg CMS (3 Bit) Reg (also C, M, S) Stb (Stable) Reg (0) Mem. Reg ALU Reg IR (8 Bit) Reg R-0 Reg R-1 Reg A-Out Reg

8 In-depth view of the GDK Clock POWER SUPPLY BZZZZZZ ZZZZZZ (vibrating noise) QUARTZ from WAM CLK Output Clock Black Box Representation CLK

9 Input 2 Input 1 Intermediate view of the PC counter Inputs 1 and 2 will never simultaneously hold information. They have direct access to each bit through a simply fusion of their wires as displayed below. Flip- Flop Flip- Flop Flip- Flop Flip- Flop Output 1 Output 2 Input 2 Input Circuit Input 1 Diagram Input Black Box Representation Input 2 Input 1

10 PC (Zero) Initializer Circuit Diagram From Button And Not To PC From clock PC Initializer Black Box Representation (Two 1-Bit inputs, One 4-Bit output (all zeros) PCI

11 UNIT ADDER ALU -- Circuit Diagram Input HA HA HA Output UNIT ADDER ALU Black Box Representation UAA

12 TWO UNIT ADDER ALU Input HA HA Output TWO UNIT ADDER ALU Black Box Representation UAA(2)

13 2.2.3Load Hardware Circuit Diagrams Register Memory Bank Circuit Diagram Bits 2,3 RDR Bits 4,5 Note: R-0, R-1 and A-Out are all found in BOTH RDR registers. The RDRs are actually far more interleaved than shown here and it is only to ease the reader's viewing that we maintain them as two separate boxes. RDR From Stb Reg (0) : Register Address From Memory: To be Written into Register R/W Register Memory Bank Black Box Representation. RMB

14 Register Selection Device (RSD) 1 2 Not Not RSD Black Box (2 inputs, 3 outputs) RSD

15 Register Data Retriever R/W from R/W Reg 1 2 Data from Memory only used w/ Store Circuit 1 Address 00: R0 RSD Circuit 1 (Addr 01: R1) Circuit 1 (Addr 10: A-out) Register Data Retriever (3 inputs and clock, 4 bit output) RDR

16 Circuit 1 in Detail for A-Out Register From ALU Reg Clk From RSD A-out

17 Address Selection Device (ASD) ASD Box (4 inputs, 16 outputs) ASD

18 Address 1 from PC ASD Address 2 from PC ASD Circuit 1 Address 0000 RAM Circuit Diagram Circuit 1 (0001) Circuit 1 (0010) Circuit 1 (0011) Circuit 1 (0100) Circuit 1 (0101) Circuit 1 (0110) Circuit 1 (0111) Circuit 1 (1000) Circuit 1 (1001) Circuit 1 (1010) Circuit 1 (1011) Circuit 1 (1100) Circuit 1 (1101) Circuit 1 (1110) Circuit 1 (1111) To IR 0-3 To IR 4-7

19 RAM Circuit Diagram Black Box Address 1 Address 2 RAM Circuit Diagram Content 1 Content 2

20 Sign Extend 1 st bit 2 nd bit Sign Extend Box-2bits to 4 bits (2 input, 4 output) SE

21 2.3.3A-OUT UPDATE PHASE 1CIRCUIT DIAGRAMS 0 1 ALU Circuit Diagram 2C S M C 2C MULT FA iz is 0 A-out Ov

22 CMS 3 Wire Circuitry 3-Bit wire circuitry 3-Bit wire black box representation Intermediate view of the C M S register C M S

23 Is Zero Box Circuit Diagram is Zero Box Box Representation iz

24 FULL ADDER CIRCUIT DIAGRAM HA HA HA HA HA HA HA S FULL ADDER BLACK BOX REPRESENTAITON 2 FA

25 HALF ADDER CIRCUIT DIAGRAM B A unkeyed OR BLACK BOX REPRESENTATION HA REMAINDER OUTPUT

26 Multiplication Circuit Diagram ABM FA Not FA FA OR Multiplication Box Representation (2 4-Bit and one binary 1 input, 1 4-Bit and one Overflow bit output) MULT

27 All Bits Multiplication Box Circuit Diagram [0-3] LBM [0-3] [0-3] [0-3] LBM LBM [0-3] LBM All Bits Multiplication Box Box Diagram (2 4-bit inputs, 4 4-bit outputs ABM

28 Left Bit Multiplication Box Circuit Diagram Left Bit Multiplication Box Box Representation LBM

29 Control Unit 8 bit OP-CODE from IR (each box is a bit, ie, box 0 is the bit at position 0) AUP1S To A-wire To AddrO MATH Register AOS iss islc ALUCU C M S SEO ALUCU From on/off button OR WAM Register isl Internal R/W Register R/W Wire From WAM ish isb Haltwire OR ON/OFF Reg B Register BZO wire BIZ Wire To BZO Reg

30 is Stop (checks if the operation is Stop) ishalt (checks if operation is Halt) isstop Box 1 if OP-CODE is STOP 0 for anything else iss is Halt Black Box 1 if the OP-CODE is Halt 0 for anything else ish isbiz (checks if operation is Biz) isload (checks if operation is LOAD) N N isbiz Black Box 1 if OP-CODE is BIZ 0 if anything else isload Black Box 1 if OP-CODE is LOAD 0 if anything else isb isl

31 isload or Comp (checks if operation is LOAD or COMP) is Store (checks if operation is Store) N isload or Comp Black Box 1 if OP-CODE is COMP or LOAD 0 for anything else islc isstore Black Box 1 if OP-CODE is STORE 0 for anything else isst

32 AddrO Stream Chooser isb isst isl OR To AddrO 1 if Address is last 4 bits 0 if anything else AddrO Stream (1, 4 bit input, 1 output) AOS

33 A-Out Update Phase 1 Selector OR A-Out Update Phase 1 Selector (4 inputs-0,1,2,3 bits of OP-CODE, 1 output) AUP1S

34 ALU CU To C Register in ALU To M Register in ALU To S Register in ALU ALU CU Black Box (6 inputs-0,1,2,3,6, and 7 bits of OP-CODE, 3 outputs for C, M, S registers) ALUCU

35 Biz Selector 1 st choice Selector BIZ Selector (1 choice and 1 selector input, 2 outputs) SEL

36 2's Complement HA HA HA 2's Complement Box (4 input, 4 output) 2C

37 Data From Left Reg Circuit 1 R/W Address 0000 Address Data Memory Circuit 1 (0001) Circuit 1 (0010) Circuit 1 (0011) Circuit 1 (0100) Circuit 1 (0101) Circuit 1 (0110) ASD Circuit 1 (0111) Circuit 1 (1000) Circuit 1 (1001) Circuit 1 (1010) Circuit 1 (1011) Circuit 1 (1100) Circuit 1 (1101) Circuit 1 (1110) Circuit 1 (1111) Mem Reg (4 bits)

38 2.4.3 WRITE HARDWARE CIRCUIT DIAGRAMS Sign Extend (1 to 4 bits) Sign Extend Black Box (1 bit input to 4 bit output) SE Sign Shrink Sign Shrink Box (4 bit input, 2 bit output) SS

39 Memory Black Box 4 bit Address (from Left) Read/Write (from CU) 0=Read 1=Write Data (from Right) Mem Reg Data Memory

40 1 st 4 bit input 2 nd 4 bit input Selector 4 bit output Mux Black Box (2 4 bit and 1 selector bit inputs, 4 outputs) MOX

41 Intermediate view of the izbiz Register (0, 1) 4-Bit Biz input Flip Flip 5-Bit izbiz Register (0,1) : follows standard register circuitry Four 1-Bit wires Flip Flip 1-Bit iz input Flip

42 APPENDIX C : First attempt at HALT and STOP Original Halt/Stop command (Historical) CLOCK CU CPU

43 APPENDIX D: FIRST ATTEMPT AT ALU CLK 2C C 2C CLK CLK C1 CLK CLK M CLK 1 M CLK 0 M 1 0 FA C2 MULT From CU iz OS A-OUT is-zero ALU CIRCUIT DIAGRAM (Historical V. 1)

CPU MINI PROJECT. Gen Kazama David Kawrykow COMP 273 Professor Vybihal CPU Mini Project

CPU MINI PROJECT. Gen Kazama David Kawrykow COMP 273 Professor Vybihal CPU Mini Project CPU MINI PROJECT Gen Kazama 260181388 David Kawrykow 260186503 COMP 273 Professor Vybihal CPU Mini Project Table of Contents Overview of CPU Section 1.0.0 CPU Diagram Section 1.1.0 1-Page CPU Overview