CSCE 312 Lab 3: Sequential Logic Design ([Vahid] Ch. 3) Instructor: Dr. Hyunyoung Lee Spring 2013

Transcription

1 CSCE 312 Lab 3: Sequential Logic Design ([Vahid] Ch. 3) Instructor: Dr. Hyunyoung Lee Spring 2013 In this chapter, we focus on the design of sequential digital circuits for real-life applications. Sequential circuits allow us to capture the notion of time, so that it is possible to store and track different states across time. Thus sequential circuits can manifest higher level of machine intelligence and perform more complicated tasks than combinational circuits. Required tools: Logisim 2.5.x Assigned on: February 11, 2013 Due date and time: 9 p.m. Sunday, February 24, Learning objectives Primary topics 1. How to design sequential digital circuits using logic gates and standard components. 2. How to document the design and its operations for others to understand. 3. The basic design considerations for sequential circuits. 4. How to standardize designs to generate reusable circuit design patterns to benefit from standardization and reusability (concept of macro). 5. How to apply standard design patterns to organize basic IO and peripheral circuitry. Secondary topics 6. Using the schematic design tool ( Logisim ) to create reusable libraries of design patterns. 7. Familiarity with all the basic sequential circuit blocks. 8. How to interpret data sheets for industrial components as apart of the design activity. Based on material prepared by Dr. Rabi Mahapatra, Suneil Mohan, and Amitava Biswas 1

2 2 Instructions Use Logisim for your designs. Logisim should be available on the lab machines. If not, you can download a copy from the previously mentioned website. 3 Useful resources Chapters 1 3 of Frank Vahid s Digital Design or the first few chapters of any digital circuit/design/architecture book by Morris Mano (available in TAMU library). 4 Exercises to do 4.1 Problem 1 First, download the Lab-3 extra files from the course homepage. When you extract the zip archive, you will see two possible solutions to Question 4 from Lab 1. The second solution is incomplete (does not implement all 5 requirements). There is also an Excel sheet that can help you understand how the solution code was created and a timing framework that you will use. 1. Study the two alternative methods of working on the question after completing the second version. 2. Run both solutions using the timing framework provided and note down how long each method takes to process. 3. Now, using the same timing framework, run the code version that you created for Lab 1, Problem 4. Report the difference between the performance between your code and the two versions of the solution codes. 4. Write an analysis why different versions of the solution code might have different performance. Also provide an analysis why your code has a different performance (slower or faster) than the solution code(s). 5. Identify ways to improve your code (or the solution code, in case your code performs better). 4.2 Problem 2 You performed well in you last design assignment at Ford Motor Company, so you still retain your job there. Today your manager asked you to design the switch that starts and stops the cars air conditioning system. The requirement is given as:... When the a/c button is pushed it should start the a/c, pushing this button for the second time should stop the a/c. The button also incorporates a built-in green LED which glows when the a/c is operating, and remains off otherwise. This switch signals the cars main control logic to turn on the relay that switches on the a/c compressor... 2

3 You asked one of your senior colleagues to help you get started. He told you that this kind of button functionality is known as a toggle push button. He also told you that as Ford is facing competition to cut costs, it would be better to use a normally off (push-to-make) illuminated push button (SPST, NO) to implement this toggle push button (which is cheaper and more reliable), rather than using a costly and less reliable mechanical toggle button. This kind of push button with built-in LED (for illumination) is available in the market. The SPST NO illuminated push button switch that you finally choose has four terminals two for the switch, and the other two are for the LED which has a resistor in series (to limit the current through the LED), you can apply 3 to 5 V to the LED terminal to illuminate the LED. (Different types of switches are described in the link: 1. Find out the meanings of SPST and NO in the context of electro-mechanical switches. 2. Design a small digital circuit (with Logisim) using basic logic gates, so that when this circuit is used with the chosen switch, it will make the circuit function as a toggle switch. Use the button component in Logisim for this question. (Input/Output > Button) The way the button switch operates in Logisim is as follows: as long as you keep the button pressed, an LED or other output signal will stay ON; when you release the button, the LED or output signal goes OFF. Design a toggle switch such that when you press the button once, your LED turns ON and then remains ON (even after the button is released) until the button is pushed again. 3. Using the text-insert feature in Logisim mention in the circuit the chip number(s) (from the 74XX family) that you would use for the circuit and identify the pin numbers that would be used by your circuit. 4. Discuss what kind of flip-flop could be used instead of basic logic gates to design the same circuit. 4.3 Problem 3: Suppose you are asked to design a circuit to implement six similar toggle switches using six SPST NO push button switches, as in the previous problem. (This will be useful to implement the air flow controls on the cars dash board.) 1. Without designing the entire circuitry, estimate how many logic gates will be required (this parameter is also known as gate count ). 2. What will be the chip count for 74XX family logic gates? The chip count is the total number of IC chips that are required for the design. For example, if a design requires 1 AND gate, 2 OR gates and 1 NOT gate, then the gate count is 4 and the chip count for that design is 3. For a design with 5 AND gates and 1 NOT gate the chip count is 3. This 3

4 is because the 74XX AND gate chip has 4 AND gates, the 74XX OR gate chip has 4 OR and there are 6 NOT gates in the 74XX family NOT gate chip. 3. What is the chip count for the design with flip-flops? Identify the 74XX series chip to use. 4.4 Problem 4: Your manager at Ford has asked you to design a circuit to implement addressable I/O for a 4 bit!"#$%&'()&)*+,-%..*-&/.&01-2%3&*2&45&,100/26&'&4/2'-5&%71/8'9%20&*:&;&'23&%2'49/26&0$%&<(=& microprocessor/microcontroller. This will be used to activate 7 actuators (the a/c compressor, 4 %2'49%&9/2%>&?2&'33-%..&8'91%&!@A&6%0.&0$%&@23&3**-&9*)B%3&CD**-&@E">>A individual door locks, the engine starter and the windshield wipers). This circuit will allow a CPU with a 4 bit address bus to activate actuators by placing/writing suitable addresses on the F%&$'.&'9.*&.B%0)$%3&*10&0$%&:*99*G/26&.5.0%+&9%8%9&3/'6-'+&:*-&5*1>&F%&%H,%)0.&5*1&0*&3%0'/9& address bus. He has provided the following text requirement to get you started:... The a/c *10&0$%&<(=&)*20-*9&49*)B&'23&6%2%-'0%&0$%&-%71/-%3&6'0%&9%8%9&)/-)1/0-5&:*-&/0>&I*-&0$%&+*+%20J& compressor!"#$%&'()&)*+,-%..*-&/.&01-2%3&*2&45&,100/26&'&4/2'-5&%71/8'9%20&*:&;&'23&%2'49/26&0$%&<(=& is turned on by putting a binary equivalent of 0 and enabling the I/O enable line. An 5*1&+'5&/62*-%&0$%&/20%-2'9.&*:&0$%&+/)-*,-*)%..*->&#$/.&G/99&4%&3/.)1..%3&9'0%->& address %2'49%&9/2%>&?2&'33-%..&8'91%&!@A&6%0.&0$%&@23&3**-&9*)B%3&CD**-&@E">>A value 2 gets the 2nd door locked (Door 2)... He has also sketched out the following system level diagram for you. He expects you to detail F%&$'.&'9.*&.B%0)$%3&*10&0$%&:*99*G/26&.5.0%+&9%8%9&3/'6-'+&:*-&5*1>&F%&%H,%)0.&5*1&0*&3%0'/9& out the I/O control block and generate the required gate level circuitry for it. For the moment, *10&0$%&<(=&)*20-*9&49*)B&'23&6%2%-'0%&0$%&-%71/-%3&6'0%&9%8%9&)/-)1/0-5&:*-&/0>&I*-&0$%&+*+%20J& <(=&%2'49%&)*20-*9&9/2% you may ignore the internals of the microprocessor. This will be discussed later. 5*1&+'5&/62*-%&0$%&/20%-2'9.&*:&0$%&+/)-*,-*)%..*->&#$/.&G/99&4%&3/.)1..%3&9'0%->&?)01'0*-&)*20-*9& P&4/0&,-.&13+2#3)& 9/2%. +/)-*)*20-*99%- P&4/0&'33-%..&41. <(=&%2'49%&)*20-*9&9/2% 1*#1(*2 P&4/0& +/)-*)*20-*99%- P&4/0&'33-%..&41.,-.&13+2#3)& 1*#1(*2?)01'0*-&)*20-*9& 9/2%. He has also given you an incomplete truth table for the output actuator operation: F%&$'.&'9.*&6/8%2&5*1&'2&/2)*+,9%0%&0-10$&0'49%&:*-&0$%&*10,10&')01'0*-&*,%-'0/*2&K!""#$%%&'(%&)*+$%,-.&!12(023#&13+2#3)&)*+$% 4355$+2!6 F%&$'.&'9.*&6/8%2&5*1&'2&/2)*+,9%0%&0-10$&0'49%&:*-&0$%&*10,10&')01'0*-&*,%-'0/*2&K!7!8!9 /+0')$!-1 :9 :8 :7 :6 /+;*+$& <*=$#% %20#2$# L!""#$%%&'(%&)*+$% L L L,-.& ; ; ; ;!12(023#&13+2#3)&)*+$% ; ; ; ; M*0$/26&$',,% $+2!6 ;!7 ;!8 ;!9 ; /+0')$ ;!-1 ; :9 ; :8 ; :7 ; :6 ; /+;*+$& ; <*=$#% ; M*0$/26&$',,%2. ; ; ; ; N N ; ; ; ; %20#2$# ; ;?()&6%0&01-2%3&*2 ; L ; L ; L NL N ; ; N ; ; ; ; ; ; D**-&N&6%0.&9*)B%3 M*0$/26&$',,%2. ; ; N ; ; N ; ; ; N ; ; ; ; ; D**-&@&6%0.&9*)B%3 M*0$/26&$',,%2. ; ; N; N; N ; N ; ; N ; ; ; ; D**-&O&6%0.&9*)B%3?()&6%0&01-2%3&*2 ; ; ; N N ; N ; ; ; ; ; D**-&N&6%0.&9*)B%3 ; ; N ; N ; ; N ; ; ; ; D**-&@&6%0.&9*)B%3 ; ; N N N ; ; ; N ; ; ; D**-&O&6%0.&9*)B%3 4

5 To help you with the design, another one of your colleagues has provided you the following timing diagram:!"#$%&'#(")#*+,$#,$%#-%.+/01#20",$%3#"0%#"4#(")3#5"&&%2/)%.#$2.#'3"6+-%-#(")#,$%#4"&&"*+0/#,+7+0/#-+2/327#8 U&"5; N=O# ]029&% TE TI TC TA T=5 LE LC!"#$%#!"#)0-%3.,20-#,$%#9+/#'+5,)3%#"4#,$%#4+02&#.(.,%7#-%.+/0#*$+5$#(")#+.#+0#(")3#7202/%3:.# Tips: To understand the big picture of the final system design which is in your manager s mind, 7+0-1#&"";#2,#$,,'<==***>72,$>&)5>%-)=?@-/=*A,%25$+0/=5"7'BCDE=4EC=FGH='IJCBEJKEI>FGH look at Activities I> L%.+/0 to do # 20- # 6%3+4( #,$% # 3%M)+3%- # 5+35)+, #," # +7'&%7%0, #,$% # N=O # 5"0,3"& #.)9K.(.,%7> # 1. Design and verify the required circuit to implement the I/O control sub-system. P",%#,$2,#,$%#/+6%0#.'%5+4+52,+"0.#-"#0",#.'%5+4(#2#*2(#,"#,)30#OQQ#2#-%6+5%#"05%#+,#$2.# Note 9%%0#,)30%-#OP> that the given #R2;+0/#2''3"'3+2,%#2..)7',+"0.1#+05&)-%#2#5"0,3"&#.%M)%05%#,$2,#520# specifications do not specify a way to turn OFF a device once it has been 2&."#2&&"*#(")#,"#,)30#OQQ#2#-%6+5%>#S")#72(#*20,#,"#,2&;#,"#(")3#!T#29"),#'"..+9&%# turned ON. Making appropriate assumptions, include a control sequence that can also allow *2(.#"4#+7'&%7%0,+0/#,$+.> you to turn OFF a device. Discuss during the lab with your TA about possible ways of implementing this. C> U3%2,%#,+7+0/#-+2/327.#V).+0/#2#'3"/327#.)5$#2.#W+.+"#"3#G2+0,X#.$"*+0/#,$%#5$20/%#"4# 2. Create.,2,%#"4#,$%#623+").#.+/02&#20-#5"0,3"&#&+0%.#2.#+7'&%7%0,%-#9(#(")3#5+35)+,>#Y$"*#,$%# timing diagrams (using a program such as Visio or Paint) showing the change of state 5&"5;#20-#,$%#.%,#"4#'2,,%30#*26%4"37.#"0#TEKTA#20-#,$%#5"0,3"&#&+0%.#92.%-#"0#,$%# of the various signal and control lines as implemented by your circuit. Show the clock and 4"&&"*+0/#25,+6+,+%.> the set of pattern waveforms on A0 A3 and the control lines based on the following activities. Clock U&"5;#5(5&%#I<#TAKTE<#62&)%#EEIE cycle 1: A3 A0: value 0010 Clock U&"5;#5(5&%#A<#TAKTE<#62&)%#EEEI cycle 3: A3 A0: value 0001 Clock U&"5;#5(5&%#Z<#TAKTE<#62&)%#EEII cycle 5: A3 A0: value 0011 I/O goes to state-1, one clock cycle after A3 A0 gets a new value and remains at a high N=O#/"%.#,"#.,2,%KI1#"0%#5&"5;#5(5&%#24,%3#TAKTE#/%,.#2#0%*#62&)%#20-#3%72+0.#2,#2#$+/$# state for one cycle. At Clock cycle 0, all lines are at 0 state..,2,%#4"3#"0%#5(5&%>#t,#u&"5;#5(5&%#e[#t&&#&+0%.#23%#2,#e#.,2,%>#\ 5