Implementing a Verilog design into the UWEE CPLD Development Board Using Xilinx s ISE 7.1i Software: A Tutorial

Transcription

1 Implementing a Verilog design into the UWEE CPLD Development Board Using Xilinx s ISE 7.1i Software: A Tutorial Revision 0 By: Evan Gander Materials: The following are required in order to complete this tutorial. ISE 7.1i Webpack software distribution available from A computer with a 25-pin Parallel port A parallel III cable (typical printer cable) A UWEE CPLD Development Board and 9V adapter Time and patience Theory and definations: The Xilinx ISE development environment allows an engineer to enter a design in a several source formats, including Verilog. ISE allows the design to be expressed in a hierarchal way as the project develops. This allows the engineer to easily change modules as needed and facilitates easy testing. In an ISE design, all design files are called SOURCES. A source is a file that specifies part of the overall design. These include HDL files in various formats (Verilog, VHDL, ABLE), schematic entry files, and state diagrams. Other types of sources are things like test fixtures and constraint files. Some source types may be new to you, but they are integral to the ISE approach. All source files are organized into a hierarchy that starts with the TOP-LEVEL MODULE. There are several ways to enter a working design into ISE. This tutorial will illustrate the preferred method. In the preferred method, the top-level module is a schematic file (.sch). Having a schematic as the top-level module allows all sub modules to be combined in the top-level module as they would be in a block diagram. A top-level schematic module also allows signal markers to be attached to the design more easily. Synthesizing a design in ISE comes down to two things. Gathering all the needed sources, and running PROCESSES on those sources. In ISE, a process is an operation that is performed on or with a source file. Different Processes are available for different sources. Selecting a source will enable a list of processes available to that source. Any processes run will be run down the hierarchy. That is why it is important to pay attention to which source a process is being performed on. Just because a process is available does not mean that it is appropriate, or necessary. When a design is complete ISE allows the entire design to be synthesized into a JEDEC file (,jed). This file is then used to program the Development Board. The same

2 design can be entered many different ways, but the design work is easiest when the power of hierarchical design and display are taken advantage of. Tutorial: Design Entry The object of this tutorial is to illustrate the entry of a frequency divider that will reduce the frequency of the Development Board s 20MHz onboard clock to.8hz. 1. First, create a folder for this project. All work should be saved to this folder due to the large number of files generated by ISE. In this case call the folder Demo_Project. ISE does not support the space character in source names, so it is a good habit to name everything using an underscore in place of a space. 2. Open ISE 7.1i. When the program opens, select File>New Project Figure 1: New Project dialog box Under Project name, title the project. This does not have to match the file name, but it is helpful. Also, make sure to specify that the top-level module is a schematic file. Select the project location and click next.

3 Figure 2: New Programs Properties dialog box Fill in the values as shown in Figure 2. Device Family XC9500 CPLDs Device XC95108 Package PC84 Speed Grade -15 Top-Level Module Type Schematic Synthesis Tool XST (VHDL/Verilog) Simulator Modelsim Generated Language Verilog Click Next. The dialog will proceed to the Add New Sources dialog. Skip this by clicking Next. 3. In the Add Existing Sources dialog import the.v module used in EE271.

4 Figure 3: The Add Existing Sources dialog box Make sure that the file is imported as a Verilog Design File, and not as a Test Fixture File. Check the box to copy the source to the project. Click Next. Click Finish. The new project is now ready for editing. Before moving on it is instructive to look at the ISE window for a new project displayed in Figure 4.

5 Figure 4: A new project and the Sources, Processes, and Console Panes 4. Now it is time to add the top-level module to the Sources Pane. Right-click the device labeled xc pc84 and select New Source as illustrated in Figure 5. This is going to create the top-level module for the hierarchy. In the dialog box enter the name of the Design. In this case the name is Main_Design. Be sure to select the Schematic source as the source type. Then click Next. Click Finish.

6 Figure 5: Adding the top-level source Figure 5: New Source dialog box

7 Figure 6: A new source in the Sources Pane 5. Now it is time to enter a sub-module source. Right-click the sources pane and select New Source. Name this module Freq_Divider and select Verilog as the source type. Click Next. Figure 7: New Verilog source

8 The Define Source dialog box, shown in Figure 8, will appear. Define the inputs and outputs of the module in this dialog box. For this example the inputs are CLK_IN and RSP, and the output is CLK_OUT. Enter the inputs and outputs and click Next, then click Finish. ISE generates a nicely formatted Verilog module with the defined inputs and outputs. Figure 8: Automatically formatted Verilog module 6. Now you can edit the nicely formatted Verilog module. Try not to screw up the nice formatting. In this case, the added code is shown below. // Q, nq, D, CLK, RST dff_1(q1, w1, w1, CLK_IN, RST); dff_2(q2, w2, w2, Q1, RST); dff_3(q3, w3, w3, Q2, RST); dff_4(q4, w4, w4, Q3, RST); dff_5(q5, w5, w5, Q4, RST); dff_6(q6, w6, w6, Q5, RST);

9 dff_7(q7, w7, w7, Q6, RST); dff_8(q8, w8, w8, Q7, RST); dff_9(q9, w9, w9, Q8, RST); dff_10(q10, w10, w10, Q9, RST); dff_11(q11, w11, w11, Q10, RST); dff_12(q12, w12, w12, Q11, RST); dff_13(q13, w13, w13, Q12, RST); dff_14(q14, w14, w14, Q13, RST); dff_15(q15, w15, w15, Q14, RST); dff_16(q16, w16, w16, Q15, RST); dff_17(q17, w17, w17, Q16, RST); dff_18(q18, w18, w18, Q17, RST); dff_19(q19, w19, w19, Q18, RST); dff_20(q20, w20, w20, Q19, RST); dff_21(q21, w21, w21, Q20, RST); dff_22(q22, w22, w22, Q21, RST); dff_23(q23, w23, w23, Q22, RST); dff_24(clk_out, w24, w24, Q23, RST); After making changes to Freq_Divider.v do a SAVE ALL operation. After the Save, the sources in the hierarchy will reorganize as in Figure 9. Figure 9: Hierarchy organization reflects the way modules interconnect

10 7. The Verilog module can now be tuned into a schematic component for use in the top level module. To do this, select Freq_Divider.v from the sources pane. Then double click Create Schematic Component under Design Utilities in the Processes Pane. After the process completes a green checkmark will appear beside the process. Figure 10: Process to turn an HDL module into a Schematic component

11 Figure 11: The process has completed successfully After the process has completed the component is ready to be added to the Main_Design Schematic. Open Main_Design and select the new tab that appears at the bottom of the sources pane, components.

12 Figure 12: The components tab Now find the symbol named Freq_Divider. Selecting this will allow you to place it on the schematic as illustrated in Figure 13.

13 Figure 13: Placing a component into the Main_Design Schematic After Freq_Divider has been added to the Main_Design Schematic, save everything. This will cause the hierarchy to reorganize again.

14 Figure 14: Design Hierarchy 8. Now it is time to add signal markers to the signals from the frequency divider. These signal markers will allow the signals to be directed to pins. Select the Add I/O Marker button from the toolbar. Click on the connector for each signal. The default name can be changed by clicking double-clicking the marker. It is recommended to change the marker names to something that describes the signal. Figure 15: Markers added to Main_Design and connected to Freq_Divider 9. The design code is now entirely implemented. The next step involves a source to specify physical attributes. This is called a User Constraint File (.UCF). To create a.ucf file, right-click Main_Design in the the Sources Pane and select New Source. Select Implementation Constraints File from the Dialog box. Click Next and then Finish. This is the same procedure as usually used for adding any new source to the project, but in this case, right-clicking on Main_Design specifies that the.ucf is subordinate to the Main_Design file.

15 Figure 16: Selecting an Implementation Constraints File (.UCF) 10. Now that there is a Constraint File for the design the physical constraints can be set. There are many options that can be set in the user constraints, but the one that is most useful with the Development Board allows signals to be routed to specific pins. First, select Main_Design in the Source Pane. Then, in the Processes Pane, Double Click Assign Package Pins under User Constraints. This will open a program called PACE. PACE is an environment that allows Signal Markers in the Schematic file to be placed on specific pins on the XC95108 CPLD. By dragging a signal to a pin, the signal is routed. Some pins are intended for specific signals, like clocks. Others are going to be restricted by the design of the Development Board. Please check the Development Board Schematic for hardware dedicated pins.

16 Figure 17: PACE signal routing with a GUI 11. At this point, the design entry is over and the implementation begins. In the Processes Pane Double-Click Implement Design. It will take a few seconds for the processes to complete. When Done, there should be green checkmarks next to Implement Design and all of its immediate subordinate processes: Synthisize XST ; Translate ; Fit ; Generate Programming File. If any of these are missing, then there is a problem with the design. Consulting the Console Pane may shed light on the problem. It has tabs that will list errors and warnings generated by running the processes. Following a successful implementation a design report will be generated. This will list statistics of the design and the specific implementation of the design at the hardware level. It will also list your pin-outs.

17 Figure 18: The successfully implementation of a design. 12. The final step in design implementation is programming the design to the Development Board. In order to do this the board must first be set up. Connect the Development Board to the Parallel Port on the computer using a standard 25- pin printer cable. Next, connect the power adapter to the Development Board and plug it in. The Board will not program without power. Be warned, in the process of programming signals can be generated on the CPLD s pins. Make sure that any circuit attached to your design is prepared for this. In the Processes Pane Double-Click on Genarate SVF/XSVF/ under Optional Implementation Tools. This will Launch another program impact. impact is a tool that uses JEDEC files to program the Development Board via the JTAG standard circuitry on the Board. impact has other uses though, so it is important that it is operating with particular setting for programming the Development Board. If the Prepare Configuration Files window opens select cancel. This should leave impact on the screen, as in figure 19.

18 Figure 19: The impact window should look like this. If impact is in File Mode, change it to Configuration Mode by Selecting Mode>Configuration Mode. If Configuration Mode is not an option then impact already in Configuration Mode. Select the Boundary-Scan tab. Boundary-Scan is the method that is used to program the CPLD. It uses a serial input stream to command the chip. Using Boundary-Scanning, impact can actually program several chips daisy chained together. The Development Board, however, does not allow for serial connection of anything other than the one XC95108 already mounted. Right-Click in the open area and select Add Xilinx Device. In the Dialog box, open Main_Design.JED. This is the file that was generated when the design was implemented in ISE. An icon should appear as in figure 21.

19 Figure 20: Adding a Device Figure 21: The XC95108 is the only device in the Boundary-Scan chain. In order to program the Development Board Right-Click the XC95108 icon and select Program. The dialog box in figure 22 will open. Make sure that the Erase Before Programming box is checked.

20 Figure 22: Make sure that Erase Before Programming is selected. Click OK. The programming process takes about 5 seconds. When it is though, the window should display a message, as in figure 23.

21 Figure 23: The Development Board has been programmed Troubleshooting: ( coming soon to revision 1 )