Project 1a: Hello World!

Transcription

1 Project 1a: Hello World! 1. Download cse465.zip from the web page. Unzip this using 7-Zip (not the Windows Utility it doesn t unzip files starting with a period) to your h:\ drive or wherever your CEC home directory is mounted. This will create 3 directories: a. cse465\ise\leon3\grlib-gpl b3145 VHDL description of the b. cse465\ise\leon3\sampleproj Sample ISE project that instantiates the 1. Leon3mp.xise Project file for the Xilinx tools. 2. top.ucf Constraints file for your design. This includes the constraints for the clocks and pins on the FPGA. 3. Top.v top level verilog for synthesis and simulation. 4. APBBusMaster.v APB Bus Master testbench 5. *.vhd wrappers for various components in Leon3 6. *.ngc Placed and routed Leon3 netlists. 7. ila.*, icon.* - cores used by ChipScope. c. cse465\eclipsekepler\sampleproj Sample C project that runs on the 2. Copy cse465\ise\leon3\sampleproj to cse465\ise\leon3\proj1 3. Double click on Leon3mp.xise to launch Xilinx ISE. If the file association is not set up correctly, then search for Xilinx in the start menu and browse to the.xise file. 4. Click on Project->New Source 5. Select Verilog Module and enter the File name: MemMappedReg.v 6. Use the New Source Wizard to define the I/O for the block diagram shown below. Use 31 instead of PAMAX-1 and PDMAX Create the Verilog to implement the block diagram shown below. Change the 31 s to parameters. The DReg will be created in the next step. 8. Create the DReg component from the class notes in the same manner. Just hit next in the Define Module dialog box since the module already contains the interface information. Page 1 of 5

2 9. Select your MemMappedReg component in the Design Window. Set the Design View to Implementation. Double click on Check Syntax. Fix any errors. Repeat for DReg. 10. Open top.v and make sure that `define SYNTH is commented out. 11. Instantiate your module in top.v after the line // Instantiate your verilog modules here a. Connect your ports to Clk, PSel11, PEnable, PWrite,Reset_,PAddr, PWData and PRData11. b. Comment out the default TestD assignments and modify the TestD vector by assigning: 1. PAddr[9:2] to TestD[31:24] 2. PRData11[7:0] to TestD[23:16] 3. PWData[7:0] to TestD[15:8] 4. 0 to TestD[7:3] 5. {PSel11,PEnable,PWrite} to TestD[2:0]. c. Modify the ChipScope signals: 1. {PSel11, PEnable, PWrite, PRData11, PAddr[15:0], PWData} to ChipScopeData 2. {PSel11, PEnable, PWrite} to ChipScopeTrig0 12. Rather than simulate the entire Leon3 processor, we will use a simulation model called APBBusMaster. This is conditionally instantiated in top.v depending on the SYNTH directive. By default, the APBBusMaster will issue 2 bus cycles. The 1 st cycle will write 0xdeadbeef to address 0x This will cause PSel8, PEnable and PWrite to be asserted and 0xdeadbeef will come out on PWData. The 2 nd cycle is a read to 0x which should assert PSel8 and PEnable and read the data on PRData8. Edit APBBusMaster.v and modify the Verilog to use device 11 by setting the address to 0x80000b00 for both the read and write cycles. We ll talk about why this works in the next lecture. 13. In the Design window, make sure Implementation is selected. Select your new MemMappedReg module. Right-Click and select Set as Top Module. Double click on Synthesize-XST/Check Syntax. Fix any errors. When finished, restore top as the top module. 14. In the Design window, select Simulation 15. Click on Edit-> Preferences and verify that these settings are set: Page 2 of 5

3 Click OK 16. Select top (top.v) in the Design window and double click on Simulate Behavioral Model under the Modelsim Simulator in the processes window. If you get errors when the design is compiled in Modelsim, then fix the errors in ISE and save the files. You can reload the entire design by hitting the up arrow in Modelsim to execute do {top.fdo} again. 17. After Modelsim launches, click on Tools->TCL->Execute Macro and browse to top_wave.do. This will add some useful signals to the wave window. 18. Click on the Restart button and the on the Run-All button. Look at the wave window verify that your design correctly responds to the 2 bus cycles and that your register the correct value. 19. Study the Verilog in APBBusMaster.v to make sure you understand how the bus cycles are generated. 20. Back in ISE, change the Design View to Implementation. Select the instance of MemMappedReg in the Processes window. Right click and make this the top module. You can now synthesize just this module. Double click on Synthesize- XST. When it finishes, look at the Errors and Warnings tabs for problems. You can safely ignore the warning Input <PAddr> is never used. 21. Now it is time to implement it your design. Uncomment `define SYNTH at the top of top.v. This will instantiate the Leon3 instead of the simulation model for the APBBusMaster. Save top.v. Right click on top.v and make it the top module. 22. Double click on Generate Programming File in the Processes window to generate top.bit 23. There are many warning generated by the implementation of the Here are a few warnings that you can safely ignore: Page 3 of 5

4 a. WARNING:Xst: Core <icon> was not loaded for <i_icon> as one or more ports did not line up with component declaration. Declared output port <control0<3>> was not found in the core. Please make sure that component declaration ports are consistent with the core ports including direction and bus-naming conventions. b. WARNING:Xst: Core <ila> was not loaded for <i_ila> as one or more ports did not line up with component declaration. Declared input port <control<35>> was not found in the core. Please make sure that component declaration ports are consistent with the core ports including direction and bus-naming conventions. c. WARNING:Route:455 - CLK Net:Clk_OBUF may have excessive skew because 0 CLK pins and 2 NON_CLK pins failed to route using a CLK template. 24. To download your bit file, double-click on Configure Target Device. This will launch the tool ISE impact. a. Click OK. b. Double Click on Boundary Scan c. Right click and select Initialize Chain. The tool will automatically detect that there are 3 devices in the JTAG chain. If you get a cable connect error, then you need to run (as admin): C:\Xilinx\11.1\common\bin\nt\install_drivers.exe d. Click Yes. e. Select Bypass for the 2 xcf04s Proms and select top.bit and click Open for the xc3s1500 FPGA. f. On the Device Programming Properties, check Verify for the xc3s1500 and click OK. g. Right click on the 2 Proms and select Erase. You only have to do this the first time. Page 4 of 5

5 h. Right click on the xc3s1500 and click Program. The FPGA is now configured with your bit file. 25. We will use Eclipse to compile and debug the C code. Follow the tutorial at f. Set your workspace to h:\cse465\eclipsekepler and create a new C project called HelloWorld. 26. For your first project, create a C project called HelloWorld in the Eclipse Workspace that writes Hello World! one character (byte) at a time to your register and then reads it back. That is, write H to address 0x80000b00 and then read the value at address 0x80000b00. You should get and H the first time. Then write an e to the same address. Use printf to display the read value. 27. The Test output port in the top module is assigned to J24. J24.1 is Test[0], J24.2 is Test[1] and so on. J24.34 is a ground. See page 22 of and cse465\ise\proj1\top.ucf for more details. Connect D15-D0 on the oscilloscope to PWData[7:0], PSel11, PEnable and PWrite. 28. Set a breakpoint in your code after the write. Run to your breakpoint and confirm that the correct values are being written to your register. Capture the write cycle of the W character using the ScopeCapture program with the Agilent toolbar in Word (on the Add-In tab). 29. Now, click on Analyze Design Using ChipScope to reprogram the FPGA using ChipScope and display the Write/Read cycle of the character W. See df for more details. 30. Go back and modify APBBusMaster.v to generate a write cycle for the character W followed by a read and re-run the simulations. Verify that the scope output and the simulations match. 31. Turn in a printout of a Write/Read cycle of the character W from both ChipScope and from the Modelsim simulations and the Write cycle from the oscilloscope. Page 5 of 5