A Flexible Programmable Memory BIST for Embedded Single-Port Memory and Dual-Port Memory

Transcription

1 A Flexible Programmable Memory BIST for Embedded Sigle-Port Memory ad Dual-Port Memory Yougkyu Park, Hog-Sik Kim, Ihyuk Choi, ad Sugho Kag Programmable memory built-i self-test (PMBIST) is a attractive approach for testig embedded memory. However, the mai difficulties of the previous works are the large area overhead ad low flexibility. To overcome these problems, a ew flexible PMBIST (FPMBIST) architecture that ca test both sigle-port memory ad dual-port memory usig various test algorithms is proposed. I the FPMBIST, a ew istructio set is developed to miimize the FPMBIST area overhead ad to maximize the flexibility. I additio, FPMBIST icludes a diagostic scheme that ca improve the yield by supportig three types of diagostic methods for repair ad diagosis. The experimet results show that the proposed FPMBIST has small area overhead despite the fact that it supports various test algorithms, thus havig high flexibility. Keywords: Built-i self-test, BIST, programmable memory BIST, PMBIST, flexible PMBIST, sigle-port memory, dual-port memory. Mauscript received Oct. 2, 212; revised Mar. 6, 213; accepted Mar. 21, 213. This research was supported by the MSIP (Miistry of Sciece, ICT & Future Plaig), Korea, uder the CITRC (Covergece Iformatio Techology Research Ceter) support program (NIPA-213-H ) supervised by the NIPA (Natioal IT Idustry Promotio Agecy). Yougkyu Park (phoe: , yk76.park@samsug.com), Ihyuk Choi (ihchoi@soc.yosei.ac.kr), ad Sugho Kag (correspodig author, shkag@yosei.ac.kr) are with the Departmet of Electrical & Electroic Egieerig, Yosei Uiversity, Seoul, Rep. of Korea. Hog-Sik Kim (hogsik1.kim@sk.com) is with the Advaced Desig Group, R&D, SK Hyix Ic., Icheo, Rep. of Korea. I. Itroductio Advaces i semicoductor techology ad reuse desig methodologies have eabled may itellectual property cores, such as processor cores, large capacity embedded memory, ad mixed sigal aalog cores, to be itegrated o a sigle chip. Such itegratio is referred to as the system o chip (SoC) desig methodology. I curret SoC products, embedded memory cores occupy most of the chip area ad thus have become a key factor i the reliability of SoC devices. I additio, the limited badwidth of exteral automated test equipmet (ATE) makes the testig of embedded memory cores more difficult. Therefore, embedded memory core testig i the SoC desig eviromet has become a very importat ad time-cosumig task [1]-[3]. Sigle-port memory ad dual-port memory are widely used as embedded memory i SoC products. I sigle-port memory, the data trasactios are coducted through a sigle IO port, whereas i dual-port memory, two differet data trasactios ca be simultaeously performed through two idepedet IO ports. As such, the fault models ad test algorithms of sigleport memory are differet from those of dual-port memory. However, most of the research i the field of embedded memory testig has bee devoted to sigle-port memory [4]- [6]. The memory built-i self-test (BIST) techique is widely regarded as a optimal embedded memory test i the SoC desig eviromet sice it ca eable a at-speed test with reduced IO chael test badwidth [7], [8]. However, previously developed memory BIST methods oly support a 88 Yougkyu Park et al. 213 ETRI Joural, Volume 35, Number 5, October 213

2 limited test based o the March algorithm ad the restrictive o-march algorithm, ad, as a result, the flexibility ad fault coverage are restricted. Programmable memory BIST (PMBIST) methodologies have bee proposed to ehace the flexibility of covetioal memory BIST techiques ad to test diverse fault models [9]-[11]. Flexibility i PMBIST is defied as how various test algorithms ca be supported ad is oe of the mai cocers for PMBIST. PMBIST techiques ca improve the flexibility of covetioal memory BIST techiques to accommodate various test algorithms. However, these techiques icrease the area overhead sigificatly. The majority of research i the field of embedded memory testig has focused o sigle-port memory. However, research regardig PMBIST architecture for dual-port memory is also importat. PMBIST has tradeoffs betwee its fault coverage ad area overhead. This is because supportig various test algorithms requires a large area overhead, ad, if the umber of supported test algorithms is limited, the area overhead shriks but the fault coverage also decreases. Thus, a PMBIST architecture for both sigle-port memory ad dual-port memory is eeded. The PMBIST should be able to support various test algorithms with a small area overhead. To improve the memory yield, a diagostic test is also eeded. The diagostic data is geerated by the BIST circuit. I this work, a ew microcode-based PMBIST architecture is proposed to test both sigle-port memory ad dual-port memory. The proposed flexible PMBIST (FPMBIST) supports March-based algorithms, o-march algorithms, ad dual-port memory test algorithms. That is, all fault models for sigle-port memory ad dual-port memory ca be addressed with a sigle BIST architecture. Such a scheme allows for the groupig of sigle-port memory ad dual-port memory ito the same BIST domai so that the total BIST area ca be reduced ad so that simple test schedulig is possible. A optimized istructio set is also proposed i this study to reduce the area overhead of the programmable BIST circuitry. Furthermore, the FPMBIST desig supports three types of diagostic methods. With this diagostic scheme, the FPMBIST desig ca icrease the memory yield. II. Previous Works o PMBIST Architecture Geerally, PMBIST ca be classified ito oe of two types: fiite state machie (FSM)-based ad microcode-based. FSMbased PMBIST allows the ATE to choose a test algorithm from several predetermied FSM compoets of test algorithms. This method usually has low test complexity ad small area overhead but has relatively low flexibility ad fault coverage. O the other had, the microcode-based PMBIST is the most widely used approach. The microcode-based PMBIST saves the test algorithm i the form of istructios i iteral storage ad implemets the test algorithm usig the saved istructios. This method of PMBIST has high flexibility ad fault coverage, but the area overhead icreases sigificatly. A variety of architectures have bee proposed for PMBIST desig. The architecture i [12] ca support five groups of test algorithms: March, Gallopig/Walkig, the test for the address decoder ope, butterfly, ad slidig diagoal. The base loop ad local loop are also used to support o-march algorithms, but oly a two-level loop is supported. As a result, the programmig flexibility is restricted. The scheme i [13] upgrades the programmable BIST architecture of [12] by chagig the istructio set to support multi-loop performace, ad the architecture also supports a diagostics scheme. However, the area overhead is sigificatly icreased. The oliear PMBIST (NPMBIST) architecture i [14] was proposed to effectively test sigle-port memory ad supports both March ad o-march algorithms. The NPMBIST uses a optimized istructio set to miimize the area overhead ad supports multi-loop performace to esure the effective implemetatio of complicated test algorithms. However, NPMBIST does ot allow algorithm dowloadig from exteral ATE ad caot support such o-march algorithms as data retetio tests, butterfly, ad so o. NPMBIST ca oly geerate limited complicated addresses usig the fast diagoal method. The architecture i [15] is a microcode-based programmable BIST scheme for dual-port memory testig. The test program set cosists of 4-bit test primitives with which the microprogram for the target test algorithm is coded. The microprogram is stored i the μprogram memory. The ROM or a I-System Programmable module is used for the μprogram memory. This scheme ca partially support multi-loop performace. The scheme of [15] ca oly access the same cell through two differet ports. As such, oly oe port fault ca be tested. The architecture i [16] is a BIST scheme for dual-port memory usig the same iterface as the stadard test access port. This scheme tests the dual-port memory by geeratig test patters with trasformed test algorithms from a March-based test algorithm, such as March C or March A. I this case, oly the March-based test algorithm ca be materialized without multi-loop support, so the programmig flexibility is limited. Furthermore, it caot detect 2PF2av faults [17] because it caot write ad read simultaeously at two differet cells through two ports. III. FPMBIST I previous FSM-based MBIST schemes, fixed test patters ETRI Joural, Volume 35, Number 5, October 213 Yougkyu Park et al. 89

3 based o test algorithms (such as the March algorithm) were supported such that the fault coverage ad flexibility were restricted, eve with a smaller hardware area. I additio, differet BIST circuitries were required for sigle-port memory ad dual-port memory. Cosequetly, the total memory BIST circuit area was icreased. I this work, a ew microcode-based FPMBIST architecture is proposed that supports various test algorithms ad memory port types. The target test algorithm for the FPMBIST is programmed with microcodes based o the proposed istructio set ad is stored i the iteral memory. By decodig the microcode sequece, test patters based o the target test algorithm are geerated usig the BIST logic. The FPMBIST ca test both sigle-port memory ad dual-port memory, so memory of the same IO-type ca be grouped together ito the same test domai. The total BIST area overhead ca thus be reduced compared to covetioal BIST schemes, ad the embedded memory cores ca be scheduled i a more flexible maer. Figure 1 shows the operatig sequece of the FPMBIST for sigle-port memory ad dual-port memory. Iitially, the FPMBIST is i the Start state. I the Load_CMD state, the commads are loaded from the outside by the Commad Load (CMDL) sigals. I the Shift_CMD state, the commads are shifted to the decoder by the MTestH sigals. The FPMBIST has two istructio sets to implemet the algorithms. Therefore, the CMD decoder cosists of two types of decodig logic. If Test Algorithm Select (TAS)=, the FPMBIST will be i the Decode_LIS state, ad the CMD decoder will decode commads with the decodig logic for the liear istructio set. If TAS=1, the FPMBIST will be i the Decode_NLIS state, ad the CMD decoder will decode commads with the decodig logic for the oliear istructio set. I the Patter_Geeratio state, the test patters are geerated by cotrollig the test patter geerator (TPG) by usig sigals received from the CMD decoder. I the Target_Memory_Test state, the target memory is determied by the Test Memory Select (TMS) sigals, ad is the tested. I the Diagostic state, the fault iformatio detected by the memory test is trasmitted to the exteral ATE. This state is operated i two modes by the Diagostic data Mode Select (DMS) sigals. The purpose of the Bypass mode is to support the faulty iformatio. The purpose of the Fault Iformatio for Repair (FIR) mode is to support the fault sydrome ad addresses of faulty cells for the redudacy aalysis, ad the purpose of the Fault Iformatio for Diagosis (FID) mode is to support the diagostic data for a fault aalysis cosistig of the fault sydrome, the addresses of faulty cells, ad the patter that detected the fault. I previous dual-port memory BISTs, the testig was performed o the dual-port memory by applyig the test Liear istructio set Yes Decode_LIS Start Load_CMD Shift_CMD TAS==? Patter_Geeratio Target_Memory_Test Diagostic BIST_Ed Noliear istructio set No Decode_NLIS TMS = : Sigle-port memory test TMS = 1: Dual-port memory test DMS = : Bypass mode DMS = 1: FIR mode DMS = 1: FID mode Fig. 1. Operatig sequece of FPMBIST. stimuli through oe port ad receivig the test resposes through the other port. I additio, oe cell could be simultaeously read ad writte through differet ports. However, several fault models, such as 2PFav, caot be tested usig these schemes. The proposed FPMBIST supports covetioal BIST operatioal modes ad ca simultaeously access two differet cells through two differet ports. A istructio set is developed for the FPMBIST. A o- March algorithm, such as the Gallopig ad slidig diagoal algorithms, ad a March-based algorithm ca easily be microcoded by the istructio sets. The istructios support most of the memory test algorithms with little hardware complexity ad allow the microcode size to be optimized. I additio, the FPMBIST supports a data retetio test ad improves memory yield with the diagostic scheme. 1. Istructio Set Architecture I the proposed FPMBIST, the target test algorithm is programmed ito microcode by the istructio set, which is stored i the iteral memory. The microcode sequece is decoded ito the origial test stimuli durig the BIST test cycle. The proposed istructio set is divided ito a liear istructio set ad a oliear istructio set accordig to the target fault model. The oliear istructio set is used i the o-marchbased test of oe-port related fault models, ad the liear istructio set is employed i the March-based test of oe-port 81 Yougkyu Park et al. ETRI Joural, Volume 35, Number 5, October 213

4 Table 1. Noliear istructio set. Istructio set Ist[13:12] Ist[11] Ist[1] Ist[9] Ist[8] Ist[7] Ist[6] Ist[5] Ist[4:2] Ist[1:] Fuctio Opcode Istructio Cotrol Backgroud True/Iversio Memory Operatio Port Select Colum Output Row Output Colum Couter Row Couter Couter Cotrol Operatio Cotrol Icremet True Read A CX RX CX RX NOP NOP 1 Brach 1 Iversio 1 Write 1 B 1 CY 1 RY 1 CY 1 RY 1 CNOP 1 Y X 1 RDBrach 1 ^Row 1 X Y 11 Pause 11 ^Colum 11 Termiate 1 D ad two-port fault models. The oliear istructio set ca also support a simple dual-port memory test. The sizes of the liear ad oliear istructio sets i this study are 9 bits ad 14 bits, respectively. I additio, multi-loop performace is supported by the oliear istructio set to more easily implemet the o-march algorithm. The architectural features of the oliear istructio set are show i Table 1. A Istructio Cotrol field (Ist[13:12]) sigifies the operatioal status so that the target test algorithm ca be implemeted. The Icremet state allows the ext istructio to be ru, ad the Brach state allows the program couter to jump to the destiatio istructio. The brach operatio is performed through a brach register that also supports multiloop performace. The Retur Data iversio Brach (RDBrach) state is the commad to reru the test program through the iversio of the backgroud data, ad the Pause state is the commad to hold the istructio durig a set time to detect a retetio fault. The Backgroud True/Iversio field (Ist[11]) determies the backgroud data type. If this bit is, the backgroud data fields are filled with ; otherwise, they are filled with 1. The Memory Operatio field (Ist[1]) defies the memory access type. If this field is, the read operatio is performed; otherwise, the write operatio is performed. The Port Select field (Ist[9]) selects the memory port to be accessed. This bit allows the o-march algorithm that is implemeted by the oliear istructio set to be applied to the dual-port memory test. The Colum Output field (Ist[8]) selects the memory test colum address betwee colum couter X ad colum couter Y. The Row Output field (Ist[7]) selects the memory test row address betwee row couter X ad row couter Y. The Colum Couter field (Ist[6]) activates the colum address couter (icremeted/ decremeted) betwee colum couter X ad colum couter Y for the geeratio of the memory test colum address. The Row Couter field (Ist[5]) activates the row address couter for the geeratio of the memory test row address. The colum address ad the row address geerate oe address. The Ist[8], Brach 1 Brach 2 Brach 3 RDBrach 4 Fig. 2. Test patters of Gallopig algorithm. Istructio # Icremet Brach RDBrach Pause Backgroud True Backgroud Iversio Memory Operatio (read) Memory Operatio (write) Port Select (A port) Port Select (B port) Colum Output (CX) Colum Output (CY) Row Output (RX) Row Output (RY) Colum Couter (CX) Colum Couter (CY) Row Couter (RX) Row Couter (RY) Couter Cotrol (NOP) Couter Cotrol (CNOP) Couter Cotrol (^Row) Couter Cotrol (^Colum) Couter Cotrol (D) Istructio Cotrol (NOP) Istructio Cotrol (Y<-X) ~ Patter ~ Patter Istructio Cotrol (X<-Y) Istructio Cotrol (termiate) Fig. 3. Materializatio of Gallopig algorithm usig a oliear istructio set. # Brach register Brach address 1 1 Ist[7], Ist[6], ad Ist[5] sets are used for multi-loop performace so that a complex address sequece ca be geerated for the o-march algorithms. The Couter Cotrol field (Ist[4:2]) desigates the couter optio. The NOP state meas o operatio. The CNOP state is a optio for Ist[5] ad Ist[4] to maitai the curret value without coutig the ETRI Joural, Volume 35, Number 5, October 213 Yougkyu Park et al. 811

5 Table 2. Liear istructio set. Istructio set Ist[8:7] Ist[6] Ist[5] Ist[4] Ist[3] Ist[2] Ist[1:] Fuctio Opcode Istructio Cotrol Up/Dow A Port Backgroud True/Iversio A Port Memory Operatio B Port Backgroud True/Iversio B Port Memory Operatio Operatio Cotrol Icremet Up True Read True Read NOP 1 Brach 1 Dow 1 Iversio 1 Write 1 Iversio 1 Write 1 Row 1 RDBrach 1 Colum 11 Pause 11 Termiate colum address couter ad the row address couter. The ^Row ad ^Colum optios of Ist[4:2] are used to support the diagoal, fast row, ad fast colum methods. ^Row ad ^Colum are coditioal arithmetic fuctios for fast diagoal addresses. The ^Row is a fuctio for arithmetic operatios that icreases the row addresses ifiitely. The ^Colum is a fuctio for arithmetic operatios that icreases the colum addresses ifiitely. The basic method of address geeratio is the fast diagoal method. The D states are the optios to icrease ad decrease the address as much as the value saved at the D register whe the address was geerated. These optios are used to materialize such algorithms as the butterfly algorithm. The Operatio Cotrol field (Ist[1:]) desigates the istructio optio. The NOP state meas o operatio. The X Y ad Y X states are the optios to geerate addresses by exchagig the values of the X couter ad the Y couter. By cotrollig the four couters, a complex address sequece based o the o-march algorithms ca easily be geerated. I additio, a simple dual-port memory test is supported through the port selectio bit. Show i Fig. 2 are test patters based o the Gallopig algorithm, a oliear March algorithm. A represetative implemetatio of the Gallopig algorithm via a oliear istructio set is show i Fig. 3. To implemet the March-based test algorithms, the liear istructio set icludes istructios with a fixed legth of 9 bits. Dual-port memory tests based o the March algorithms are also supported through the liear istructio set. Therefore, various memory operatios ad features for each IO port ca be implemeted with the liear istructio set. The basic method that is used to geerate the address of the liear istructio set is the fast diagoal method. The architecture ad the features of the liear istructio set are show i Table 2. The Istructio Cotrol field (Ist[8:7]) of the liear istructio set is equivalet to its couterpart (Ist[13:12]) i the oliear istructio set. The Up/Dow field (Ist[6]) determies the directio of the address geeratio for the March ad dual-port memory algorithms. The Backgroud True/Iversio field (Ist[5]) determies the backgroud data Istructio # Icremet Brach RDBrach Pause Up Dow A Port Backgroud True Brach Brach RDBrach Brach RDBrach Brach A Port Backgroud Iversio A Port Memory Operatio (read) A Port Memory Operatio (write) Cotrol (NOP) Cotrol (Row) Cotrol (Colum) Cotrol (termiate) Brach register # Brach address Fig. 4. Materializatio of March A2PF algorithm usig liear istructio set. B Port Backgroud True B Port Backgroud Iversio B Port Memory Operatio (read) B Port Memory Operatio (write) type for Port A. The A Port Memory Operatio field (Ist[4]) defies the memory access type for Port A. If this field is, a read operatio is performed; otherwise, a write operatio is performed. The Backgroud True/Iversio field (Ist[3]) determies the backgroud data type for Port B. The B Port Memory Operatio field (Ist[2]) defies the memory access type for Port B. To test oe-port faults, the Ist[3] ad Ist[2] bits are fixed at a logic value of so that the test geeratio for Port B ca be deactivated. The Operatio Cotrol field (Ist[1:]) sigifies the istructio optio that is geerally used for the testig of dual-port memory. Durig the dual-port memory test, write operatios are performed o a cell through oe port, while read operatios are performed o a eighborig cell i the same colum (or the same row) through the other port. As a example, for Ist[1:]= 1, the port address for the read operatio is geerated i the adjacet directio of the colum. The liear istructio set uses a smaller umber of bits tha the previous istructio sets whe implemetig March-based algorithms. For example, i a March stage such as (r1, w, 812 Yougkyu Park et al. ETRI Joural, Volume 35, Number 5, October 213

6 r); or (r, w1, r1);, six March elemets (r1, w, r, r, w1, ad r1) are implemeted by six istructios of the previous istructio set, but the liear istructio set is implemeted i four istructios. This is possible because of the RDBrach state i Ist[8:7] of the liear istructio set. Therefore, the March A2PF algorithm of 18N [18] is implemeted with 12 istructios, ivolvig a reductio of six istructios. Figure 4 shows the materializatio of the March A2PF algorithm with the liear istructio set. 2. FPMBIST Architecture I this study, a ew advaced PMBIST architecture ad test algorithm are proposed to test both sigle-port memory ad dual-port memory. The FPMBIST supports algorithm dowloadig from the exteral ATE so that sigle-port memory ad dual-port memory ca be tested via TMS ad TAS. A block diagram of the proposed FPMBIST desig is show i Fig. 5. The FPMBIST architecture cosists of the BIST cotroller (BCTR), TPG, ad diagostic data processig module (DPM) blocks. The BCTR block reads istructio codes from the istructio memory ad coveys them to the TPG block. I additio, the BCTR cotrols the FPMBIST via the iput ports, such as CMDL, TMS, TAS, DPS, Pause Time Select (PTS), ad MTestH. The TPG block geerates the test address, test data, ad test cotrol patters based o the istructio codes ad cotrol sigals from the BCTR block. The DPM block trasforms the fault iformatio that was obtaied by coductig the memory tests ito diagostic data ad provides it to the exteral ATE for repair or diagosis. The iput sigals of the FPMBIST iclude BIST Reset Sigal (BRS), MTestH, TMS, CMDL, TAS, DMS, PTS, ad CMD. The MTestH sigal forces the FPMBIST to eter test mode. The CMDL sigal forces the FPMBIST to eter program mode, where the istructio code sequece is stored i the iteral istructio memory from the exteral ATE. The TMS sigal coveys the memory type to be tested. If TMS is, the target is sigle-port memory; otherwise, the target is dual-port memory. The TAS sigal determies the istructio set type of the curret istructios. If TAS is, the the istructios belog to the liear istructio set for the Marchbased ad dual-port memory test algorithm; otherwise, the istructios belog to the oliear istructio set for the o- March algorithm. Through the use of both TMS ad TAS, the target memory port type ad the test algorithm are determied. BRS is the reset sigal for FPMBIST, while the CMD sigal receives istructio codes from the ATE. The DMS sigal is used to select the type of diagostic data to be provided to the exteral ATE. The PTS sigal is etered from the ATE for data retetio tests. The BIST Fiish Sigal (BFS) is a output pi that is used to idicate that the BIST operatio is fiished. BIST Fault Out (BFO) is a output that is used to sed the diagostic data to the ATE. As show i Fig. 5, the BCTR block cotrols the FPMBIST operatios ad the flow of istructios. The BCTR block cosists of a CMD block, CMD cotroller, ad FPMBIST cotroller. The FPMBIST cotroller cotrols the FPMBIST based o the iput sigals from the exteral ATE ad cotrols the ability of the CMD block to read ad store the istructios from the ATE to the iteral istructio memory durig the program mode. The FPMBIST cotroller also cotrols each BCTR TPG CLK BRS CMDL CMD o MTestH TMS TAS DMS 2 PTS DVS BFO BFS CMD loader CMD block Istructio 1 Istructio 2 Istructio 3 Istructio 4 Istructio memory Istructio 19 Istructio 2 PMBIST cotroller P-to-S DPM cotroller Bypass module CMD cotroller Brach register FIR/FID module CMD decoder CMD op. selector Cotrol sigal geerator geerator Data geerator Comparator I/O selector oe_a web_a csb_a addr_a m data_i/o_a oe_b web_b csb_b addr_b m data_i/o_b oe web csb addr m data_i/o Dual-port memory Sigle-port memory Diagostic data processig module (DPM) Fig. 5. FPMBIST architecture. ETRI Joural, Volume 35, Number 5, October 213 Yougkyu Park et al. 813

7 iteral block so that test patters ca be geerated durig the test mode. The CMD block loads ad stores the istructio codes from the exteral ATE to the iteral istructio memory. The CMD cotroller reads ad seds the istructio sequece from the istructio memory to the CMD decoder i the TPG block. The CMD cotroller has a brach register that stores brach addresses to effectively cotrol the braches of the istructios. The istructio sets geerate complex patters by simply exploitig the multi-loops through the brach register. The test patters are geerated i the TPG block ad are applied to the large-capacity memory. A pass/fail test is the performed ad the results are determied. The TPG block cosists of a CMD decoder, cotrol sigal geerator, address geerator, data geerator, comparator, ad IO selector. The CMD decoder iterprets the istructios from the istructio memory ad geerates the test patter iformatio for the test geerators (cotrol sigal geerator, address geerator, ad data geerator). The istructios from the CMD block are received ad iterpreted by the CMD decoder, which icludes a CMD operatio selector circuit to determie the istructio type (liear ad oliear istructio sets). The CMD decoder the iterprets the istructios accordig to the correspodig istructio type. The cotrol sigal geerator produces memory cotrol sigals, while the data geerator geerates memory test data based o the istructio decodig results. The address geerator produces a test address, ad the comparator determies the test results by comparig the test respose data from the target memory with the test referece data from the data geerator. The cotrol sigal, address, ad data geerators ca geerate both sigle-port memory ad dual-port memory test patters. The IO selector determies the output ports of the test patters accordig to the target memory. The TPG of the proposed FPMBIST icludes a address geerator to support diverse methods (fast diagoal, fast row, ad fast colum) for the complex address sequece geeratio of diverse algorithms. The address geerator cosists of two couters to support a two-level loop, as show i Fig. 6. The address icremet ad decremet sequeces are sufficiet for most March algorithms. However, for o-march algorithms, the address sequeces are geerated through diverse loops; cosequetly, a sigle couter caot support address geeratio. Therefore, the proposed address geerator idepedetly exploits two couters (the X ad Y couters) to easily geerate a complex address sequece. Each couter cosists of a colum couter ad a row couter, ad it icludes a D register that ca cout to the specified value. The D register desigates the values at the BIST cotroller. I additio, various coutig offsets ca be set by the ATE to geerate diverse address sequeces. ct_i_x D_reg_i ct_i_y fault_ out f D Reg. Y_i_Sel ^Colum_X ^Row_X Colum couter Colum couter Couter X Couter Y Row couter Row couter X_i_Sel ^Colum_Y ^Row_Y O_Sel_X/Y Fig. 6. geerator. Parallelto-serial DPM cotroller Bypass mode Bypass module Fail moitor Mode cotrol Operatio FIR/FID mode Fig. 7. Diagostic data processig module. ct_out DPM_mode 2 fault_i patter_ifo. 5 addr Figure 7 shows the simplified block diagram of the DPM desig. The DPM block geerates the diagostic data usig the memory test results received from the TPG. The DPM block supports three types of diagostic methods: bypass, FIR, ad FID. The bypass method is a mode to support the fault iformatio of 1 bit whether the memory is faulty or ot. If a fault is detected, a 1 will be show; if o fault is detected, a will be show. FIR is a mode that supports fault address iformatio for redudacy aalysis. FIR supports the fault sydrome ad the address iformatio for faulty memory cells. FID is a mode to support detailed diagostic iformatio for a fault aalysis. FID s diagostic data cosists of the fault sydrome, the fault cell address, ad the patter that detected the fault. Sice the backgroud data is selected by the ATE, backgroud data iformatio is ot ecessary. The DPM modifies the diagostic data created i the FIR ad FID modes ito serial data by usig a parallel-to-serial circuit ad the serially outputs the data to the exteral ATE. Figure 8 shows the diagostic data formats of the FIR ad FID. The FIR format cosists of two fields: the fault sydrome ad the fault address. The FID format cosists of three fields: the fault detectig patter, the fault sydrome, ad the fault address. The fault sydrome is the fault data iformatio of faulty cells. The fault address is the address of the faulty cell. 814 Yougkyu Park et al. ETRI Joural, Volume 35, Number 5, October 213

8 Fault sydrome Fault address dm d a a Fault detectig patter (a) FIR mode Fault sydrome (b) FID mode Fault address i4 i dm d a a Fig. 8. Diagostic data format of FIR ad FID. The fault detectig patter reports the read operatio i the test algorithm that detected the fault. IV. Implemetatio ad Verificatio To evaluate the proposed FPMBIST, the FPMBIST architecture is implemeted usig the Samsug embedded sigle-port SRAM (16.3 K 16) ad dual-port SRAM (8.2 K 32) [19], which ca be used for SoC desigs. The target sigle-port memory is a SRAM with a 7-bit row address, a 7-bit colum address, ad a 16-bit data word. The target dualport memory is a SRAM with a 9-bit row address, a 4-bit colum address, ad a 32-bit data word. I additio, various memory test algorithms for sigle-port memory testig (March Y, March C+, March SS, Walkig, ad Gallopig) ad dualport memory testig (March s2pf, March A2PF) are microprogrammed via the proposed istructio set. The proposed FPMBIST scheme is desiged with Verilog HDL ad is sythesized usig a Syopsys Desig Compiler with TSMC.13-μm CMOS techology. The istructio bit size of the proposed istructio set that is used to geerate the test patters is show i Table 3. The istructio set does ot require as may istructios as the umber of March elemets whe it implemets March-based algorithms. For example, the March C+ algorithm of 14N requires 1 istructios to implemet algorithms with liear istructio sets. This is possible because of the RDBrach fuctio. Accordigly, the March C+ algorithm requires 9 bits (1 9 bits) of istructio memory. The March s2pf ad March SS algorithms [2] are implemeted with ie istructios ad fourtee istructios, respectively, from the liear istructio set. The Gallopig algorithm was implemeted with oly seve istructios from the oliear istructio set. The oliear istructio set geerates complex patters by simply exploitig the two-level loop of the address geerator ad the multiple loops through the brach register. The FPMBIST geerates test patters usig the istructio codes stored i the iteral istructio memory. The sizes of the codes determie the total BIST area overhead. Sice most of the covetioal memory test algorithms ad the proposed Table 3. Istructio bit sizes for test algorithm. Algorithm Istructio set Istructio set size Istructio bit Gallopig Butterfly March Y (8N) March C+ (14N) March SS (22N) March s2pf (14N) March A2PF (18N) Areas (Gates) 3, 2,5 2, 1,5 1, 5 PMBIST cotroller CMD block Noliear istructio set Noliear istructio set Liear istructio set Liear istructio set Liear istructio set Liear istructio set Liear istructio set CMD cotroller CMD decoder geerator 14 bits 98 bits 14 bits 14 bits 9 bits 54 bits 9 bits 9 bits 9 bits 126 bits 9 bits 81 bits 9 bits 18 bits Fig. 9. Areas of differet compoets of FPMBIST architecture. Data geerator Cotrol sigal geerator Compoets of SPMBIST dual-port memory test algorithms are ecoded with fewer tha 3 istructios, the istructio memory size is 7 bytes (14 bits 4). Accordig to the sythesis results, the hardware area (or gate cout) of the proposed FPMBIST with a 7-byte istructio memory is estimated to be 7,942 gates, ad the maximum operatig frequecy is calculated to be 4 MHz. A performace compariso of the proposed FPMBIST ad previous microcode-based PMBIST schemes is also show i Table 4. The architectures from [12]-[14] are programmable memory BIST schemes for sigle-port memory testig, whereas the schemes from [15] ad [16] are iteded for dualport memory testig. The area overhead of each iteral block of the PBIST is show i Fig. 9. The CMD block, address geerator, ad DPM occupy about 67.5% of the total hardware area. The address geerator occupies a large area because it requires a complex couter architecture. The diagostic module also occupies Comparator I/O selector DPM ETRI Joural, Volume 35, Number 5, October 213 Yougkyu Park et al. 815

9 Target test algorithm Target memory Table 4. Performace compariso. [12] [13] [14] [15] [16] FPMBIST Sigle-port memory Y Y Y Y Y Y Dual-port memory N N N Y Y Y March-based algorithm Y Y Y Y Y Y No-March Gallopig, slidig diagoal Y Y Y N N Y algorithm Butterfly N Y N N N Y Dual-port memory test algorithm N N N Y Y Y Data retetio fault test N N N N N Y Fast diagoal Y Y Y Y Y Y geeratio Fast row N N N N N Y methods Fast colum N N N N N Y Flexibility Medium High High Medium Medium Very high Multi-loop N Y Y P N Y Maximum frequecy NA NA 3 MHz NA NA 4 MHz Diagostic Fault iformatio Y Y N N N Y scheme Efficiecy Medium Medium NA NA NA High Istructio set architecture Materializatio of test algorithm Liear istructio set size (bit) NA Noliear istructio set size (bit) 14 Istructio bits of March Y (bit) NA 54 Istructio bits of March C+ (bit) NA 9 Istructio bits of March SS (bit) NA 117 Istructio bits of March s2pf (bit) NA NA NA 216 NA 81 Istructio bits of March A2PF (bit) NA NA NA NA NA 99 Istructio bits of Walkig (bit) NA NA 9 NA NA 84 Istructio bits of Gallopig (bit) NA NA 18 NA NA 98 Area overhead (gate) 8.9 K 13.6 K 6.4 K 9.9 K NA 7.9 K Y: support, N: ot support, P: partially support, NA: ot available about 12.6% of the area overhead. Table 4 shows a compariso of the proposed scheme ad previous programmable BIST schemes i terms of the testable memory types, supportable test algorithm, istructio size, ad the istructio memory requiremets. I Table 4, March C+ is used for the sigle-port memory test, whereas March s2pf is employed for the dual-port memory test. The hardware areas of the proposed scheme ad of the previous architectures are also displayed i Table 4. The architectures i [12] ad [13] ca support March ad o-march algorithms; however, the scheme i [12] caot ecode all o-march algorithms sice multi-loop is ot supported. The scheme i [13] ca support multi-loop performace, but the hardware area is too large. The architecture i [14] supports both March ad some o-march algorithms. The scheme i [14], which supports the Gallopig algorithm, requires 18 bits of istructio memory. It also supports multi-loop performace ad reduces the area overhead. The schemes i [12] ad [13] iclude diagostic logic with gate couts of.3 K ad 1.2 K, respectively. However, the diagostic logic supports oly the failig memory address ad the fail-map data as fault iformatio, ad thus a accurate fault aalysis is ot possible. Also, the PMBIST schemes i [12]-[14] ca oly test sigle-port memory, ot dual-port memory. The architectures i [15] ad [16] ca ecode all March algorithms ad portios of the dual-port memory test algorithms. The schemes of [15] ad [16] caot ecode the A2PF algorithm ad ca oly access the same cell through two differet ports. Therefore, it is ot possible to detect all faults i dual-port memory. I additio, o-march algorithms for sigle-port memory caot be programmed; thus, the fault 816 Yougkyu Park et al. ETRI Joural, Volume 35, Number 5, October 213

10 coverage is costraied. The proposed FPMBIST ca ecode all March ad o- March algorithms for both sigle-port memory ad dual-port memory. I additio, sice multi-loop performace is supported, complex algorithms ca be efficietly programmed. To ecode the March C+ (14N), March s2pf (16N), ad Gallopig algorithms, 9-bit, 81-bit, ad 98-bit istructio memory is required, respectively, through the liear ad oliear istructio sets. The oliear istructio set (14 bits) has five more bits tha the istructio set (9 bits) proposed i [14]. However, it uses 1 fewer bits to implemet the Gallopig algorithm. Furthermore, it ca effectively implemet diverse o-march algorithms ad it ca support data retetio tests ad so o. As a result, the memory sizes are cosiderably smaller tha those i previous PMBIST schemes. The implemetatio results reveal that the hardware area of the proposed scheme is the smallest. The proposed FPMBIST ca test both sigle-port memory ad dual-port memory ad ca support various test algorithms i a small hardware area. I additio, sice memory of the same port type ca be grouped ito oe BIST test domai with the proposed FPMBIST scheme, various embedded memory cores ca easily be tested with relatively smaller area overhead ad shorter test applicatio times. Furthermore, the FPMBIST has a efficiet diagostic module that supports the bypass, FID, ad FIR methods for repair ad diagosis. The diagostic module improves memory yield by effectively supportig diverse diagostic data to the exteral ATE. V. Coclusio A ew microcode-based flexible programmable BIST scheme was proposed to ecode various algorithms for memory of differet port types. The liear ad oliear istructio sets were also developed to support all Marchbased algorithms, dual-port memory test algorithms, ad o- March-based algorithms for both sigle-port memory ad dual-port memory. I additio, the FPMBIST supports the data retetio test. Due to the efficiet address geerator architectures ad the use of diverse address geeratio methods (fast diagoal, fast row, ad fast colum), the istructio sets ca reduce the istructio memory requiremet ad reduce the BIST hardware area. The diagostic module improves memory yield by effectively supportig diverse fault iformatio for repair ad diagosis. Accordig to the experimet results, the proposed FPMBIST scheme ca esure more flexible programmability for various test algorithms ad a smaller istructio memory requiremet ad is able to support memory of diverse port types i a small hardware area. Refereces [1] Y. Zoria, E.J. Mariisse, ad S. Dey, Testig Embedded- Core-Based System Chips, IEEE Comput., vol. 32, issue 6, 1999, pp [2] W.L. Wag, K.J. Lee, ad J.F. Wag, A O-Chip March Patter Geerator for Testig Embedded Memory Cores, IEEE Tras. Very Large Scale Itegr. Syst., vol. 9, issue 5, 21, pp [3] A. va de Goor et al., Low-Cost, Customized ad Flexible SRAM MBIST Egie, Proc. It. Symp. Desig Diagostics Electro. Circuits Syst., 21, pp [4] K. Zarrieh, S.J. Upadhyaya, ad S. Chakravarty, A New Framework for Geeratig Optimal March Tests for Memory Arrays, Proc. It. Test Cof., Oct. 1998, pp [5] S. Hamdioui, Z. Al-Ars, ad A.J. va de Goor, Testig Static ad Dyamic Faults i Radom Access Memories, Proc. VLSI Test Symp., Apr. 22, pp [6] A. va de Goor et al., Geeric, Orthogoal ad Low-cost March Elemet Based Memory BIST, Proc. IEEE It. Test Cof., 211, pp [7] C. Cheg et al., BRAINS: A BIST Compiler for Embedded Memories, Proc. IEEE It. Symp. Defect Fault Tolerace VLSI Syst., Oct. 2, pp [8] K. Yamasaki et al., Exteral Memory BIST for System-i- Package, Proc. It. Test Cof., Nov. 25, pp [9] A.W. Hakmi et al., Programmable Determiistic Built-I Self- Test, Proc. IEEE It. Test Cof., Oct. 27, pp [1] N.Q. Mohd Noor, A. Saparo, ad Y. Yusof, A Overview of Microcode-Based ad FSM-Based Programmable Memory Built-i Self-Test (MBIST) Cotroller for Couplig Fault Detectio, Proc. IEEE Symp, Id. Electro. Appl., Oct. 29, pp [11] H.C. Lu ad J.F. Li, A Programmable Olie/Off-lie Built-i Self-Test Scheme for RAMs with ECC, Proc. It. Symp. Circuits Syst., May 29, pp [12] X. Du et al., Full-Speed Field-Programmable Memory BIST Architecture, Proc. IEEE It. Test Cof., Nov. 25, pp [13] X. Du et al., A Field Programmable Memory BIST Architecture Supportig Algorithms with Multiple Nested Loops, Proc. IEEE Asia Test Symp., Nov. 26, pp [14] Y. Park et al., A Effective Programmable Memory BIST for Embedded Memory, IEICE Tras. If. Syst., vol. E92-D, o. 12, Dec. 29, pp [15] A. Beso et al., A Programmable BIST Architecture for Clusters of Multiple-port SRAMs, Proc. IEEE It. Test Cof., Oct. 2, pp [16] M. Karuarate ad B. Oomma, Optimized BIST for Embedded Dual-Port RAMs, Proc. IEEE Midwest Symp. ETRI Joural, Volume 35, Number 5, October 213 Yougkyu Park et al. 817

11 Circuits Syst., Aug. 21, pp [17] S. Hamdioui ad A.J. va de Goor, Efficiet Tests for Realistic Faults i Dual-Port SRAMs, IEEE Tras. Comput., vol. 51, issue 5, 22, pp [18] Y. Park et al., A Effective Test ad Diagosis Algorithm for Dual-Port Memories, ETRI J., vol. 3, o. 4, Aug. 28, pp [19] Samsug.13 μm Geeric Process Compiled Memory (STD15E), Data Book of Samsug Electroics, May 25. [2] S. Hamdioui, A.J. va de Goor, ad M. Rodgers, March SS: A Test for All Static Simple RAM Faults, Proc. IEEE It. Workshop Memory Techol., Desig, Testig, July 22, pp Sugho Kag received his BS i cotrol ad istrumetatio egieerig from Seoul Natioal Uiversity, Seoul, Rep. of Korea, ad his MS ad PhD i electrical ad computer egieerig from the Uiversity of Texas at Austi, Austi, TX, USA, i He was a research scietist with the Schlumberger Laboratory for Computer Sciece, Schlumberger Ic., ad a seior staff egieer with Semicoductor Systems Desig Techology, Motorola Ic. Sice 1994, he has bee a professor i the Departmet of Electrical ad Electroic Egieerig, Yosei Uiversity, Seoul, Rep. of Korea. His mai research iterests iclude VLSI/SOC desig ad testig, desig for testability, ad desig for maufacturability. Yougkyu Park received his B.S. degree i electroics egieerig from Hoseo Uiversity, Rep. of Korea, i 24 ad his M.S. ad Ph.D. degrees i electrical ad electroics egieerig from Yosei Uiversity, Seoul, Rep. of Korea, i 27 ad 213, respectively. From 213, he was a seior egieer with Memory Divisio, Samsug Electroics Compay, Rep. of Korea. His curret research iterests iclude VLSI desig ad testig, memory BIST, ad desig for testability. Hog-Sik Kim received his BS, MS, ad PhD degrees i electrical ad electroics egieerig from Yosei Uiversity, Seoul, Rep. of Korea, i 1997, 1999, ad 24, respectively. I 25, he was a postdoctoral fellow with the Virgiia Istitute of Techology, Blacksburg, VA, USA. I 26, he was a seior egieer with System LSI Group, Samsug Electroics Compay, Rep. of Korea. From 27 to 21, he was a research professor with Yosei Uiversity. Sice 21, he has bee a seior egieer with SK Hyix Semicoductor. His curret research iterests iclude desig for testability, lossless data compressio, 3-D graphics rederig hardware desig, ad ew memory/storage subsystems. test ad validatio. Ihyuk Choi received his BS i electrical ad electroics egieerig from Yosei Uiversity, Seoul, Rep. of Korea, i 29. Curretly, he is workig toward a combied MS/PhD i electrical ad electroics egieerig at Yosei Uiversity. His research iterests iclude SoC desig, desig for testability, ad system-level 818 Yougkyu Park et al. ETRI Joural, Volume 35, Number 5, October 213