Self-Test Methodology for At-Speed Test of Crosstalk in Chip Interconnects

Transcription

1 Self-Test Methodology for At-Speed Test of Crosstalk i Chip Itercoects Xiaoliag Bai Departmet of ECE Uiversity of Califoria, Sa Diego xibai@ece.ucsd.edu Sujit Dey Departmet of ECE Uiversity of Califoria, Sa Diego dey@ece.ucsd.edu Jausz Rajski Metor Graphics Corporatio Wilsoville, OR jausz_rajski@metorg.com * Abstract The effect of crosstalk errors is most sigificat i highperformace circuits, madatig at-speed testig for crosstalk defects. This paper describes a self-test methodology that we have developed to eable o-chip at-speed testig of crosstalk defects i System-o-Chip itercoects. The self-test methodology is based o the Maximal Aggressor Fault Model [13], that eables testig of the itercoect with a liear umber of test patters. To eable self-testig of the itercoects, we have desiged efficiet o-chip test geerators ad error detectors to be embedded i ecessary cores; while the test geerators geerate test vectors for crosstalk faults, the error detectors aalyze the trasmissio of the test sequeces received from the itercoects, ad detect ay trasmissio errors. We have also desiged test cotrollers to iitiate ad maage test trasactios by activatig the appropriate test geerators ad error detectors, ad havig error diagosis capability. We have developed, simulated, ad sythesized parameterized HDL models of the selftest structures. We have applied the self-test methodology to test crosstalk defects i the buses of a DSP chip. Usig a ew highlevel crosstalk simulatio techique, we have validated the selftest methodology, icludig the self-test structures iserted i the DSP chip. 1. Itroductio Use of ao-meter techologies i System-o-Chips (SoC) icreases cross-couplig capacitace ad iductace betwee itercoects, leadig to severe crosstalk effects that may result i improper fuctioig of the chip. Several desig techiques, icludig physical desig [1][2] ad aalysis tools [3][4][5], are beig developed to help desig for margi ad miimize crosstalk problems. However, the amout of over desig may be prohibitive. Moreover, it is impossible to aticipate i advace the full rage of process variatios, ad maufacturig defects may sigificatly aggravate the cross-couplig effects. Hece, there is a critical eed to develop testig techiques for maufacturig defects that may produce crosstalk effects. Cross-couplig betwee a pair of itercoects ca result i two differet crosstalk effects: a glitch, or a delayed trasitio, depedig o the ature of sigal trasitios at the itercoects, show i Figure 1(a) ad 1(b) respectively. I additio to glitches ad delays, presece of sigificat couplig iductace ca result * This work is supported by the Semicoductor Research Corporatio uder Cotract #98-TJ-648 z z z Figure 1 - (a) Glitch, (b) Delay, ad (c) Oscillatios i damped voltage oscillatios superimposed o top of a glitch or delay, as illustrated i Figure 1(c). If the dampig is large eough, the effects of this third case may be approximated by oe of the first two cases. I this paper, we focus o testig for couplig capacitace iduced glitch ad delay errors. Sice the crosstalk effects will be most evidet i highfrequecy chips, it is importat to be able to test such chips at the operatioal speed of the system. However, as described i the 1999 ITRS [6], while ASIC speeds have improved at 3% per year, exteral testers accuracy for timig sigal resolutio at ASIC pis have improved oly at a rate of 12 % per year. Moreover, due to demads for higher speed, icreased pi cout, icreased memory, ad greater accuracy alog with mixed digital ad aalog sigals, the test equipmet cost ca rise toward US $2 M. Hece, to facilitate at-speed testig, as well as circumvet the prohibitively risig cost of exteral ATEs, we address the problem of self-testig for crosstalk i System-o-Chip itercoects. Empirical data has show that crosstalk effects are most sigificat i log itercoects [3][13]. With the sharply icreasig umber of compoets ad cores i a sigle chip, global itercoects will domiate future System-o-Chips. Figure 2 shows a example system chip. It comprises of several cores, C1-C12, ad several bus structures, both iteral to cores as well as at the system-level. Iside each compoet, like the CPU core C1 show i Figure 2, the blocks like the ALU, multiplier, shifter, istructio decode uit ad program couter commuicate through umerous buses. At the system-level, the cores commuicate usig a hierarchy of buses, havig differet badwidth, speed, power ad other characteristics, as well as umerous core-core itercoects, like the itercoects betwee the MPEG decoder ad iterface core show i Figure 2. Cosequetly, we focus o eablig at-speed testig of Systemo-Chip itercoects, like buses ad other iter-core wires. Our self-test methodology ivolves isertig self-test structures, like test geerators ad error detectors i appropriate cores, ad a global test cotroller, to coordiate the self-test of the SoC itercoects, as show i Figure 2. Several crosstalk extractio ad aalysis methods [4][5] have bee recetly developed; while useful for desig validatio, they caot be used for maufacturig testig, ad the geeratio of the simulatio vectors is ot clear. Research has also started i test patter geeratio for crosstalk oise [7][8]. The techiques have focused o test geeratio for glitches ad delay faults itroduced by cross-couplig capacitace i gate level circuits, ad are ot applicable to test SoC itercoects. Moreover, while several self-testig techiques, icludig Built-I Self-Test (BIST), have bee developed for other maufacturig defects ad

2 faults, like stuck-at ad delay faults, o effort has bee reported to eable at-speed testig of cross-couplig defects, icludig ay self-test techiques for crosstalk. Our self-test methodology of SoC itercoects is based o the Maximal Aggressor Fault Model that was reported ad validated i [13]. We will ext briefly review the itercoect fault model, ad the correspodig test trasitios that are required to test the itercoect faults. 1.1 Itercoect Crosstalk Fault Model ad Tests If the cross-couplig problem has to be cosidered at the process level, the umber of possible process variatios ad defects that eed to be cosidered ca be extesive eve for a pair of itercoects. For wide buses, cosiderig all such variatios explicitly is clearly prohibitive. At the circuit level, a courser mesh of lumped circuit elemets ca describe the cumulative effect of process variatios behaviorally, but the resultig fault space is still too large. Hece, the eed for a abstract fault model which will cover all the crosstalk defects with a small umber of faults. The Maximal Aggressor Fault Model (MAFM), is a high level represetatio of all the physical defects ad process variatios that lead to oe of the four crosstalk errors, positive glitch(g p ), egative glitch (g ), risig delay (d r ), fallig delay(d f ), o the victim wire of the set of itercoects uder test [13]. All the other wires are desigated aggressors, ad act collectively to geerate the glitch or delay error o the victim. Figure 3 shows the trasitios eeded o the aggressor/victim itercoects to produce the four error types o victim wire. These are the uique Maximal Aggressor tests that are eeded for the correspodig four crosstalk faults for victim Test for g p Self-Test Structures Test for g Test for d f Test for d r Figure 3 Vectors, victim ad aggressors of MAF model For a set of N itercoects to be tested, a total of 4N faults eed to be tested, requirig 4N 2-patter tests. Note that these 4N faults cover all the possible physical defects ad process variatios that ca lead to ay crosstalk error effect o ay of the N itercoects. Hece, a Maximal Aggressor (MA) test set for all the MAFM faults will cover all the crosstalk defects affectig the N itercoects. Sice the required MA tests are kow a-priori, if self-test structures ca be iserted i the SoC to geerate all the required MA tests, the resultig self-test methodology will be able to perform o-chip at-speed testig of SoC itercoects, with 1% coverage of crosstalk defects. C1 C12 CPU Cache Bus Cache C8 C9 MPEG C2 Video C11 UDL UART Arbiter Decoder Ecoder Iterface C7 32-bit Processor Bus Bridge 8-bit Peripheral Bus Exteral Test RAM RAM DMA UDL BIU C1 Cotroller C3 C4 C5 C6 8 Exteral Bus Figure 2 System-o-Chip showig buses, itercoects ad embedded self-test structures 1.2 Paper Outlie I Sectio 2, we explai the requiremets ad selectio of test trasactios to test the global itercoects of system chips. I Sectio 3, we will describe the self-test methodology that we have developed, which ivolves the isertio of test geerators, error detectors, ad global test cotrollers i the system chip, as show i Figure 2. I Sectio 4, we report o the applicatio of our self-test methodology o a DSP chip, ad the validatio of the self-test structures usig a high-level crosstalk simulatio method. Sectio 5 cocludes the paper. 2. Test Requiremets ad Test Trasactios Testig the bus ad other core-core itercoects i a SoC for crosstalk imposes several requiremets o the test vectors applied. The followig issues have to be addressed while decidig o a set of test trasactios, which should covers testig of all the ormal core-core trasactios. Bi-directioal trasactios: Because of trasmissio lie effects ad variatios i drivers ad loads coected to buses ad core-core itercoects, crosstalk may vary whe itercoects are drive from differet directios. For buses that are bidirectioal i ormal operatio, testig has to be coducted i both directios. Core-to-Core trasactios: Every core-to-core trasactio used i ormal operatio must be tested, sice every core-core trasactio ivolves a uique set of itercoects, drive stregths, ad loads. Cosider the system show i Figure 4 cosistig of 3 cores, sharig some itercoects (bus) betwee them. Though testig the iter-core commuicatio C1 C3 does exercise the shared itercoects/bus, the above test is ot eough to test C2 C3, sice the latter ivolves a differet set of itercoects, drive stregths, ad loads. If all the commuicatios C1 C3, C2 C3, ad C1 C2 are part of the ormal system operatio, the all three pairs eed to be tested separately. Dyamic bus sizig: For geeral-purpose buses shared amog several cores, the etire bus width may ot be utilized for some trasactios. Suppose i the system show i Figure 4, the C2 C3 trasactio requires oly bits of the 32-bit bus. Cosideratio must be give to the state of the uused lies durig testig. They may be biased to a logic value, floatig, or i trasitio. The differece betwee these cases is illustrated i Figure 5. This diagram illustrates a positive glitch test o a threewire bus of which oly two wires are used durig ormal operatio. Depedig o the state of the uused lie durig testig, the eergy i the geerated glitch may chage dramatically. For testig specific bus trasactios with reduced bus width, the state of the uused lies must reflect their actual operatioal state. Otherwise, the test may lead to overly pessimistic or optimistic testig i which a glitch (or delay) may be geerated that is too large or too small. Split bus trasactios: Split bus trasactios occur whe a bus is partitioed betwee two simultaeous but uassociated bus trasactios, each with reduced width. Usig the same reasoig

3 C1 C2 Glitch Eergy give for dyamic bus sizig, the trasactios must be cosidered simultaeously whe testig. For example, i Figure 2, cosider a situatio durig ormal operatio whe the processor bus is split for a C2 to C3 trasactio ad a simultaeous C4 to C6 trasactio. Whe testig a victim lie i the C2 to C3 trasactio, alog with the aggressor lies i the C2 to C3 path, all C4 to C6 lies must also be cosidered aggressors i order to geerate the same amout of crosstalk as that see durig ormal operatio. Defied by the fuctio of the system, there is a prescribed set of valid iter-core trasactios durig ormal operatio. As show above, the cosideratio of bi-directioal, core to core, ad split trasactios, as well as dyamic bus sizig requires that the set of iter-core trasactios for testig mimic those i the ormal operatio trasactio set. C3 Figure 4 -Testig core-to-core itercoects I determiig the set of test trasactios, oe way to esure correct ad complete coverage is to perform the etire set of valid operatioal trasactios. This, however, may be more testig tha ecessary. For a operatioal set of trasactios, certai trasactios i the set may cover the fault situatio of other trasactio i the set. Additioally, a umber of trasactios i the set may be testable simultaeously. 3. Self-Test Structures For each core to core test trasactio, our self-testig methodology requires a test geerator i the bus/itercoects iterface of the source core ad a error detector i the bus/itercoects iterface of the destiatio core. For example, i the SoC show i Figure 2, if we pla to test the trasactio from core C1 (CPU) to core C3 (RAM), a test geerator is iserted at the output of the CPU core, ad a error detector is iserted at the iputs of the RAM core. The test vector is lauched o the bus uder test by the test geerator(s) o oe clock edge from the source core(s), ad the measured for logical cosistecy at the other ed of the bus by the error detector(s) i the destiatio core(s) o the subsequet clock edge with the clock ruig at operatioal speed. Sice drivers ad loads of the cores play a critical role i crosstalk oise, the test geerators/error detectors must be located before the core s buffer coectios to the bus. Additioally, to select ad activate the appropriate test geerators ad error detectors, a global test cotroller is also Y 2 Test for g p Y 3 High-Z Aggressor Uused Active Lies Figure 5- Glitch eergy relatioship to state of uused bus lies required. Next, we will describe our desigs for the test geerator, error detector, ad test cotroller. 3.1 Test Geerator Each possible fault g p, g, d f, ad d r o a victim wire of a - bit wide bus requires a two-vector test sequece, as show i Figure 3. However, the test vectors ca be overlapped such that a six-vector test sequece ca test all the four possible faults o each victim wire of the bus/global itercoectio, as show i Figure 6 (a). The test sequece has several iterestig properties, eablig very efficiet desigs of the test geerators ad error detectors. For example, for each -bit test vector, there are oly two distict values eeded: the value o the victim wire, ad a value that is idetical o each aggressor wire. Figure 6 (b) shows our test geerator desig based o the above property. The fiite state machie geerates the two distict values, victim ad aggressor, i each state, s1 to s6. A state traversal from s1 to s6 correspods to geeratio of the six test vectors, durig which oe of the bus lies will be cofigured as a victim (receive the victim value), ad the rest of the bus wires will be cofigured as aggressors (receive the aggressor value). The cofiguratio is achieved by the victim couter, which couts from victim to victim -1, ad the decoder, which activates the select sigal q i of the appropriate multiplexer to eable bus wire b i to be the victim, ad every other wire to be a aggressor. The victim couter is reset by the reset sigal whe the FSM receives the start sigal T eable from the global test cotroller, ad makes a trasitio to state s1 to start geeratig the 1st vector. At the ed of every s1-s6 traversal, havig geerated all the tests for the victim wire, the FSM returs to state s1, settig the eable sigal to advace the victim couter. After the completio of 6-vector sequeces (upo receivig sigal q -1 i state s6, the FSM returs to the idle state s, ad stays there util T eable is received agai. 3.2 Error Detector Error detectio at the destiatio cosists of verifyig the correctess of the two-vector trasitio pairs. Figure 7 illustrates the possible desig of a error detector. It utilize a XOR etwork that compares the icomig vectors to the test vectors geerated by a local test geerator that is idetical to the source test geerator. The cofiguratio show i Figure 7 allows the test geerator to be utilized for both test geeratio ad error Bus Bit Positios Tests N i+1 i i g p g d f d r : Bus wire i q Couter (log2) 1 (log 2-1) log2 to Decoder q 1 q -1 reset eable S3 S2 Teable=1 S1 S4 S6 S S5 Output:(reset,eable,victim,aggressor) victim aggressors q 1 q 1 1 q -1 1 b.. (a) (b) Figure 6-(a) 6-vector Maximal Aggressor test sequece, (b) Desig of Test Geerator b 1 b -1 Teable= q -1 =

4 T mod Core Output Bus Core Test Geerator Figure 7-Desig of Error Detector Aalyzer Error Flag detectio. As show i Figure 7, T mode multiplexes the test geerator output with the ormal core output for drivig test vectors oto the bus. For cores with bi-directioal trasactios, we combied the test geerator ad error detector as oe testig compoet, amed. The testig compoet uses a additioal bit to receive mode iformatio, which iforms it to act as either a test geerator or a error detector as eeded. 3.3 Implemetatio of Parameterized Test Geerator/Error Detector We have developed parameterized HDL simulatio ad sythesis models for the proposed test geerator ad error detector desigs described above. The models are parameterized i terms of the umber of itercoects edig with a geerator/detector. Hece, they ca be easily istatiated to fit the differet width requiremets of the cores/itercoects of a system chip. The models have bee sythesized ad verified for various bit widths, usig Leoardo sythesis tool (Metor Graphics), ad a.35 µm techology library. I Table 1, we report the area overhead (i terms of 2-iput NAND gates) of the test geerators, error detectors, ad combied test geerator-error detector () sythesized for differet bit widths. For example, a 32-bit Test Width Test Error Geerator Detector 8-Bit Bit Bit Table 1- Overhead of Test Geerators, Error Detectors Geerator eeds iput NAND gates. Compared to the size of typical cores, like the ARM7TDMI processor core with 59K trasistors, ad the NEC V85 micro-cotroller core with 72K trasistors, the test geerator ad error detector overheads are very omial. 3.4 Global Test Cotroller For the BIST hardware described above, system level testig requires global sychroizatio of geerators ad error detectors ad selectio of cores ivolved i each test. The desig of the global test cotroller depeds extesively o the architecture of the system ad hece, optimal implemetatio will vary from system to system. The processor bus i Figure 2 for istace, may have distributed arbitratio where selectio of cores is accomplished through address decode logic cotaied i each core. I this case, test cotrol that is also distributed ad shares the same decode logic may be optimal. I cotrast, bus arbitratio may be cetralized ito oe arbiter that cotrols cores with select lies. Here, a test cotroller that is combied with the arbiter logic may be optimal. I the followig part, we describe our desig of a geeric global test cotroller that disables ormal bus arbitratio ad coducts the tests idepedetly. Figure 8 illustrates the cotroller. The cotroller coducts a sequece of core to core test trasactios by eablig a set of geerators ad error detectors via select lies ad moitorig for errors through flags set by the error detectors. The cotroller is cetered aroud a look up table (LUT) that cotais iformatio o which eable lies are activated ad how may test vectors are ru for each test trasactio. It also cotais iformatio for bus splittig. The LUT is a result of selectig ad schedulig test trasactios. To start the test, the ormal bus arbitratio logic is disabled ad the state machie i the test cotroller is tured o. Durig the test, the state machie advaces a trasactio couter that sequeces through each test trasactio by poitig to a row i the LUT that cotais iformatio o the curret test trasactio. The appropriate selectig sigals are drive by the LUT ad the a vector couter begis to cout the umber of test vectors clocked. The vector couter is compared to the vector cout also cotaied i the LUT, ad whe the correct umber of vectors have bee ru, the cotroller advaces to the ext test trasactio ad repeats util all test trasactios are completed. Durig testig, if a error is detected, the curret trasactio ad vector cout are logged ito a buffer for post testig diagosis. From the trasactio umber ad the vector umber, the exact lie o which the error occurred ca be determied. Tmode= Trasactios Complete=1 Tmode= Idle Tras Rst Vector Rst Tmode= Next Tras.=1 Complete Wait Tras Ic Vector Rst Test ad Vector Couter Log Tras Rst Tras Ic Vector Rst Test Clk Next Trasactio Trasactio Couter Vector Couter Test Cout Vector Cout Last Trasactio Couter Vector Cout/Global Eable LUT Tmod Test Complete Flag Flag k Aalyzer Error Flags Figure 8- Desig of Global Test Cotroller Geerator, Aalyzer Global Eables E m E

5 4. Applicatio of the Self-Test Methodology to a DSP chip To validate the self-test methodology, icludig the desig of test geerator, error detector ad test cotroller, we have applied the methodology to a Digital Sigal Processor chip, CMUDSP [1], which correspods to Motorola DSP562. We first briefly describe the architecture ad structure of the CMUDSP chip. Next, we discuss how we apply our self-test methodology for testig crosstalk i the buses of the chip, icludig isertio of the appropriate test geerators, error detectors, ad test cotroller, ad the overhead ivolved. We also discuss how validatio of the selftest methodology is performed. As show i Figure 9, CMUDSP cosists of four uits: Arithmetic ad Data Logic Uit (ALU), Address Geeratio Uit (AGU), Bus Switch, ad Program Cotrol Uit (PCU). The ALU cotais the X, Y, A ad B registers alog with the multiplyaccumulate ad adder uits. The AGU geerates the addresses for accessig the data memories. The PCU cotais program couter ad flag bits for cotrollig the whole DSP core. The PCU also performs program address geeratio ad istructio decodig. The Bus Switch is used to cotrol data flow betwee buses. CMUDSP cosists of three sets of separate data buses (XDB, YDB, PDB) ad address buses (XAB, YAB, PAB). The X ad Y buses are coected with data memory, ad the P buses are coected with program memory. From the CMUDSP architecture, ad the bus trasactios that are allowed durig ormal operatio, we first idetify the test trasactios that eed to be supported. Based o the test trasactios eeded, we iserted self-test compoets i each core selectively. For testig output buses to a core, a test geerator is iserted, ad for testig iput buses, a test detector is used. For bidirectioal buses to a core, we iserted a combied test geerator/error detector structure, which shares some commo logic to miimize hardware overhead (see Table 1 i Sectio 3.3). A test cotroller is iserted to cotrol the test trasactios as show i Figure 9. Besides havig to test sigle bus trasactios, if a set of multiple buses are ivolved i ormal operatio, the that set of multiple buses eed to be tested simultaeously to activate the worst-case crosstalk effect. For example, the Bus Switch uit has Origial Circuit With Test Compoet ALU AGU Bus PCU Test Switch Cotroller N/A Table 2 - Hardware overhead (2-iput NAND gates) Clock four separate 24-bit buses - three of them, XDB, YDB ad GDB are tested with self-test structures iserted, as show i Figure 9. If all the three buses eed to be tested together (say from the XDB, YDB at ALU ad GDB at AGU to Bus Switch uit), the test cotroller has to be cofigured so that the test geerators i AGU ad ALU combie properly to geerate test vectors for the multiple buses (as discussed i sectio 2), ad the compoet of the Bus Switch act as a error detector simultaeously. This is doe from the cofiguratio of Look Up Table (LUT) of the test cotroller. We have sythesized the origial DSP chip, as well as the chip with self-test structures iserted, usig Metor Graphics Leoardo sythesis tool [11]. Table 2 shows the sythesis results, i terms of the umber of 2-iput NAND gates for each origial compoet ad after test structures are iserted. The total hardware overhead (measured i 2-iput NAND gate) for the selftest methodology is about 22%. As show by Table 2, the high overhead is due to the relatively small size of some of the compoets (like PCU ad the Bus Switch). We expect that the area overhead will be much smaller whe we compare the area of the physical layouts of the origial ad fial circuits, as this will cosider the area due to the bus compoets, which costitute a sigificat part of the circuit, ad for which there is o extra test overhead. Also, applicatio of the self-test methodology o System-o-Chips, cosistig of processor ad other cores, will also show relatively small test overhead sice the overhead of the test geerator ad error detector compoets will be omial compared to the size of processor ad other cores, as show i Sectio Validatio of the Self-Test Methodology To validate the self-test methodology, icludig the proper desig ad fuctioig of the test geerators, error detectors ad test cotrollers embedded i the DSP chip, we will have to iject ad simulate crosstalk defects i the bus structures, ad esure that the test vectors geerated by the self-test structures detect all the defects ijected. The most accurate way of simulatig the chip is spice-level simulatio; however, spice-level simulatio of the etire chip is ot feasible. Hece, we have developed a high-level crosstalk defect simulatio method, which allows simulatio of the crosstalk effects o bus itercoects, together with the HDL models of the rest of the chip compoets, icludig the self-test structures. While we will ot get ito the details of the high-level crosstalk fault simulatio methodology here, we will describe it briefly, ad demostrate its use i validatig the self-test methodology applied to the CMUDSP chip. To eable ijectio of crosstalk defects i bus itercoects, ad simulatio of the behavior of the defect effects (glitch or delay) at the high-level, we also iserted behavioral-level itercoect DSM error models correspodig to the bus itercoects that are uder test. The resultig high-level crosstalk Reset XWrite XRead YWrite YRead AGU Immediate SWrite LWrite GDB ALU XDB YDB PDB XAB YAB PAB Detector PCU Test Cotroller S S1 Bus Switch Figure 9- CMUDSP with self-test compoets

6 Figure 1 -Validatig self-test methodology usig high-level crosstalk defect simulatio defect simulatio eviromet for the CMUDSP chip is show i Figure 1. A behavior level itercoect DSM error model geerates correspodig errors such as positive glitch, egative glitch, risig delay ad fallig delay [13] accordig to the crosscouplig parameters ad the test vectors trasmitted o a bus. A crosstalk defect ca be ijected by perturbig the values ad distributio of cross-couplig parameters beyod a threshold value [13] to reflect process variatios beyod desig margis. Durig crosstalk defect simulatio, the flow of test vectors through the circuit compoets is as followig: A HDL test geerator geerates the MAF test vectors for a bus, which are iput to the correspodig DSM error model. Depedig o the test vector trasitios, ad the couplig parameters of the bus, the DSM error model geerates output vectors, which may or may ot cotai (digitally ecoded) glitch or delay errors. Fially, the HDL error detector model at the ed of the bus aalyzes the output of the DSM error model, ad determies whether a error has occurred. We have used the high-level crosstalk defect simulatio eviromet, ad ModelSim HDL simulator[12], to validate the MAFM-based self-test methodology used for the DSP chip. A parameter file, cotaiig radomly perturbed cross-couplig values betwee the various itercoects, is used durig crosstalk simulatio. The couplig values lead to radomly geerated crosstalk defects, which are expected to give rise to errors o radomly selected victim lies. Simulatio starts with the activatio of the test cotroller, which schedules the required test trasactios ad iitiates the correspodig test geerators ad error detectors by issuig appropriate Test Eable sigals. Depedig o the use of the test vectors ad the parameter file, the itercoect error models may geerate crosstalk errors, which are the captured by the error detector ad commuicated back to the test cotroller, leadig to the activatio of the Iterrupt sigal from the cotroller. Figure 11 shows a sap-shot of the crosstalk simulatio of the CMUDSP chip. The sigals show iclude the system clock, the bus data (test vectors trasmitted o buses), the test eable sigals, ad the iterrupt sigal from the cotroller. By aalyzig the simulatio waveform, ad checkig with the expected errors (which ca be determied a-priori from the parameter file), we ca determie the correctess of the self-test methodology, icludig the self-test structures. We have performed crosstalk simulatio with several parameter files correspodig to several sets of radomly perturbed couplig values. For all the simulatio rus, the self-test methodology has bee able to report each error Clock Bus Data Test Eable Iterrupt Figure 11- Waveform of crosstalk simulatio correctly, idicatig the correctess of the desigs ad fuctioig of test geerators, error detectors, ad the test cotroller. 5. Coclusio We have ivestigated ad developed a self-test methodology for at-speed testig of crosstalk errors i global itercoects ad buses i System-o-Chips. The self-test methodology ivolves the isertio of self-test structures, such as test geerators, error detectors, ad a test cotroller i the SoC. The self-test structures geerate tests accordig to the MAFM [13], ad hece guaratees that ay crosstalk error, due to couplig capacitaces betwee itercoects, are detected. The parameterized test structures (test geerator, error detector, test cotroller) have bee simulated ad sythesized. We have also applied our self-test method to a DSP chip, ad validated the proper desig ad fuctioig of the selftest structures usig a ovel high-level crosstalk simulatio framework. I the future, we will apply this techique to other circuits, icludig SoCs, ad perform physical desig to assess the true cost of the techique. Use of the proposed self-test structures to geerate crosstalk test for aggressors may be costly for some applicatios. We would like to ivestigate alterative techiques to eable the itercoect crosstalk testig icludig the geeratio of test patters usig o-chip cores such as processors. 6. Refereces [1] H. Zhou, ad D. F. Wag, Global Routig with Crosstalk Costaits, Proceedigs 1998 desig ad Automatio coferece 35 th DAC, page , [2] Z. Che, ad I. Kore, Crosstalk Miimizatio i Three-Layer HVH Chael Routig, Proceedig IEEE Iteratioal Symposium o Defect ad Fault Tolerace i VLSI System, pages 38-42, [3] P. Nordholz, D. Treytar, J. Otterstedt, H. Grabiski, D. Niggemeyer, ad T.W. Williams, Sigal Itegrity Problems i Deep Submicro arisig from Itercoects betwee Cores, Proceedigs IEEE VLSI Test Symposium, pages 28-33, [4] K. Rahmat J. Neves, J. Lee, Methods for calculatig couplig oise i early desig: a comparative aalysis. Proceedig Iteratioal Coferece o Computer Desig VLSI i Computers ad Processors, pages76-81, [5] H. Kawaguchi ad T. Sakurai, Delay ad Noise Formulas for Capacitively Coupled Distributed RC Lies, Proceedigs of the Asia ad South Pacific Desig Automatio Coferece, Pages35-43, [6] Semicoductor Idustry Associatio (SIA), Iteratioal Techology Roadmap for Semicoductor, 1999 Editio. [7] K. T. Lee, C. Nordquist, ad J. Abraham, Automatic Test Patter geeratio for Crosstalk Glitches i Digital Circuits, Proceedigs IEEE VLSI Test Symposium, pages 34-39, [8] N. Itazaki, Y. Matsumoto, ad K. Kioshita, A Algorithmic Test Geeratio Method for crosstalk Faults i Sychroous Sequetial Circuits, Proceedigs Sixth Asia Test Symposium, pages 22-27, Nov [9] W. Che, S. K. Gupta, ad M. A. Breuer, Test Geeratio i VLSI Circuits for Crosstalk Noise, Proceedigs IEEE Iteratioal Test Coferece, pages , [1] C. Iacio, The CMU DSP Team, The Caregie Mello Sythesizable Digital Sigal Processor Core, [11] Leoardo Spectrum, V1999.1d, Exemplar Logic Ic., Fremot, CA. [12] ModelSim EE Vsim 5.3a Simulator, Model Techology Ic. Portlad, OR. [13] M. Cuviello, S. Dey, X. Bai, Y. Zhao, Fault Modelig ad Simulatio for Crosstalk i System-O-Chip Itercoects, Proceedigs of the Iteratioal Coferece o Computer-Aided Desig (ICCAD), pages , 1999.