MB hm91460-v1.21-errata-x1-17. Fujitsu Microelectronics Europe GmbH. Errata sheet, MB91460 Hardware Manual (hm91460-v1.21)

Transcription

1 Corrections of Hardware Manual MB91460 hm91460-v1.21-errata-x1-17 Fujitsu Microelectronics Europe GmbH Errata sheet, MB91460 Hardware Manual (hm91460-v1.21) This is the errata sheet for the Hardware Manual hm91460-v1.21 of the MB91460 microcontroller series. It describes all known discrepancies and corrections of the MB91460 microcontroller series Hardware Manual. Ref. Number (Internal ref. number) (Text Link) Date dd.mm.yy Version No. Chapter/Page Description/Correction HWM V1.00 HWM V1.00 Transition to standby mode with enabled prefetch mechanism Timing requirement of the PARALLEL programming mode of the flash security HWM V1.00 UART4 SOT4 is initialized by the boot-rom HWM V Wake-up from stop mode, ext. IRQs are not stored during blackout. HWM V Watchdog Timer: Retriggered /cleared automatically by DMA (MB91V460A, MB91461) HWM V1.00 Chip IDs HWM V USART FIFO HWM V Eva-device: Input frequency for clock modulator HWM V , 9.2, 9.6.4/5, , 21 RC clock run mode after clock supervisor reset cannot be left with hardware watchdog reset HWM V Flash access mode switching HWM V Watchdog reset HWM V USART; Status bits of register SSR04 hm91460-v1.21-errata-x1-17.docx 1 / 44

2 HWM V A/D Converter; Sampling Timer Setting Register (ADCT) HWM V LCD: Enabling LCD even in the Sub-STOP state HWM V LCD: Cautions Corrections added HWM V LCD: Settings Corrections added HWM V LCD: Control Register, Note added HWM V Main Clock Oscillation Stability Wait Timer HWM V Corrected I/O Signal description for Pins 16_0 Pin16_6 HWM V HWM V ICU interrupts: Corrected edge polarity description Correction of note regarding bits of the Extended Communication Control Register (ECCR04) HWM V Registers modified by BootROM HWM V Flash Memory write protection limitations HWM V HWM V HWM V HWM V HWM V HWM V HWM V HWM V HWM V HWM V HWM V1.15 HWM V , , Note added regarding Flash access mode switching Corrected EDSU Control Register (BCTRL) description Corrected EDSU Channel Configuration Register (BCR) description EDSU; Corrected relationship of BCR, BAD and BIRQ register description. EDSU; Corrected operand size and operand address relations description EDSU; Corrected data value break description EDSU; Note regarding Instruction Address Capture Register (BIAC) Extended Communication Control Register (ECCR04); Added function description regarding Start/Stop bit mode enable(bit3). Corrected block diagram of clock distribution Corrected Chapter Clock Supervisor Corrected ADC input circuit and sampling time calculation formula The Sub Oscillation Stabilization Timer operation enable bit WPCRH.WEN is not available hm91460-v1.21-errata-x1-17.docx 2 / 44

3 HWM V , 23 HWM V Description of clearing the counter of Main Oscillation Stabilization Timer and Sub Oscillation Stabilization Timer is described precisely. A difference to MB91460E series is described. Extended note on how to prevent high pulse on SCK line when performing software reset (setting SMR:UPCL in master mode 2 with the mark level set to 0 ). hm91460-v1.21-errata-x1-17.docx 3 / 44

4 HWM Transition to standby mode with enabled prefetch mechanism Affected devices: - MB91V460A (in flash mode only not for debugging) - MB91F467DA Revision 1, 2 - MB91F464AA Revision 1 (cache not specified) - MB91F465KA Revision 1 - MB91F469GA Revision 1 - MB91F467RA Revision 1 Problem Description: If the Flash I-Cache is enabled (FCHCR.ENAB == 1) and the Prefetch Mechanism is enabled (FCHCR.PFEN == 1) and the device is set into the standby modes SLEEP or STOP it can happen that an invalid entry into the Flash I-Cache is made which can cause irregular program operation after recovering from the SLEEP or STOP mode. Problem Workaround: It is mandatory to lock the Flash I-Cache (FCHCR.LOCK :=1) before setting the device into SLEEP or STOP mode to avoid writing an invalid entry into the Cache. After recovering from SLEEP or STOP mode the Flash I-Cache can be unlocked again. Please see the corresponding customer information for details: CI MB91460_Flash_IF_Arbitration.pdf HWM Timing requirement of the PARALLEL programming mode of the flash security. Precondition: CHIP ERASE COMMAND is performed with addresses of sectors secured with the write protection bits and the write data DIN data changes while WEX=L. Effect: CHIP ERASE COMMAND might or might not be executed. Workarounds: 1. Perform the CHIP ERASE COMMAND with addresses of sectors NOT secured with the write protection bits. OR 2. Change timing of write data DIN vs. write enable WEX WEX DIN X X timing <--tds---> <---tdh----> to avoid changing while WEX=L. hm91460-v1.21-errata-x1-17.docx 4 / 44

5 Remarks: - This effect does not compromise the flash security! - It does not affect programming operation and standard timing of an empty flash - It does not affect programming operation and standard timing of an unsecured flash (read and write) - It does not affect programming operation and standard timing of a read-only secured flash - It does not affect programming operation and standard timing with a chip erase command addresses not inside write protected sectors HWM Affected devices: - MB91V460A (UART0 instead of UART4) - MB91F467DA Revision 1, 2 - MB91F464AA Revision 1 - MB91F465KA Revision 1 Precondition: Initialization of UART4 by the boot ROM. (Security vectors are not set) and UART4 is initialized after start-up for asynchronous data transmission. Effect: The boot ROM always initializes the UART4 SOT4. If nothing is transmitted by the boot ROM, this results in a high level on SOT4 for the time of the active boot ROM. At the end of the boot ROM, the registers of the UART4 are reset to the initial values; hence after about 2 µs of low level is SOT4 high-impedance, which may be interpret by a receiver as low level. If the UART 4 is initialized immediately after start-up for asynchronous data transmission by the application, a receiver may interpret the changes as a valid signal. Workarounds: - Pull-up resistor on SOT4 to provide a high-level when SOT4 is high-impedance. This reduces the time of low level to about 2 µs. - Do not use UART4 in asynchronous mode immediately after start-up. (UMa) HWM Please see the corresponding customer information CI MB91460_External_Interrupt.pdf (MBo) hm91460-v1.21-errata-x1-17.docx 5 / 44

6 HWM Watchdog Timer: Retriggered /cleared automatically by DMA (MB91V460A, MB91461) Chapter 20.1, page 273 affected devices: MB91V460A and MB91461 The watchdog timer will be retriggered / cleared automatically by DMA during D- bus access. (NFl, MBo) HWM Below, the chip-ids of the different devices are listed. Chip-ID location: 0xBFF4 Datecodes MB91V460A 0x020DCC01 MB91F464AA Rev. 1 0x0205D048 Rev. 2 0x0205D049 from 0644-K00, K01, K02 Rev. 3 0x0205D04A MB91F464AB 0x0205D04B MB91F465BB 0x MB91F467BA Rev. 1 0x Z00 Rev. 2 0x MB91F467BB 0x MB91F467CA MB91F467CB 0x x MB91F465DA Rev. 1 0x Rev. 2 0x MB91F467DA Rev. 1 0x0205D329 Rev. 2 0x0205D32A from 0616-Z11 Rev. 3 0x0205D32B from 0642-Z07 Rev. 4 0x0205D32C MB91F467DB 0x0205D32D MB91F469GA Rev. 1 0x0205D558 Rev. 2 0x0205D558 from 0643-Z03 Rev. 3 0x0205D55A MB91F469GB 0x0205D55B hm91460-v1.21-errata-x1-17.docx 6 / 44

7 Chip-ID location: 0xBFF4 Chip-ID Datecodes MB91F465KA Rev. 1 0x0205D050 Rev. 2 0x0205D051 Rev. 3 0x0205D052 MB91F465KB 0x0205D053 MB91F467MA 0x MB91F465XA Rev. 1 0x Rev. 2 0x Chip-ID location: 0xB000 Chip-ID MB x MB91F463NA MB91F463NB 0x x MB91F467RA MB91F467RB MB91F467RC 0x x x (MBo, MVo) hm91460-v1.21-errata-x1-17.docx 7 / 44

8 HWM Chapter FIFO Control Register (FCR04), Page 631: Notes, Rx triggerlevel. Incorrect: "The RX triggerlevel sets the reception FIFO level where the reception interrupt is activated. E.g. if the triggerlevel is at its default value of RXL[3:0]=0000, the interrupt is activated if one reception is stored in the FIFO. If the the triggerlevel is set to RXL[3:0]=1111, the interrupt is activated if 16 receptions are stored in the FIFO. In general: a reception interrupt is triggered if FSR[4:0] > FCR[7:4]." Correct: "The RX triggerlevel sets the reception FIFO level where the reception interrupt is activated. E.g. if the triggerlevel is at its default value of RXL[3:0]=0000, the interrupt is activated immediately. If the the triggerlevel is set to RXL[3:0]=1111, the interrupt is activated if 15 receptions are stored in the FIFO. In general: a reception interrupt is triggered if FSR[4:0] >= FCR[7:4]." Below listed devices are not affected. Please note that register setting FCR[3] = 1 has to be done. MB91F463CA MB91F465CA MB91F467SA MB91F465PA MB91F467PA MB91F467TA MB91F469TA MB91F469QA MB91FV460B (UMa, MBo, MSt, MHz) HWM Chapter 17 Clock Modulator For the MB91V460A Eva device there is a restriction for the input frequency of the clock modulator. Input frequency of clock modulator is limited to the range: 16 MHz 24 MHz. (UMa, MBo, MHz) hm91460-v1.21-errata-x1-17.docx 8 / 44

9 HWM RC clock run mode after clock supervisor reset cannot be left by hardware watchdog reset The clock supervisor function is used to detect a missing main clock or sub clock signal. In case the clock supervisor detects a missing clock signal, it switches to RC clock sources and issues a clock supervisor reset. MCU starts up on RC clock now. If you now ran into a hardware watchdog reset by not triggering HWWD_CL bit in time, the bit CSVCR_MM (main clock missing) or CSVCR_SM (sub clock missing) is not cleared which leads to another startup on RC clock. Even if the hardware watchdog reset is an INITX reset type, it is not able to clear these bits. To clear these bits and to startup on main clock again (only possible if previous clock supervisor reset was caused by a short-time distortion of main clock signal and not of a total loss of oscillator connection), you need poweron reset or external reset input at INITX pin. (MVo, MBo) HWM Chapter 54.6 "Flash Access Mode Switching" Note: For availability of this function and its start address, please refer to the datasheet of the device, section "Embedded Program/Data Memory (Flash)". (PHu, MBo, MHz) HWM Chapter 6 "Watchdog Reset (INIT: Settings Initialization Reset)" Chapter 6.3 Flag Incorrect: When watchdog reset request is triggered, the watchdog timeout flag (RSRR.WDOG) is set to 1. (SWWD and HWWD) Correct: When watchdog reset request is triggered, the watchdog timeout flag (RSRR.WDOG) is set to 1. (SWWD) (JWa, HSt, MHz) hm91460-v1.21-errata-x1-17.docx 9 / 44

10 HWM Chapter 32 "USART (LIN/FIFO)" Table 4-5 Functions of each bit of status register 04 (SSR04) ; p. 627 Incorrect: Correct: TIE (JWa, HSt, MHz) HWM Chapter Sampling Timer Setting Register (ADCT) Change in the paragraph [bit9 to 0] for better legibility. Before: Tsamp = (200 * * 103) * 10.7 * * 7 = [us] Better: Tsamp = (200 * * 10 3 ) * 10.7 * * 7 = [us] (JWa, HSt, MHz) hm91460-v1.21-errata-x1-17.docx 10 / 44

11 HWM Chapter How to enable LCD display even in the Sub-STOP state Incorrect: According to hardware manual, the LCD continues working in "Sub-STOP" mode if the control bit LCR0.LCEN is set. Correct: While the digital part continues working, the analog part is disabled in STOP mode, regardless of LCR0.LCEN setting. The outputs COM[3:0] and SEG[39:0] will output "L" level in STOP mode. Workaround: Don't use STOP mode, or use MB91V460B. (JFl, MHz) HWM Chapter 47.8 Caution Some statements in chapter 47.8 Caution are incorrect: Incorrect: Correct: VRAM[0:19] can be written in byte, halfword and word access hm91460-v1.21-errata-x1-17.docx 11 / 44

12 Incorrect: Correct: According to ref. number HWM the LCD it is disabled in any kind of STOP state. (JFl, MHz) HWM Chapter 47.6 Setting Table 6-4 Required Setting to Enable LCD Display in Sub-STOP state Incorrect: Correct: The CPU does not need to be switched to Sub Clock. It is sufficient to switch the LCD clock source to Sub Clock by setting LCR0.CSS. (JFl, MHz) HWM Chapter LCR0: LCDC Control Register 0 Note: The LCD can also be operated on RC-clock. This can be enabled by setting bit CSCFG.CSC3 (switches to RC clock instead of 32kHz Sub Clock). Please see also chapter Clock Source Configuration Register. (JFl, MHz) hm91460-v1.21-errata-x1-17.docx 12 / 44

13 HWM Chapter OSCRH: Control Register for the Main Clock Oscillation Stability Wait Timer Incorrect: Correct: (2.0 ms) (65.5 ms) (4.0 s) (MBo, MHz) hm91460-v1.21-errata-x1-17.docx 13 / 44

14 HWM Chapter 30.1 I/O Ports function Corrected I/O Signal description for Pins 16_0 Pin16_6 of Port 16 Incorrect: hm91460-v1.21-errata-x1-17.docx 14 / 44

15 Correct: P16_6 P16_5 P16_4 P16_3 P16_2 P16_1 P16_0 (MVo, MHz) hm91460-v1.21-errata-x1-17.docx 15 / 44

16 HWM Chapter What are the types of active edge polarity for external input, and how to select them? Corrected external input active edge polarity bit pattern. Incorrect: Correct: 01 (HGl, MHz) hm91460-v1.21-errata-x1-17.docx 16 / 44

17 HWM Chapter Extended Communication Control Register (ECCR04) In Figure 4-6 a wrong note is given for bit TBI Transmission bus idle, bit RBI Reception bus idle and bit BIE Bus idle interrupt enable. Incorrect: ~ ~ Correct: ~ ~ Not useable in mode 2 when MS = 1 (MVo, JFl, MHz) hm91460-v1.21-errata-x1-17.docx 17 / 44

18 HWM Chapter 53.3 Registers modified by BootROM The list which shows the RAM address of the individual devices where the BootROM stores the RSRR is updated. Before update: After update: (RSc, MHz, JWa) MB91V460A MB91F460A MB91F460B MB91F460C MB91F465D MB91F467D MB91F460E MB91F460G MB91F460K MB91F460M MB91F460P MB91F460Q MB91F460S MB91F460T MB91F460X 0x x2E500 0x2E500 0x2E500 0x2E500 0x x2E500 0x x2E500 0x2E500 0x2E500 0x2E500 0x2E500 0x2E500 0x2E500 hm91460-v1.21-errata-x1-17.docx 18 / 44

19 HWM Limitations on the FLASH write protection function specifications 1.1 Affected products MB91460 series: MB91F464A, MB91F465B, MB91F467B, MB91F465C, MB91F467C MB91F465D, MB91F467D, MB91F469G, MB91F464H, MB91F465K, MB91F467M, MB91F463N, MB91F465P, MB91F467P, MB91F469Q, MB91F467R, MB91F467S, MB91F467T, MB91F465X 1.2 Overview The FLASH write protection function in the MB91460 series allows each sector to be set as write-protected (writing prohibited). However, it has been discovered that it may be possible to write to sectors that have been set as writeprotected depending on the usage method. However, there are no problems if any of the following methods are used. Please use the method shown in [1] below to write to the FLASH memory. For a method of write protection other than method [1], please use method [2]. [1] Set the address used in the write sequence to a sector address that is always written to. [Example] Write 0xAAAA to address ((adr & 0xFFFC000) + 0x155n) // 1st unlock cycle Write 0x5555 to address ((adr & 0xFFFC000) + 0x2AAn) // 2nd unlock cycle Write 0xA0A0 to address ((adr & 0xFFFC000) + 0x155n) // 3rd unlock cycle Write the target data to address adr // Data write Where the conditions are that adr is the address of the target sector and n is set to be within the target sector. [2] Set the write protection (writing prohibited) function on all sectors. hm91460-v1.21-errata-x1-17.docx 19 / 44

20 2. List of FLASH memory commands for the MB91460 series (revised version) (MBo, MHz) hm91460-v1.21-errata-x1-17.docx 20 / 44

21 HWM Chapter 54.6 Flash Access Mode Switching Note: For the address of the switching routine in the Boot ROM, please refer to the datasheet of the appropriate flash device. (JWa, MBo, MHz) HWM Chapter Explanations of Registers Corrected EDSU Control Register (BCTRL) description Incorrect: hm91460-v1.21-errata-x1-17.docx 21 / 44

22 Correct: BIT BIT BIT BIT hm91460-v1.21-errata-x1-17.docx 22 / 44

23 BIT BIT (MSt, KGo, MHz) HWM Chapter Explanations of Registers Corrected EDSU Channel Configuration register (BCR) description Incorrect: hm91460-v1.21-errata-x1-17.docx 23 / 44

24 hm91460-v1.21-errata-x1-17.docx 24 / 44

25 Correct: BIT BIT hm91460-v1.21-errata-x1-17.docx 25 / 44

26 BIT BIT BIT BIT hm91460-v1.21-errata-x1-17.docx 26 / 44

27 BIT BIT (MSt, KGo, MHz) hm91460-v1.21-errata-x1-17.docx 27 / 44

28 HWM Chapter Explanations of Registers Corrected description in table 3-3. Incorrect: hm91460-v1.21-errata-x1-17.docx 28 / 44

29 hm91460-v1.21-errata-x1-17.docx 29 / 44

30 Correct: IA0 / OA0 DT0 IA1 / OA1 DT1 IA0 / OA0 IA1 / OA1 IA0 / OA0 DT0 IA1 / OA1 DT1 IA0 / OA0 IA1 / OA1 IA0 / OA0 DT0 IA1 / OA1 DT1 IA0 / OA0 IA1 / OA1 hm91460-v1.21-errata-x1-17.docx 30 / 44

31 IA0 / OA0 DT0 IA1 / OA1 DT1 IA0 / OA0 IA1 / OA1 IA0 / OA0 DT0 IA1 / OA1 DT1 IA0 / OA0 IA1 / OA1 IA0 / OA0 DT0 IA1 / OA1 DT1 IA0 / OA0 IA1 / OA1 IA0 / OA0 DT0 IA1 / OA1 DT1 IA0 / OA0 IA1 / OA1 IA0 / OA0 DT0 IA1 / OA1 DT1 IA0 / OA0 IA1 / OA1 (MSt, KGo, MHz) hm91460-v1.21-errata-x1-17.docx 31 / 44

32 HWM Chapter Operand address break Corrected description in table 4-3. Incorrect: hm91460-v1.21-errata-x1-17.docx 32 / 44

33 Correct: BOAC BOAC (MSt, KGo, MHz) hm91460-v1.21-errata-x1-17.docx 33 / 44

34 HWM Chapter Data value break Corrected description in table 4-3 Incorrect: hm91460-v1.21-errata-x1-17.docx 34 / 44

35 Correct: BAD1/0 BAD1 BAD1 (MSt, KGo, MHz) hm91460-v1.21-errata-x1-17.docx 35 / 44

36 HWM Chapter Explanations of Registers Additional note regarding Instruction Address Capture Register (BIAC) Note: In case of Instruction Address (IA), Operand Address (OA) or Operand Data Value Break (DT) the BIAC register keeps valid Instruction Address (IA) until respective BIRQ.BD-bits are reset. In case of Protection Violation Break (PV) the BIAC register keeps valid Instruction Address (IA) until PV-bit is reset. In case of multiple breaks PV along with e.g. IA, OA or DT the BIAC register keeps valid Instruction Address (IA) until both PV-bit and respective BIRQ.BDbits are reset. (MSt, KGo, MHz) hm91460-v1.21-errata-x1-17.docx 36 / 44

37 HWM Chapter Extended Communication Control Register (ECCR04) Table 4-8, Added function description regarding Start/Stop bit mode enable (bit3) Incorrect: ~ ~ ~ ~ Correct: ~ ~ ~ ~ Setting SSM is only possible if operation mode is set to 2 (SMR04, MD bits) (JWa, MHz) hm91460-v1.21-errata-x1-17.docx 37 / 44

38 HWM Chapter 13 Clock Control Corrected Figure 1-1: Block diagram of clock distribution Incorrect: CORRECT: CLKMAIN (NFl, MHz) hm91460-v1.21-errata-x1-17.docx 38 / 44

39 HWM Chapter 16 Clock Supervisor The whole chapter 16 Clock Supervisor is updated and corrected due to several wrong and missing descriptions. Correct: Please refer to the following additional document for the complete reviewed and corrected chapter 16 Clock supervisor. >> hm91460-errata-clock-supervisor-x1.00.pdf Please note, that this document completely replaces the chapter 16 of the current MB91460 Hardware Manual hm91460-v1.21. All text parts marked by a red change bar on the left side indicate differences to the current hm91460-v1.21. The document is also valid for MB91FV460B and derived flash devices. Additional features of these devices are marked by red text new feature. All parts, which are marked with new feature, describe the intended behavior for future devices. The current implementation of the new feature in MB91FV460B1/2 and MB91F467PA shows partly faulty behavior. JWa, JFl hm91460-v1.21-errata-x1-17.docx 39 / 44

40 HWM Chapter 44 A/D Converter (ADC) The description of the ADC input circuit and the appropriate formula for sampling time calculation given in the current hardware manual v1.21 is incomplete. Especially for high input impedance, the calculated sampling time will be too short. The following lines will describe the wrong documentation and will give the correction. (1) Replacement circuit for analog input (chapter 44, section 1): Incomplete: The parasitic PCB and pin input capacitance of the MCU itself is missing in the circuit. Correct: The equivalent circuit now also considers the external capacitance C ext (e.g. PCB wiring capacitance) and the pin input capacitance of the MCU C in. hm91460-v1.21-errata-x1-17.docx 40 / 44

41 (2) Calculation formula for sampling time (chapter 44, section 3.4 and 6.3) Considering the complete equivalent circuit, the formula for sampling time calculation given in the current hardware manual is wrong. Wrong: The formula is valid for a single RC filter with. The real input circuit is two RC filters in series for which the calculation of the time constant i.e. sampling time ( ) is more complex. If the additional capacitance of C ext and C in is not considered, the sampling time will be too short. Especially for high input impedance circuits the ADC sampling capacitance C ADC is mainly charged by C ext and C in. As these capacities are normally in the same range as C ADC, a charge exchange between C ext C in and C ADC will take place, resulting in a voltage drop. Then all three capacities (C ext, C in and C ADC ) must be charged by the source. Therefore the calculation formula must comprise C ext and C in also. Correct: The sampling time should be set to minimum. The following approximation formula for the replacement model above can be used: If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µf to the analog input pin. In this case the internal sampling capacitance C ADC will be charged out of this external capacitance. Note: Please refer to the appropriate datasheet of your device to obtain the values for the formula shown above. The pin input capacitance (C in ) can be found in chapter Electrical Characteristics, section 3. DC characteristics, referred as Input capacitance C IN. The ADC values are located in section 4. A/D converter characteristics. The input resistance R ADC is referred as Input resistance R IN and the ADC sampling capacitance C ADC as Input capacitance C IN. JWa, JFl hm91460-v1.21-errata-x1-17.docx 41 / 44

42 HWM Chapter 23 Sub Oscillation Stabilization Timer The Timer operation enable bit for the Sub Oscillation Stabilization Timer WPCRH.WEN (Bit5) is not available. The timer is always running. Reading this bit returns 0. Wrong: Section 23.3 Register WPCRH Bit5: WEN Section Register WPCRH Bit5: WEN, Timer operation enable Section Sets with the timer operation enable bit (WPCRH.WEN). Correct: Register WPCRH Bit5: --- Register WPCRH Bit5-3: Reserved bit. Be sure to write 0. The read value is 0. The timer is always running as long as the Sub clock is available. JWa, JFl hm91460-v1.21-errata-x1-17.docx 42 / 44

43 HWM Chapter 22 Main Oscillation Stabilization Timer Chapter 23 Sub Oscillation Stabilization Timer The Main Oscillation Stabilization Timer and Sub Oscillation Stabilization Timer provide a Timer clear bit WCL. Timer clear bits: Main Oscillation Stabilization Timer: OSCRH.WCL Sub Oscillation Stabilization Timer: WPCRH.WCL Writing 0 to these bits initiates to clear the appropriate timer counter. The description given in the current version of the hardware manual (HWM) is not complete. Addendum to the explanation given in the current HWM: After writing 0 to the WCL bit, the timer is not cleared immediately, it stops counting only. To finally clear and restart the counter, a sub-sequent access to an address within the R-Bus address area must be done. This can be done by either writing or reading another register of a resource (connected to the R-Bus) or simply read the RBSYNC address (0x03A). Correct sequence example: For Main Oscillation Stabilization Timer: OSCRH_WCL = 0; RBSYNC; // Initiate counter clearing (counter will stop now) // Read access to R-bus to force timer // to clear and restart For Sub Oscillation Stabilization Timer: WPCRH_WCL = 0; RBSYNC; // Initiate counter clearing (counter will stop now) // Read access to R-bus to force timer // to clear and restart Attention: If no R-bus access follows the sequence of setting OSCRH_WCL/WPCRH_WCL = 0, the appropriate counter will stop only. It will clear and restart not until another R-bus access is done. Note on MB91460E series: JWa, JFl The above described behavior is different for MB91460E series devices. Writing WCL = 0 will immediately clear and restart the corresponding timer (either Main Oscillation Stabilization Timer or Sub Oscillation Stabilization Timer). This means on MB91F467E the Osci Stabi Timer Interrupts may appear earlier then on other devices running the same software. hm91460-v1.21-errata-x1-17.docx 43 / 44

44 HWM Chapter 32 USART (LIN / FIFO) Section 8. Notes on using USART Note Software reset of UART Problem: In synchronous master mode (Mode 2 with SMR:SCKE=1) and with the SCK mark level set to 0 (ESCR:SCES = '1'), there will be a high-pulse on the SCK line after software reset (writing '1' to SMR:UPCL). バスクロック Serial Clk SCKO UPCL ソフトウェアリセット The connected slave device may consider this pulse on SCK line as a serial clock. Current description of note: Extended description of note: Software reset of UART Perform the software reset (SMR: UPCL=1), when the TXE bit of the SCR register is "0". When performing software reset (writing '1' to SMR:UPCL) in master mode 2 (synchronous), with the mark level set to '0' (ESCR:SCES = '1'), special care has to be taken to avoid pulses on SCK. Please stick to the following precautions: Once: Set output data for the port function of the SCK pin to 0 by writing '0' to the related PDR register bit and enable port output function for the SCK pin by writing '1' to the related DDR register bit. At every software reset: Disable SCK output by writing '0' to the related PFR register bit before performing software reset by writing '1' to SMR:UPCL. Then enable SCK output again by writing '1' to the PFR register bit. JFl,JWa hm91460-v1.21-errata-x1-17.docx 44 / 44