MOV CX,80 MOV CX,100. For example, MOV DI, OFFSET TEXT_STRING ;DI points to the TEXT_STRING in the extra segment ; Byte to be scanned in AL

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1 Q1. Explain briefly the following instructions with examples. (a) IDIV (b)imul (c) SAR (d) SAL (a) IDIV: This instruction is used to divide a signed word by assigned byte, or to divide signed doubleword (32 bits) by a signed word. When dividing a signed word by a signed byte, the word must be in AX register. The divisor can be in an 8-bit register or a memory location. After the division, AL will contain the signed result (quotient) and AH will contain the signed remainder. If an attempt is made to divide by 0, 8086 will automatically do a type 0 interrupt. When dividing a signed double word by a signed word, the most significant word of the dividend must be in DX register and the least significant word must be in AX register. The divisor can be in a 16-bit register or a memory location. After the division, AX will contain the signed result (quotient) and DX will contain the signed remainder. If an attempt is made to divide by 0, 8086 will automatically do a type 0 interrupt. For example, MOV AX,03ABH ; AX=03ABH= =939 (Decimal) MOV BL,D3H ;BL= D3H= = -2DH=-45 (Decimal) IDIV BL ; AL=ECH=-14H=-20 (Decimal) and AH=27H =+39( Decimal) (b) IMUL: This instruction multiplies a signed byte from some source times a signed byte in AL or a signed word from some source times signed word in AX. The source can be a register or a memory location. When a byte from some source is multiplied by AL, the signed result (product) will be in AX. When a word from some source is multiplied by AX, the most significant word of the signed result is put in DX, and least significant word of the signed result is put in AX. For example, MOV AL, E4H ;AL=E4H= =-1AH= -28 (Decimal) MOV BL, 3BH ;BL=3BH= =59 (Decimal) IMUL BL ; AX=F98CH=-674H=-1652 (Decimal) (c) SAR (Shift arithmetic right): The arithmetic shift is used for signed numbers. MSB MSB LSB This instruction shifts each bit by bit to the right. As a bit is shifted out of the MSB position, a copy of the MSB is put in the MSB position For example, MOV AL,-10 ;AL=-10=F6H= SAR AL,1 ;AL= =FDH=-5 (d) SAL (Shift arithmetic left) is same as SHL Q2. Explain the following instructions with examples: (a) STOS (b) LODS (c) CMPS (d) REPZ (e) SCAS (f) XLAT (a) STOS: The STOS instruction copies a byte from AL or a word from AX to a memory location in the extra segment pointed by DI. After the copy, DI is automatically incremented by 1 for a byte string or CF Page: 1

2 incremented by 2 for a word string if the direction flag is cleared (DF=0) and DI is automatically decremented by 1 for a byte string or incremented by 2 for a word string if the direction flag is set (DF=1); For example, MOV DI, OFFSET TARGET_STRING ; DI is pointing to the TARGET_STRING STOSB ; AL is copied to the memory location pointed by DI (b) LODS: This instruction copies a byte from a string location pointer by SI to the register AL or it copies a word from the string location pointed by SI to the register AX. After the copy, SI is automatically incremented by 1 for a byte string or incremented by 2 for a word string if the direction flag is cleared (DF=0) and DI is automatically decremented by 1 for a byte string or incremented by 2 for a word string if the direction flag is set (DF=1); For example, MOV SI, OFFSET SOUR_STRING ; SI is pointing to the TARGET_STRING LODSB ; Content of memory location pointed by SI is copied to AL (c) CMPS: The CMPS instruction can be used to compare a byte in one string with a byte in another string or to compare a word in one string with a word in another string. The CMPS instruction can be used with a REPE or REPNE prefix to compare all elements of a string. For example, MOV SI, OFFSET FIRST_STRING ; SI pointing to the source string MOV DI, OFFSET SECOND_STRING ; DI pointing to the destination string CLD MOV CX,100 REPE CMPSB (d) REPZ: REPZ/REPE are often used as prefix written before CMPS (Compare string) or SCAS (Scan String). REPE and REPZ stand for Repeat if Equal and Repeat if zero respectively. REPE or REPZ causes the CX register to be decremented and string instruction to be repeated until CX=0. REPE and REPZ will cause the string instruction to be repeated as long as the compared bytes or words are equal and CX is not yet counted down to zero. For example, MOV SI, OFFSET FIRST_STRING ; SI pointing to the source string MOV DI, OFFSET SECOND_STRING ; DI pointing to the destination string CLD MOV CX,100 REPE CMPSB (e) SCAS: SCASB compares a byte in AL with a byte pointed by DI in Extra segment (ES). SCASW compares a word in AX with a word pointed by DI in Extra segment(es). If the direction flag is cleared (DF=0), then DI will be incremented by 1 after SCASB or DI will be incremented by 2 after SCASW. If the direction flag is set (DF=1), then DI will be decremented by 1 after SCASB or DI will be decremented by 2 after SCASW. For example, MOV DI, OFFSET TEXT_STRING ;DI points to the TEXT_STRING in the extra segment MOV AL,0DH ; Byte to be scanned in AL MOV CX,80 ;CX is used as element counter Page: 2

3 CLD ; Clear the direction flag (DF=0) REPNE SCASB ; Scanning is repeated until bytes are not equal or CX is not zero. (f) XLAT: The XLAT is used to translate a byte from one code to another code. This instruction replaces a byte in the AL register with a byte pointed to by BX in a look up table in the memory. Before the XLAT instruction to be executed, the look up table containing the values for the new code must be put in the memory and the offset address of the starting address of the look up table must be loaded in BX. The code byte to be translated is put in AL. To point to the desired byte in the lookup table, XLAT instruction add the byte in AL to the offset of the start of the lookup table in BX. It then copies the byte from the address pointed by (AL+BX) into AL. For example, MOV BX, OFFSET TABLE ; BX pointing to TABLE XLAT ; Replaces value in AL with the value from the TABLE Q3. Explain briefly the memory address decoding for 32KB memory chip for address 08000H to 0FFFFH. A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A H= FFFFH= K=32x1024=2 15 As the memory chip is of 32KB and hence 15 lower bits of the address (A 0 to A 14 ) are connected to the memory chip. Remaining 5 bits (A 15 to A 19 ) are connected to the NAND gate as input such that output of the NAND gate is LOW to enable the memory chip. The connection is shown below: A0 D0 Address Bus A14 D7 Data Bus 32K x 8 A15 A16 A17 A18 A19 CS OE WR MEMR MEMW Page: 3

4 Q4. Explain briefly the memory address decoding for 64KB memory chip for address 90000H to 9FFFFH. A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A H= FFFFH= K=64x1024=2 16 As the memory chip is of 64KB and hence 16 lower bits of the address (A 0 to A 15 ) are connected to the memory chip. Remaining 4 bits (A 16 to A 19 ) are connected to the NAND gate as input such that output of the NAND gate is LOW to enable the memory chip. The connection is shown below: A0 D0 Address Bus A15 D7 Data Bus 64K x 8 A16 A17 A18 A19 CS OE WR MEMR MEMW Q5. Explain briefly the 74LS138 decoder. 74LS138 decoder has three inputs (C,B,A) and 8 active low outputs (Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7). There are another three additional enable inputs (G2A, G2B, G1) to enable the decoder. To activate the decoder, the G2A and G2B inputs must be low and G1 must be high. Once 74LS138 is enabled, the address inputs (C, B and A) select which output pin goes low. Following figure shows 74LS138: Page: 4

5 Selection Inputs A B C Y 0 Y 1 Y 2 Y 3 Y 4 Output Enable Inputs G2A G2B G1 Y 5 Y 6 Y 7 Following is the truth table of the decoder 74LS138: INPUTS Enable Select OUTPUTS G2A G2B G1 C B A Y 0 Y 1 Y 2 Y 3 Y 4 Y 5 Y 6 Y 7 1 X X X X X X 1 X X X X X X 0 X X X Q6. Explain briefly memory interface for the addresses F0000H to FFFFFH using eight 2764 EPROMs for 8088 microprocessor based system. A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 F0000H= FFFFFH= F0000H FFFFFH=64KB 2764 EPROM= 8KB and hence total 8 numbers of 2764 EPROM are required. Page: 5

6 The connection is shown below: Address A 0 Data A 12 D 0 D MEMR OE A 13 A 14 A 15 A 17 A 18 A 19 A 16 A B C G1 G2A G2B F0000-F1FFF F2000-F3FFF F4000-F5FFF F6000-F7FFF F8000-F9FFF FA000-FBFFF FC000-FDFFF FE000-FFFFF Q7. Find the address range in the following figure for (a) Y4 (b) Y2 (c) Y7: Address A 0 A 13 A 14 A 15 A 16 A B C Y 0 Y 1 Y 2 Y 3 Data MEMR D 0 D 7 OE 16K X 8 ROM A 17 G2A Y 4 A 18 G2B Y 5 A 19 G1 Y 6 Y 7 (a) The address range for Y4: A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A =F0000H =F3000H Hence, the range of address for Y4 is F0000H to F3000H Page: 6

7 (b) The address range for Y2: A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A =E8000H =EBFFFH Hence, the range of address for Y2 is E8000H to EBFFFH (c) The address range for Y7: A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A =FC000H =FFFFFH Hence, the range of address for Y7 is FC000H to FFFFFH Q8. Find the address range in the following figure for Y4: Address A 0 A 15 A 16 A 17 A 18 A B C Y 0 Y 1 Y 2 Y 3 Data MEMR D 0 D 7 OE 64K X 8 ROM G2A Y 4 G2B Y 5 A 19 G1 Y 6 Y 7 The address range for Y4: A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A =C0000H =CFFFFH Hence, the range of address for Y4 is C0000H to CFFFFH Page: 7

8 Q9. Explain how 74LS138 decodes 2732 EPROMs for 32K x 8 section of memory. Assume the starting address is 40000H EPROM is 4KB memory device. 4K=2 12, hence A0 to A11 are connected to each of the memory devices. Number of memory devices required=32k/4k =8 4K-1=2 12-1= =FFFH Following table shows the address range for different memory devices. Memory device Address range H - 40FFFH H - 41FFFH H - 42FFFH H - 43FFFH H - 44FFFH H - 45FFFH H - 46FFFH H - 47FFFH The range of address is 40000H to 47FFFH. A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A =40000H =47FFFH Following figure shows decodes of 32K x 8 memory section using 2732 memory devices and 74LS138. Page: 8

9 Address A 0 Data A 11 D 0 D MEMR OE A 12 A 13 A 14 A 18 A 15 A 16 A 17 A 19 A B C G1 G2A G2B H - 40FFFH 41000H - 41FFFH 42000H - 42FFFH 43000H - 43FFFH 44000H - 44FFFH 45000H - 45FFFH 46000H - 46FFFH 47000H - 47FFFH Q10. Interface 512KB RAM using 64KB RAM with starting address 80000H. Number of memory devices required=512kb/64kb=8 64K=2 16, hence A0 to A15 are connected to each memory devices. 64K-1=2 16-1= =FFFFH Following table shows the address range for different memory devices. Memory device Address range H 8FFFFH H 9FFFFH 3 A0000H - AFFFFH 4 B0000H - BFFFFH 5 C0000H - CFFFFH 6 D0000H - DFFFFH 7 E0000H - EFFFFH 8 F0000H - FFFFFH The range of address is 80000H to FFFFFH. A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A =80000H =FFFFFH Page: 9

10 Following figure shows decodes 512KB memory section using 64KB memory devices and 74LS138. Address A 0 A 15 Data D 0 D 7 64KB MEMR OE A 16 A 17 A 18 A 19 A B C G1 G2A G2B H 8FFFFH 90000H 9FFFFH A0000H - AFFFFH B0000H - BFFFFH C0000H - CFFFFH D0000H - DFFFFH E0000H - EFFFFH F0000H - FFFFFH Q11. Explain briefly data integrity in ROM and RAM There are many ways to ensure data integrity depending on the type of storage. The checksum method is used for ROM and the parity bit method is used for DRAM. Use of checksum byte for error detection in ROM: To ensure the integrity of the content of ROM, every PC must perform a checksum calculation. The process of checksum will detect any corruption of the contents of the ROM. One of the ROM corruption is current surge, either when the PC is turned on or during operation. The checksum byte is an extra byte that is tagged to the end of a series of bytes of data. Checksum byte is calculated as follows: (i) Add the bytes together and drop the carries. (ii) Take 2 s complement of total sum and that is the checksum byte, which is last byte of the stored information. For example, suppose 4 bytes 25H, 62H, 3FH and 52H are to be stored along with checksum. The sum of 4 bytes is 25H+62H+3FH+52H=118H. Dropping the carry, the byte is 18H and 2 s complement of 18H is E8H. The checksum is E8H. Now, addition of the bytes stores (dropping carry) and checksum should produce result 00H, otherwise the store data have been corrupted. Use of parity bit in DRAM error detection: An extra bit (parity bit) is stored for every byte of data to be stored. With the extra parity bit, every bank requires an extra chip of x1 organization for parity check. There may be a bit change from 1 to 0 of from 0 to 1 due to current surge or certain kinds of particle radiations in the air. Parity is used to detect such errors. Including a parity bit to ensure data integrity in RAM is most widely used method. Page: 10

11 Q12. Assume that we have 4 bytes of hexadecimal data: 25H, 62H, 3FH and 52H. (a) Find the checksum byte. (b) Perform the checksum operation to ensure data integrity. (c) If the second byte had been changed to 22H, show how checksum detect the error. (a) The sum of 4 bytes is 25H+62H+3FH+52H=118H. Dropping the carry, the byte is 18H and 2 s complement of 18H is E8H. The checksum is E8H. (b) Adding all the 4 bytes along with checksum, 25H+62H+3FH+52H+E8H=200H Dropping carry, the byte is 00H. Hence, the data is not corrupted. (c) If 62H is changed to 22H, Then, adding all the 4 bytes along with checksum, 25H+22H+3FH+52H+E8H=1C0H Dropping the carry the byte is C0H. Hence, the data is corrupted. Q13. Explain briefly 16-bit memory interface. In a 16-bit memory interface, memory location 00000H-FFFFFH are separated in Odd and Even banks as shown in the figure blow. Odd Bank (BHE=0) Even Bank (A0=0) D15 D8 D7 D FFFF FFFE Odd and Even Banks of memory To distinguish between odd and even bytes, the microprocessor provides a signal called BHE( Bus High Enable). BHE and A0 are used to select either Odd or Even byte. Following table shows selection of Odd bank or Even bank. BHE A0 0 0 Even word D0-D Odd byte D8-D Even byte D0-D7 1 1 None Page: 11

12 Q14. Explain the 8255 control word format. Following is the control word format for 8255: D7 D6 D5 D4 D3 D2 D1 D0 Group B Port C (Lower) 1=Input 0=Output Port B 1=Input 0=Output Mode selection 0=Mode 0 1=Mode 1 Group A Port C (Upper) 1=Input 0=Output Port A 1=Input 0=Output Mode selection 00=Mode 0 01=Mode 1 1x=Mode 2 1=I/O Mode 0= BSR MOde Q15. Explain briefly the difference between peripheral I/O (Isolated I/O) and memory mapped I/O. Peripheral I/O (Isolated I/O) Memory mapped I/O IN and OUT instructions to be used for data transfer MOV instruction can be used for data transfer between microprocessor accumulator and port. between microprocessor accumulator and port. For example, IN AL,DX ; This instruction load the For example, MOV AL,[2000H] will transfer AL register from the port addressed by DX. data from input port of address 2000H to AL OUT DX, AL ; This instruction load the port register. addressed by DX from AL register. MOV [2010H],AL will transfer data from AL register to output port of address 2010H. Memory space is not used. Memory space is used. Only 16 bits addresses(a0-a15) are decoded. Entire26 bits addresses(a0-a19) are decoded. Limited to 2 16 (65536) ports. Limited to 2 20 ( ) ports Control signals IOR and IOW are used. Control signals MEMR and MEMW are used. Q26. Explain briefly I/O address map of x86 PCs. Designer of the original IBM PC assigned different port addresses to various peripherals. The list of the designated I/O port addresses is referred to as I/O map. Table below shows some of the port addresses those are assigned to different peripherals. Range of port addresses Peripherals 000H-01FH DMA controller 020H-03FH Interrupt controller 040H-05FH Timer 060H-06FH Keyboard 070H-07FH Real time clock, NMI mask Page: 12

13 0F8H-0FFH 1F0H-1F8H 278H-27FH 2F8H-2FFH Math coprocessor Fixed disk Parallel printer port Serial port Q17. (a) Find the control word if PA=out, PB=in, PC0-PC3=in and PC4-PC7=out (b) Write ALP program to get data from port B and send it to the port A. (c) Write ALP program send data from PCL to PCU. Use port addresses of 300H-303H for the 8255 chip. (a) =83H (b).model small.data pa equ 300h pb equ 301h pc equ 302h cwr equ 303h.code mov ax,@data mov ds,ax mov al,83h mov dx,cwr mov dx,pb in al,dx mov dx,pa mov ah,4ch int 21h end (c).model small.data pa equ 300h pb equ 301h pc equ 302h cwr equ 303h.code mov ax,@data mov ds,ax mov al,83h mov dx,cwr mov dx,pc Page: 13

14 in al,dx and al,0fh rol al,1 rol al,1 rol al,1 rol al,1 mov ah,4ch int 21h end Q18. The 8255 shown in the figure below configured as follows: port A as input, B as output and all the bits of port C as output. D0-D7 A A2 A3 IOW IOR A B CL A4 A5 A6 A1 CS CU A7 A8 A9 AEN (a) Find the port addresses assigned to A,B,C and control word register. (b) Find the control byte for this configuration. (c) Program the ports to input data from port A and send it to both port B and port C. (a) The port addresses are as follows: CS A1 A0 Address Port H Port A H Port B H Port C H Control register (b) Control word byte is =90H Page: 14

15 (c).model small.data pa equ 310h pb equ 311h pc equ 312h cwr equ 313h.code mov mov ds,ax mov al,90h mov dx,cwr mov dx,pa in al,dx mov dx,pb mov dx,pc mov ah,4ch int 21h end Q19. Implement a BCD up-down counter on the Logic Controller Interface..model small.stack 64.data pa equ 0b490h pb equ 0b491h pc equ 0b492h cwr equ 0b493h.code mov ax,@data mov ds,ax mov al,82h mov dx,cwr call up_down call delay mov ah,4ch int 21h up_down proc push ax push dx Page: 15

16 mov dx,pa mov al,00h again: call delay inc al cmp al,09h jl again again1: call delay dec al cmp al,00h jg again1 pop dx pop ax ret up_down endp delay proc push bx push cx mov cx,0ffffh outloop:mov bx,0fffh inloop: nop nop dec bx jnz inloop loop outloop pop cx pop bx ret delay endp end Q20. Read the status of two 8-bit inputs(x & Y) from Logic Controller Interface and display X*Y..model small.stack 64.data pa equ 0b490h pb equ 0b491h pc equ 0b492h cwr equ 0b493h x db? y db? msg db 10,13,"2nd number $",10,13 res dw? Page: 16

17 .code mov mov ds,ax mov al,82h mov dx,cwr mov dx,pb in al,dx mov x,al push dx lea dx,msg mov ah,09h int 21h pop dx call delay call delay in al,dx mov y,al mul x mov res,ax mov dx,pa call delay call delay mov al,ah mov ah,4ch int 21h ;delay procedure delay proc push bx push cx mov cx,0ffffh outloop:mov bx,0fffh inloop:nop nop dec bx jnz inloop loop outloop pop cx pop bx ret delay endp end Page: 17

18 Q21. Display messages FIRE and HELP alternately with flickering effects on a 7-segment display interface for a suitable period of time. Ensure a flashing rate that makes it easy to read both messages..model small.stack 64.data msg db 8eh,0cfh,88h,86h ; FIRE msg1 db 89h,86h,0c7h,8ch ; HELP pa equ 0b490h pb equ 0b491h pc equ 0b492h cwr equ 0b493h.code mov ax,@data mov ds,ax mov al,80h mov dx,cwr mov si,0003h repeat1: lea bx,msg[si] call display call delay ;2nd message lea bx,msg1[si] call display call delay mov ah,01h int 16h jz repeat1 mov ah,4ch int 21h ;Display procedure display proc push ax mov ah,04h continue: mov al,[bx] dec bx mov cl,08 again:rol al,01h mov dx,pb push ax mov al,00h mov dx,pc Page: 18

19 mov al,0ffh pop ax loop again dec ah jnz continue pop ax ret display endp ;Delay procedure delay proc push bx push cx mov cx,0ffffh outloop: mov bx,0fffh inloop: nop nop dec bx jnz inloop loop outloop pop cx pop bx ret delay endp end Q22. Drive a stepper motor interface to rotate the motor in specified direction (Clockwise or Counter clockwise) by N steps. Introduce suitable delay between successive steps..model small.stack 64.data n db 100 pa equ 0b490h pb equ 0b491h pc equ 0b492h cwr equ 0b493h.code mov ax,@data mov ds,ax mov al,80h mov dx,cwr mov al,88h Page: 19

20 mov dx,pa mov cl,n again: call delay rol al,01h loop again mov ah,4ch int 21h ;delay procedure delay proc push bx push cx mov cx,0ffffh outloop: mov bx,0fffh inloop: nop nop dec bx jnz inloop loop outloop pop cx pop bx ret delay endp end Page: 20

INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI Note: PUSHF / POPF have no operands The figure below shows that if (SS) = 3000H, (SP) = 0042H, so the execution of POP CX loads CX by the word 4050H form the stack segment. The SP is incremented by 2.