Many analog implementations of CPG exist, typically using operational amplifier or

Transcription

1 FPGA Implementtion of Centrl Pttern Genertor By Jmes J Lin Introuction: Mny nlog implementtions of CPG exist, typiclly using opertionl mplifier or trnsistor level circuits. These types of circuits hve reuce power consumption n cn be reily trnslte from the CPG ynmic eqution. However, one primry isvntge is fixe prmeters. Without fixe prmeters, it is ifficult to crete circuits tht cn generte vrious signls epening on sensory feebck. In this ocument, igitl implementtion of CPG will be propose n nlyze. It is expecte tht the CPG cn be bstrcte; thus, sensory feebck cn tune the oscilltory prmeters. The following is list of the hrwre n softwre tools use in this ocument. Hrwre: Xilinx Virtex 4 ML403 Device/Pckge = 4vfx2 / ff668 SpeeGre = -0 Softwre: MATLAB v7.0.4 Simulink Xilinx DSP System Genertor v7 Centrl Pttern Genertor: The concept of CPG emerges from biologicl systems. Typiclly, in the bse of the spine re group of oscilltory neurons clle the CPG. Together, these neurons generte the rhythmic ptterns tht mp onto locomotive motion. The mthemticl escription of CPG comes in numerous forms. For our implementtion we will choose the Rection-Diffusion CPG eqution. This eqution hs four tunble prmeters: lph, bet, i, n i 2. Our CPG implementtion will store these four vlues in registers, which will llow externl controllers to moify these prmeters. The overll RD CPG stte response is escribe below:

2 x / t = -x + lph*y bet*y2 + i x 2 / t = -x 2 + lph*y + bet*y 2 + i 2 y i = f(x i ) f(x) = 0.5*[bs(x+) - bs(x-)] As bckgroun, the function f is clle the ctivtion function n numerous types exist incluing the sigmoi n rctn. Our piecewise liner ctivtion function is simple pproximtion. Using MATLAB Simulink, this CPG eqution cn be represente by the following simultion circuit in Figure x - -b -b*y2 i.5 lph *y s x' x - -x y Sigmoi x Scope bet x2 Phse Plot -x2 b*y 0.3 i2 s x2' x2 - Gin *y2 y2 Sigmoi Figure : Continuous time implementtion of RD-CPG in Simulink Notice tht there re two primry moules tht re unique to the RD-CPG: the integrtor n the sigmoi function. The interction between these two moules forms the hert of the RD-CPG stte response. A phse plot is shown in Figure 2 n output stte response plot is shown in Figure 3. The input prmeters re chosen s: lph =.5; bet = ; i =.3; i 2 = -.3. These prmeters were selecte by genetic lgorithm progrmme by Jonthn Ty. The etils of this specific prmeter selection will be iscusse in nother ocument.

3 Figure 2: Phse plot Figure 3: Output stte response wveform Notice tht the phse plot forms limit cycle. This implies tht the output stte response will generte stble oscilltory signls. With the esire output wveforms n RD CPG circuit efine, we cn now implement igitl circuit n verify tht it prouces similr properties. FPGA Implementtion of CPG: There re numerous wys to implement CPG igitlly. We hve chosen to use Xilinx DSP System Genertor to progrm our CPG. Using this softwre tool, we hve bstrcte key moules typiclly use in igitl progrmming n my now focus on the esign of our specific ppliction. This prouces more robust n efficient coe. For our igitl implementtion of CPG using FPGA, we cn ivie our lbor into three tsks. The fi tsk is to crete the CPG integrtor n sigmoi block using the System Genertor. The secon tsk is to crete the RD CPG neuron for Verilog genertion. The thir tsk is to configure the FPGA to run the moule.

4 DSP System Genertor: Xilinx prouces mny softwre tools to simplify the esign tsks for hrwre progrmmers. One such progrm is the DSP System Genertor. It interfces with MATLAB Simulink n provies efficient implementtions of igitlly relizble Simulink blocks n commonly use igitl progrmming blocks. This inclues the Aer, Multiplier, Negte, Constnt, Register, Mux, n Comprtor. Another importnt feture of System Genertor is the Gtewy In/Out blocks. These provie the interfce between the ouble precision of Simulink with the floting point rchitecture of the FPGA. Using these bsic blocks, higher-orer blocks n moules cn be crete for our RD CPG. Integrtor n Sigmoi: We begin our System Genertor RD CPG moule using bottom-up pproch. At the hert of the RD CPG is the integrtor n sigmoi block. These blocks hve simple igitl representtions. Integrtion cn be pproximte with Riemnn sum. This implies tht n Aer n Register blocks cn pproximte integrtion. In Figure 4, the integrtor block is shown using these two System Genertor blocks. In xlsub +b b A k =0 xlregister z - q Register Out Figure 4: Integrtor block With regr to the sigmoi block, the output is n - when the input is bove or below n -, otherwise, the output equls the input. Comprtor n Mux blocks re use to implement this function. Shown Figure 5 is the sigmoi block.

5 In - k = 2 - xlreltion <b b Reltionl xlreltion >b b Reltionl2 Figure 5: Sigmoi block hi xlconct ct lo Conct sel 0 xlmux 2 3 Mux Out Notice tht higher-orer blocks cn be quickly crete using the funmentl blocks provie by System Genertor. This reuces our progrmming buren n llows the Xilinx tools to optimize our moule for specific FPGA pltforms. With these System Genertor blocks for integrtion n sigmoi, we hve ll the blocks necessry to implement the RD CPG moule. System Genertor Moel of CPG: Keeping in min tht our gol is to bstrct the RD CPG neuron to provie tunble prmeters, we inten to crete four input ports tht moify the lph, bet, i, n i 2 registers. Shown in Figure 6 is our RD CPG System Genertor moule. InOut Sigmoi i Gtewy I xlregister z - q In In2 Out In3 InOut (-) I In4 Sum Integrtor Negte 2 lph Gtewy Alph xlregister z - q Alph b z -4 (b) -Alph*y2 b z -4 (b) Gtewy x x Alph*y 2 3 bet Gtewy Bet xlregister z - q Bet (-) -Bet b z -4 (b) Gtewy x2 Out2 -Bet*y2 k =0 0 b z -4 (b) Bet*y In 4 i2 Gtewy I2 xlregister z - q I2 In2 Out In3 In4 Sum2 InOut Integrtor2 (-) Negte2 Sigmoi2 In Out Figure 6: RD CPG moule

6 For our igitl implementtion of RD CPG, we hve chosen 2 s complement n 20 bit floting point number with binry point of 5. This choice ws rbitrry n further nlysis will etermine the optiml floting point representtion. Figure 7 shows the simultion testbench n Figure 8 shows the output wveform prouce by the RD CPG circuit. -.3 Sy stem Genertor Constnt.5 Constnt2 Constnt3.3 Constnt4 i x lph bet Out2 i2 CPG Figure 7: Simultion test-bench Scope Phse Plot Figure 8: Output wveform of RD CPG Notice tht the output wveform is iscrete version of Figure 3 n tht the time xis hs been scle. These vritions re expecte since the FPGA moule will smple vlues ccoring to the system clock, which prouces the step shpe of the wveform n ccounts for the time

7 scle. With this successful simultion moel of RD CPG, we will generte the Verilog moule. Figure 9 shows the System Genertor wizr n our Virtex 4 FPGA bor prmeters. Figure 9: System Genertor Wizr