Pipeline Example: Cycle 1. Pipeline Example: Cycle 2. Pipeline Example: Cycle 4. Pipeline Example: Cycle 3. 3 instructions. 3 instructions.

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1 ipeline Exmple: Cycle 1 ipeline Exmple: Cycle X X/ /W X X/ /W $3,$,$1 lw $,0($5) $3,$,$1 3 instructions 8 9 ipeline Exmple: Cycle 3 ipeline Exmple: Cycle X X/ /W X X/ /W sw $6,($7) lw $,0($5) $3,$,$1 sw $6,($7) lw $,0($5) $3,$,$1 3 instructions 10 11

2 ipeline Exmple: Cycle 5 ipeline Exmple: Cycle 6 X X/ /W X X/ /W sw $6,($7) lw $,0($5) sw $6,(7) lw 1 13 ipeline Exmple: Cycle 7 ipeline igrm X X/ /W ipeline igrm: shorthn for wht we just sw cross: cycles own: insns Convention: X mens lw $,0($5) finishes execute stge n writes into X/ ltch t en of cycle $3,$,$1 F X W sw lw $,0($5) F X W sw $6,($7) F X W 1 15

3 Wht bout ipeline Control? ipeline Control houl it be like single-cycle control? ut iniviul insn signls must be stge How mny ifferent control units o we nee? ne for ech insn in pipeline? olution: use simple single-cycle control, but pipeline it ingle controller Key ie: pss control signls with instruction through pipeline X X/ /W xc mc wc CTRL mc wc wc ipeline erformnce Clcultion Why oes Every Tke 5 Cycles? ingle-cycle Clock perio = 50ns, CI = 1 erformnce = 50ns/insn ipeline Clock perio = 1ns (why not 10ns?) CI = 1 (ech insn tkes 5 cycles, but 1 completes ech cycle) erformnce = 1ns/insn 18 X X/ /W $3,$,$1 lw $,0($5) Why not let skip n go stright to W? It wouln t help: pek fetch still only 1 insn per cycle tructurl hzrs: not enough resources per stge for insns 19

4 ipeline Hzrs Hzr: conition les to incorrect execution if not fixe Fixing typiclly increses CI Three kins of hzrs tructurl hzrs Two insns trying to use sme circuit t sme time E.g., structurl hzr on Reg write port Fix by proper I/pipeline esign: 3 rules to follow Ech insn uses every structure exctly once For t most one cycle lwys t sme stge reltive to F hzrs (next) Control hzrs ( little lter) 0 Hzrs X X/ sw $6,0($7) lw $,0($5) Let s forget bout brnches n control for while The sequence of 3 insns we sw erlier execute fine ut it wsn t rel progrm Rel progrms hve t epenences They pss vlues vi registers n memory 1 /W $3,$,$1 Hzrs ory Hzrs X X/ /W X X/ /W sw $3,0($7) i $6,1,$3 $3,$,$1 Woul this progrm execute correctly on this pipeline? Which insns woul execute with correct inputs? is writing its result into $3 in current cycle lw re $3 cycles go got wrong vlue i re $3 1 cycle go got wrong vlue sw is reing $3 this cycle K (regfile timing: write first hlf) lw $,0($1) sw $5,0($1) Wht bout t hzrs through memory? No lw following sw to sme ress in next cycle, gets right vlue Why? re/write tke plce in sme stge hzrs through registers? Yes (previous slie) ccur becuse register write is 3 stges fter register re Cn only re register vlue 3 cycles fter writing it 3

5 Fixing Hzrs Cn only re register vlue 3 cycles fter writing it ne wy to enforce this: mke sure progrms cn t o it Compiler puts two inepenent insns between write/re insn pir If they ren t there lrey Inepenent mens: o not interfere with register in question o not write it: otherwise mening of progrm chnges o not re it: otherwise crete new t hzr Coe scheuling: compiler moves roun existing insns to o this If none cn be foun, must use Ns This is clle softwre interlocks I: icroprocessor w/out Interlocking ipeline tges oftwre Interlock Exmple $3,$,$1 sw $7,0($3) $6,$,$8 i $3,$5, Cn ny of lst 3 insns be scheule between first two? sw $7,0($3)? No, cretes hzr with $3,$,$1 $6,$,$8? K i $3,$5,? No, lw woul re $3 from it till nee one more insn, use $3,$,$1 $6,$,$8 sw $7,0($3) i $3,$5, 5 oftwre Interlock erformnce oftwre interlocks ssume 0% of insns require insertion of 1 ssume 5% of insns require insertion of s CI is still 1 techniclly ut now there re more insns #insns = 1 0.0*1 0.05* = % more insns (30% slowown) ue to t hzrs Hrwre Interlocks roblem with softwre interlocks? Not comptible Where oes 3 in re register 3 cycles fter writing come from? From structure (epth) of pipeline Wht if next I version uses 7 stge pipeline? rogrms compile ssuming 5 stge pipeline will brek better (more comptible) wy: hrwre interlocks rocessor etects t hzrs n fixes them Two spects to this etecting hzrs Fixing hzrs 6 7

6 etecting Hzrs Fixing Hzrs X X/ /W X X/ /W hzr hzr Compre F/ insn input register nmes with output register nmes of oler insns in pipeline Hzr = (F/..R1 == /X..R) (F/..R == /X..R) (F/..R1 == X/..R) (F/..R == X/..R) 8 revent F/ insn from reing (vncing) this cycle Write into /X. (effectively, insert in hrwre) lso cler the tpth control signls isble F/ ltch n write enbles (why?) Re-evlute sitution next cycle 9 Hrwre Interlock Exmple: cycle 1 Hrwre Interlock Exmple: cycle X X/ /W X X/ /W hzr hzr $3,$,$1 $3,$,$1 (F/..R1 == /X..R) (F/..R == /X..R) (F/..R1 == X/..R) (F/..R == X/..R) = 1 30 (F/..R1 == /X..R) (F/..R == /X..R) (F/..R1 == X/..R) (F/..R == X/..R) = 1 31

7 Hrwre Interlock Exmple: cycle 3 ipeline Control Terminology X X/ hzr /W Hrwre interlock mneuver is clle stll or bubble echnism is clle stll logic rt of more generl pipeline control mechnism Controls vncement of insns through pipeline istinguishe from pipeline tpth control Controls tpth t ech stge ipeline control controls vncement of tpth control $3,$,$1 (F/..R1 == /X..R) (F/..R == /X..R) (F/..R1 == X/..R) (F/..R == X/..R) = ipeline igrm with Hzrs hzr stll inicte with * tll propgtes to younger insns This is not K (why?) $3,$,$1 F X W F * * X W sw $6,($7) F X W $3,$,$1 F X W F * * X W sw $6,($7) F X W Hrwre Interlock erformnce Hrwre interlocks: sme s softwre interlocks 0% of insns require 1 cycle stll (i.e., insertion of 1 ) 5% of insns require cycle stll (i.e., insertion of s) CI = 1 0.0*1 0.05* = 1.3 o, either CI stys t 1 n #insns increses 30% (softwre) r, #insns stys t 1 (reltive) n CI increses 30% (hrwre) me ifference nywy, we cn o better 3 35

8 bserve X X/ This sitution seems broken hs lrey re $3 from regfile $3,$,$1 hsn t yet written $3 to regfile ut funmentlly, everything is still K hsn t ctully use $3 yet $3,$,$1 hs lrey compute $3 36 /W $3,$,$1 ypssing X X/ ypssing Reing vlue from n intermeite (µrchitecturl) source Not witing until it is vilble from primry source (Reg) Here, we re bypssing the register file lso clle forwring 37 $3,$,$1 /W WX ypssing LUin ypssing X X/ /W X X/ /W $3,$,$1 $,$,$3 $3,$,$1 Wht bout this combintion? nother bypss pth n UX input First one ws n X bypss This one is WX bypss Cn lso bypss to LU input 38 39

9 W ypssing? ypss Logic X X/ /W X X/ /W sw $3,0($) lw $3,0($) oes W bypssing mke sense? Not to the ress input (ICQ: why not?) ut to the store t input, yes 0 bypss Ech UX hs its own, here it is for UX LUin (/X..R1 == X/..R) mux select = 0 (/X..R1 == /W..R) mux select = 1 Else mux select = 1 ypss n tll Logic Two seprte things tll logic controls pipeline registers ypss logic controls muxes ut complementry For given t hzr: if cn t bypss, must stll lie #0 shows full bypssing: ll bypsses possible Is stll logic still necessry? Yes, Lo utput to LU Input X X/ /W stll $,$,$3 $,$,$3 lw $3,0($) tll = (/X.. == L) && ((F/..R1 == /X..R) ((F/..R == /X..R) && (F/..!= TRE)) 3 lw $3,0($)

10 ipeline igrm With ypssing $3,$,$1 F X W F X W i $6,$,1 F * X W ometimes you will see it like this enotes tht stll logic implemente t X stge, rther thn Equivlent, oesn t mtter when you stll s long s you o $3,$,$1 F X W F X W i $6,$,1 F * X W ipelining n ulti-cycle pertions X/ Wht if you wnte to multi-cycle opertion? E.g., -cycle multiply /W: seprte output ltch connects to W stge Controlle by pipeline control n multiplier F 5 X Xctrl /W ipeline ultiplier Wht bout tll Logic? X/ X/ ultiplier itself is often pipeline: wht oes this men? rouct/multiplicn register/lus/ltches replicte Cn strt ifferent multiply opertions in consecutive cycles /0 0/1 1/ /W /0 0/1 1/ /W tll = (ltlllogic) (F/..R1 == /0..R) (F/..R == /0..R) (F/..R1 == 0/1..R) (F/..R == 0/1..R) (F/..R1 == 1/..R) (F/..R == 1/..R) 6 7

11 ctully, It s omewht Nstier Honestly, It s Even Nstier Thn Tht X/ X/ Wht oes this o? Hint: think bout structurl hzrs tll = (ltlllogic) (F/..R!= null && 0/1..R!= null) 8 /0 0/1 1/ /W n wht bout this? ( WR hzr ) tll = (ltlllogic) (F/..R == /0..R) (F/..R == 0/1..R) 9 /0 0/1 1/ /W ipeline igrm with ultiplier mul $,$3,$5 F W i $6,$,1 F * * * X W This is the sitution tht slie #8 logic tries to voi Two instructions trying to write Reg in sme cycle mul $,$3,$5 F W i $6,$1,1 F X W $5,$6,$10 F X W ore ultiplier Nsties This is the sitution tht slie #9 logic tries to voi is-orere writes to the sme register Compiler thinks gets $ from i, ctully gets it from mul mul $,$3,$5 F W i $,$1,1 F X W $10,$,$6 F X W ulti-cycle opertions complicte pipeline logic They re not impossible, but they require more complexity 50 51