Engineer To Engineer Note

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1 Engineer To Engineer Note EE-208 Technicl Notes on using Anlog Devices' DSP components nd development tools Contct our technicl support by phone: (800) ANALOG-D or e-mil: Or visit our on-line resources nd Considering the ADSP SHARC DSP Contributed by G. Linden September 25, 2003 Introduction The ADSP DSP is the ltest member of the SHARC fmily delivering new levels of speed, power performnce nd peripherl integrtion while mintining code comptibility with the existing SHARC portfolio of products. This document is focused on helping existing SHARC designers who need informtion on evluting whether upgrding systems to the new ADSP is right for them. This note will highlight the new fetures tht the ADSP hs to offer nd detil the list of trditionl SHARC peripherls tht do not exist in this product. The ADSP will be used s the exmple for the trditionl SHARC processor. For more in depth nlysis of ech of the peripherls vilble on the ADSP the ADSP-2126x SHARC Hrdwre Reference Mnul is n excellent resource. Commonlities The ADSP hs lot in common with the previous members of the SHARC fmily in terms of memory nd core functionlity. The seril interfces nd JTAG port re lso lrgely the sme s in the ADSP nd other SHARC products. The ADSP uses the SHARC SIMD core nd runs t 200MHz, twice the speed of the ADSP Becuse the ADSP uses the trditionl 2 nd genertion SIMD SHARC core, existing code written for the core is 100% comptible to the ADSP The ADSP lso provides 2Mbits of on chip dul ported SRAM, twice wht is vilble on the ADSP The efficient model for ccessing dt from memory using the core or IO processor lso remins the sme between both prts. In ddition there is 4Mbit secure ROM tht cn be progrmmed with your personl code t n dditionl fee. While you will find tht some of the peripherl options hve been significntly chnged, the seril interfce protocols re similr to those tht exist in the ADSP There re 6 seril ports vilble on the ADSP nd they support norml mode, I2S nd TDM s well s left justified smple pir mode tht is common to some older CODEC components. The SPORTs re connected to the pins on the DSP through signl routing unit (SRU) which is prt of the Digitl Applictions Interfce (DAI) tht will be discussed in more detil lter in this document. The SPORTs will continue to run t hlf the core processor speed trnslting to 100Mbits/s on the ADSP Additionlly, precision clock genertors (PCG) now enble the DSP to generte low jitter clock for use by externl devices s well s the DSPs own seril ports. In ddition to seril ports, the ADSP supports the SPI protocol in seprte port. While the internl design of the SPI port is not identicl to the ADSP-21161, the functionlity is minly the sme. The mjor difference between the 2 ports is tht ADSP now supports DMA chining on the SPI DMA chnnel. The Copyright 2003, Anlog Devices, Inc. All rights reserved. Anlog Devices ssumes no responsibility for customer product design or the use or ppliction of customers products or for ny infringements of ptents or rights of others which my result from Anlog Devices ssistnce. All trdemrks nd logos re property of their respective holders. Informtion furnished by Anlog Devices Applictions nd Development Tools Engineers is believed to be ccurte nd relible, however no responsibility is ssumed by Anlog Devices regrding technicl ccurcy nd topiclity of the content provided in Anlog Devices Engineer-to-Engineer Notes.

2 trnsmit nd receive DMA chnnels re shred on this prt so DMA trnsfers re not full duplex, lthough they cn be if the core is used or is used in conjunction with DMA. A hrdwre option for SPI mster booting llows the DSP to boot from seril EPROM nd FLASH in ddition to the trditionl SPI slve boot mode tht llows n SPI host to control the booting process on the DSP. The boundry scn nd ICE/debug functionlity provided is the sme s in the previous SHARC fmily processor, sve two functionlity improvements: user defined hrdwre brekpoints nd bckground telemetry chnnels (BTC). The user defined hrdwre brekpoints llow users to progrm hrdwre brekpoints from within their ppliction code insted of mnully through the emultor softwre. The BTC is n enhnced trce cpbility tht llows the emultor to modify some buffers through JTAG without interrupting the core. Importnt Differences One of the gols for the ADSP is to provide flexible nd powerful SHARC in smller pckge tht uses less power nd rel estte for more ttrctive price. A number of mjor chnges hve been mde to fcilitte this philosophy. One of the wys to meet this gol ws to introduce new wy to effectively ccess number of the peripherls through wht we ve termed Digitl Applictions Interfce (DAI). The DAI contins signl routing unit (SRU) tht llows 20 I/O pins to be configured for use by ny of the peripherls in the DAI s well s used s generl purpose I/O. The SRU lso llows peripherls to be connected to ech other internlly without hving to drive the signl out onto the pds of the DSP. A mcro is provided tht mkes it quite simple to connect signls through the SRU, simplifying the underlying hrdwre. In ddition to the seril ports nd the PCG which re mentioned erlier in this document, there is lso n Input Dt Port tht cn cpture dt from 8 seril chnnels nd bring it into the internl memory vi DMA. 3 I/O intervl timers cn be routed through the SRU s well. These timers re in ddition to the progrmmble timer provided in the core. They support PWM, even cpture nd cn hndle wtchdog timing. Ech pin lso hs sttus bit ssocited with it so ll the pins cn be polled. Inputs on these signls cn lso generte interrupts on the DAI port itself through dedicted DAI interrupt controller tht mps DAI interrupts to the core interrupt hndler. The DAI lso contins the Prllel Dt Acquisition Port (PDAP) for bringing in synchronous prllel dt. This configurble 20 pin synchronous port is only cpble of dt cquisition nd cnnot write dt out of the DAI pins. Another wy to bring the pin count down is to reduce the externl port width. Insted of trditionl externl/host port,the ADSP employs Prllel Port (PP). The PP is configurble 8 or 16 bit wide port tht mkes use of totl of 19 pins for dt nd ddressing. The port llows you to ccess externl SRAM vi DMA nd lso llows for booting from n EPROM or FLASH. Becuse of the limited size of the externl port nd the ssocited time constrints tht go with ccessing pcked instructions or dt there is no support for externl execution. The expnded internl memory spce, possibility of using ROM code nd the use of overlys from externl memory will provide ll of the memory requirements for instructions nd dt. There is lso no support for multiprocessing s there ws in previous SHARC fmilies s this requires extensive use of lrge externl bus. The PP nd the PDAP re the only wys for the DSP to cquire prllel dt. The ADSP does not support the link port protocol tht is supported in number of previous SHARCs. Considering the ADSP SHARC DSP (EE-208) Pge 2 of 5

3 Additionl Improvements nd Chnges The ADSP is designed with new stble PLL. In ddition to supporting CLKIN to CORE rtes of 3:1, 8:1 nd 16:1 on powerup the PLL cn be configured dynmiclly to chieve greter power svings by slowing down the core clock or disengging the clock from unused peripherls. Multipliers of 1-32 nd divisors of 2,4,8 nd 16 re supported. The ADSP is not pin comptible option for upgrding from ny of the previous SHARC products. The core voltge hs lso chnged to 1.2V due to chnges in the process nd push for lower power consumption. There re lso some new system design considertions. For customers using the ADSP-2126x with crystl on the CLKIN pins, in deprture from the 06x & 16x, there is no internl shunt resistor, so the designer would need to dd one (we spec 1M-ohm in the dtsheet.) Also, the requirement for properly terminting the JTAG signls when the emultor is not in use hs become more importnt in this product. When designing with this prt, plese consult the updted System Design Chpter in the Hrdwre Reference to better understnd constrints for designing with this product. Conclusion With twice the speed, more memory, lower power nd expnded seril interfce options upgrding to the ADSP cn be wise choice for certin ADSP designs. This document is intended to provide generl overview of wht is new nd wht is not in the ADSP nd the ADSP More indepth nlysis of the ADSP is vilble in the ADSP Dtsheet nd the ADSP-2126x Hrdwre Reference Mnul. Another importnt reference is the section entitled Differences from Previous SHARC DSPs in chpter 1 of the Hrdwre Reference Mnul. The chrt in the ppendix summrizes the mjor differences of the ADSP nd the ADSP SHARC DSPs. Considering the ADSP SHARC DSP (EE-208) Pge 3 of 5

4 Appendix Fetures ADSP ADSP Core mx instruction rte 100MHz 200MHz Core to CLKIN PLL rtios 2::1, 3::1, 4::1 /CLKDBL will double rtios to 4::1, 6::1 nd 8::1 SW Progrmmble (M/N); 3 rtios pin-selectble: 3::1, 8::1, 16::1; Divisors of 2,4,8 or 16; Multipliers of 1-32 Memory On Chip, Dul Port SRAM 1Mbits 2Mbits On Chip, Custom bootble ROM with security fetures 4Mbits Peripherls DMA controller 14 DMA chnnels 22 DMA chnnels SPI Digitl Applictions Interfce (DAI) Seril Port (SPORT) Input Dt Port (IDP) Precision Clock Genertor (PCG) Prllel Dt Acquisition Port (PDAP) 1 port ccessible through DMA nd core; full duplex with dedicted TX nd RX DMA chnnels mx 1/2 core speed (norml mode, I2S, TDM) 1 port ccessible through DMA nd core including chining support; full duplex through the core nd hlf duplex with shred DMA chnnel for TX nd RX Consists of Signl Routing Unit (SRU), Precision Clock Genertor (PCG), Input Dt Port (IDP), Prllel Dt Acquisition Port (PDAP) nd Seril Ports mx 1/2 core speed; routed though the SRU, (norml mode, I2S, Left Justified Smple Pir, TDM) Cptures receive sport dt through 8 DMA chnnels Genertes up to 4 low jitter clock or frme sync signls Cptures up to 20 bits of prllel synchronous dt Multiplexed with other pins; 20 Generl Purpose I/O flgs 4 core flgs; 8 IOP flgs possible routed through the SRU/4 dedicted flgs through the PP Prllel Port (PP) (see Externl Port) Speed 66MB/sec typicl ; 132MB/sec mx Width 8 bit dt mode (24 bit ddress spce); 16 bit dt mode (16 bit ddress spce) Fetures supports overlys Externl Port see (Prllel Port) Considering the ADSP SHARC DSP (EE-208) Pge 4 of 5

5 Speed CLKIN or 2xCLKIN Width 24 bit ddress bus (32 bit dt bus expndble to 48 bits) Fetures Multiprocessor Support, Externl Execution, Overlys Link Ports 2 (nibble or byte wide) (see PDAP or PP for prllel dt cquisition) Boundry Scn nd Enhnced emultion support including JTAG Support Boundry Scn nd bsic emultion support Bckground Telemetry nd Softwre defined brekpoints Temperture Grdes K (0 to 85 C) : C (-40 to 105 C) K (0 to 85 C) : C (-40 to 105 C) Voltge Requirement 1.8V core/ 3.3V IO 1.2V core/ 3.3V IO Pckge 225 BGA 135 bll BGA; 144 pin LQFP Approximte Pricing in 10K volume $21.67 $14.95 for BGA; $16.45 for LQFP Appendix 1. Comprison of the ADSP nd the ADSP References [1] ADSP SHARC DSP Microcomputer Dt Sheet. First Rev A, Anlog Devices, Inc. [2] ADSP SHARC High Performnce Floting-Point Processor Preliminry Dt Sheet. Rev. PrB, Anlog Devices, Inc. Document History Version September 25, 2003 September 3, 2003 by G. Linden Description Title chnge Initil Relese Considering the ADSP SHARC DSP (EE-208) Pge 5 of 5