Introduction to hardware design using VHDL

Transcription

1 Introuction to hrwre esign using VHDL Tim Güneysu n Nele Mentens ECC school Novemer 11, 2017, Nijmegen Outline Implementtion pltforms Introuction to VHDL Hrwre tutoril 1

2 Implementtion pltforms Microprocessor FPGA = Fiel-Progrmmle Gte Arry ASIC = Appliction-Specific Integrte Circuit Implementtion pltforms Microprocessor rchitecture The CPU is the hert of microprocessor n contins.o.: ALU (Arithmetic Logic Unit) register file progrm memory Exmple: AVR 2

3 Implementtion pltforms esign flow esign entry Microprocessor C, Jv, compiler ssemly progrm ssemler oject files The hrwre rchitecture of microprocessor is fixe The coe escries wht shoul e execute on the fixe hrwre The instructions en up in the progrm memory linker executle loer memory Implementtion pltforms Fiel-Progrmmle Gte Arrry (FPGA) rchitecture Bsic components: CLB = Configurle Logic Block CLBs consist of slices. Slices consist of Look-Up Tles (LUTs), Multiplexers, Flip-Flops (FFs), Crry logic. SM = Switch Mtrix IOB = Input/Output Block 3

4 Implementtion pltforms Fiel-Progrmmle Gte Arrry (FPGA) sic content of slice Look-Up Tle (LUT) Flip-Flop (FF) Implementtion pltforms Fiel-Progrmmle Gte Arrry (FPGA) sic principle of switch mtrix 4

5 Implementtion pltforms Fiel-Progrmmle Gte Arrry (FPGA) esign flow esign entry synthesis mpping + plce & route schemtic, HDL, netlist itstrem genertion FPGA configurtion physicl lyout itstrem The hrwre rchitecture of n FPGA is configurle The coe escries the hrwre tht we nee The itstrem ens up in the configurtion memory The re is mesure in terms of occupie LUTs, flip-flops, eicte hrwre locks Implementtion pltforms Appliction-Specific Integrte Circuit (ASIC) rchitecture Bsic components: Stnr cells from stnr cell lirry Logic cells n sequentil cells 5

6 Implementtion pltforms Appliction-Specific Integrte Circuit (ASIC) esign flow esign entry synthesis floorplnnnig + plce & route friction pckging schemtic, HDL, netlist physicl lyout wfer The hrwre rchitecture of n ASIC is fixe The coe escries the hrwre tht we nee The GDS file contins the physicl informtion tht goes to the founry The re is mesure in terms of the numer of equivlent NAND gtes (Gte Equivlent = GE) Implementtion pltforms Comprison HW HW-SW SW ASIC FPGA Domin specific DSP VLIW Generl purpose Are efficiency High Low Performnce/Energy unit Low High Progrmmility 6

7 Introuction to VHDL Stnr VHDL (VHSIC Hrwre Description Lnguge) VHSIC = Very High Spee Integrte Circuit Interntionl stnr First stnr: IEEE Most recent upte: IEEE Introuction to VHDL Hrwre vs. softwre Description lnguge for hrwre progrmming lnguge Progrmming lnguge (e.g. C): hrwre = processor hrwre is lrey esigne, implemente n fricte coe: escries how the hrwre will e use coe is compile for specific processor Hrwre escription lnguge (e.g. VHDL) hrwre = FPGA or ASIC esign hrwre is esigne coe: escries which hrwre will e esigne coe is synthesize for specific FPGA or ASIC technology exmple: c <= n ; e <= c or ; e <= c or ; c <= n ; c e 2x the sme implementtion 7

8 Introuction to VHDL Entities n rchitectures The VHDL coe of ech component consists of n interfce escription: entity, ehviorl escription: rchitecture. Exmple: c e e entity n_or_gte is port( en n_or_gte;,, : in it; e: out it); rchitecture rch of n_or_gte is signl c: it; c <= n ; e <= c or ; en rch; Introuction to VHDL Hierrchy Hierrchy cn e uilt in. There is hierrchy when component contins n instntition of nother component. c n_or_xor_gte n_or_gte e f e entity n_or_xor_gte is port(,, c, : in it; e: out it); en n_or_xor_gte; rchitecture rch of n_or_xor_gte is component n_or_gte is port(,, : in it; e: out it); en component; signl f: it; inst_n_or_gte: n_or_gte port mp( =>, =>, => c, e => f); e <= xor f; en rch; 8

9 Hierrchy cn e uilt in. There is hierrchy when component contins n instntition of nother component. c n_or_xor_gte n_or_gte inst_n_or_gte: n_or_gte port mp(,, c, f); e f Introuction to VHDL Hierrchy e entity n_or_xor_gte is port(,, c, : in it; e: out it); en n_or_xor_gte; rchitecture rch of n_or_xor_gte is component n_or_gte is port(,, : in it; e: out it); en component; signl f: it; inst_n_or_gte: n_or_gte port mp( =>, =>, => c, e => f); e <= xor f; en rch; orer must e correct Introuction to VHDL it vs. st_logic The pckge st_logic_1164 in lirry ieee contins.o. the types st_ulogic en st_logic, consisting of 9 vlues (inste of 2 for it ) type st_ulogic is ( U, -- Uninitilize X, -- Forcing Unknown 0, -- Forcing 0 1, -- Forcing 1 Z, -- High Impence W, -- Wek Unknown L, -- Wek 0 H, -- Wek 1 -, -- Don t Cre); sutype st_logic is resolve st_ulogic; type st_ulogic_vector is rry (NATURAL rnge <>) of st_ulogic; type st_logic_vector is rry (NATURAL rnge <>) of st_logic; signl,, z: st_logic; z <= ; z <= ;? z It is vise to lwys use st_logic inste of it 9

10 Introuction to VHDL Concurrent n sequentil sttements Concurrent sttements: re implement in prllel n execute t the sme time Sequentil sttements: cn only occur in process exmple: entity mux is port(,, s: in st_logic; z: out st_logic); en mux; rchitecture rch of mux is p1: process(,, s) if s = 1 then z <= ; else z <= ; en if; en process; en rch; sensitivity list s 1 0 z Introuction to VHDL Storge elements D-flipflop: clk q lirry ieee; use ieee.st_logic_1164.ll; entity ff is port(, clk: in st_logic; q: out st_logic); en ff; rchitecture rch of ff is store: process(clk) if clk event n clk = 1 then q <= ; en if; en process; en rch; 10

11 Introuction to VHDL Storge elements D-flipflop with synchronous reset: rst lirry ieee; use ieee.st_logic_1164.ll; entity ff is port(, clk, rst: in st_logic; q: out st_logic); en ff; clk q rchitecture rch of ff is store: process(rst, clk) if rst = 1 then q <= 0 ; elsif clk event n clk = 1 then q <= ; en if; en process; en rch; D-flipflop with synchronous reset: Introuction to VHDL Storge elements lirry ieee; use ieee.st_logic_1164.ll; entity ff is port(, clk, rst: in st_logic; q: out st_logic); en ff; rst clk q rchitecture rch of ff is store: process(clk) if clk event n clk = 1 then if rst = 1 then q <= 0 ; else q <= ; en if; en if; en process; en rch; 11

12 Introuction to VHDL Storge elements D-flipflop with enle: lirry ieee; use ieee.st_logic_1164.ll; enle entity ff is port(, clk, enle: in st_logic; q: out st_logic); en ff; q clk 1 0 q rchitecture rch of ff is store: process(clk) if clk event n clk = 1 then if enle = 1 then q <= ; en if; en if; en process; en rch; Introuction to VHDL Moules with prmeters Register with prmeterizle with: lirry ieee; use ieee.st_logic_1164.ll; clk n n q entity ffn is generic(size: integer:=4); port( clk: in st_logic; : in st_logic_vector(size-1 ownto 0); q: out st_logic_vector(size-1 ownto 0)); en ffn; rchitecture rch of ffn is p: process(clk) if clk event n clk = 1 then q <= ; en if; en process; en rch; 12

13 Simultion A VHDL moule cn e simulte with testench: Also written in VHDL No ports in the entity Contining n instntition of the evice uner test (DUT) Input signls re pplie internlly in the testench Output signls re evlute Through wveforms in simultion winow In text file DUT testench Hrwre tutoril 4-it er n-it er 4-it moulr er EXERCISE: n-it moulr er n-it moulr er/sutrcter n-it moulr constnt multiplier (multipliction y 5) EXERCISE: n-it moulr multiplier through consecutive itions EXERCISE: n-it moulr multiplier through left-to-right moulr oule-n- 4xn-it register file EXERCISE: elliptic curve point ouling 13

14 For ech moule, the VHDL coe for the moule n the VHDL coe for the testench re given Where it sys EXERCISE, the VHDL coe for the moule nees to e complete The tutoril will cover synthesis n postsynthesis (ehviorl) simultion Hrwre tutoril esign flow esign entry synthesis mpping + plce & route schemtic, HDL, netlist itstrem genertion FPGA configurtion physicl lyout itstrem 14