Computer Architecture ELEC3441

Transcription

1 Computer Architecture ELEC3441 Lecture 13 ulti-core Processors Dr. Hayde Kwok-Hay o 100,000 10,000 Departmet of Electrical ad Electroic Egieerig 1 Performace (vs. VAX-11/780) Ed of a Era AX-11/780, 5 Hz tel Xeo 6 cores, 3.3 GHz (boost to 3.6 GHz) tel Xeo 4 cores, 3.3 GHz (boost to 3.6 GHz) tel Core i7 Extreme 4 cores 3.2 GHz (boost to 3.5 GHz) tel Core Duo Extreme 2 cores, 3.0 GHz tel Core 2 Extreme 2 cores, 2.9 GHz AD Athlo 64, 2.8 GHz 11,865 14,38719,484 AD Athlo, 2.6 GHz tel Xeo EE 3.2 GHz 7,108 tel D850EVR motherboard (3.06 GHz, Petium 4 processor with Hyper-Threadig Techology) 6,043 6,681 B Power4, 1.3 GHz 4,195 tel VC820 motherboard, 1.0 GHz Petium processor 3,016 Professioal Workstatio XP1000, 667 Hz 21264A 1,779 Digital Alphaerver /575, 575 Hz , Alphaerver /600, 600 Hz Digital Alphastatio 5/500, 500 Hz Digital Alphastatio 5/300, 300 Hz %/year Digital Alphastatio 4/266, 266 Hz 183 B POWERstatio 100, 150 Hz 117 Digital 3000 AXP/500, 150 Hz 80 HP 9000/750, 66 Hz 51 B R6000/540, 30 Hz 24 52%/year P 2000, 25 Hz P /120, 16.7 Hz u-4/260, 16.7 Hz 9 VAX 8700, 22 Hz 5 Limited by Power, LP, emory speed 24,129 21,871 25%/year 1.5, VAX-11/ d sem. ' Ways to Achieve Parallelism structio Level Parallelism (LP) Parallel operatios come from istructios that execute i parallel Dyamic: uper-scalar processor, OOO executio tatic: VLW Data Level Parallelism (DLP) Parallel operatios come from cocurret operatio o idepedet data Vector machies, D extesios Thread Level Parallelism 2d sem. ' d sem. '

2 Coectig Cores ultiprocessor ystems o a Chip achies with more tha 1 processors was popular amog servers ad supercomputers i the 80 ad 90s Uiprocessor speed comes to a halt due to power wall All major processor vedors move to multi-core desigs O-chip Network hared emory hared memory ulti-processor board level 2d sem. '17-18 Chip ulti-processor 5 Direct Coectios 2d sem. '17-18 Direct Network 6 Network Typology Usually i the form of low latecy, high throughput, poit-to-poit etwork betwee processors By pass /O subsystems Allows low-latecy commuicatio betwee eighborig processors mesh rig ometimes with dedicated machie istructios ulti-hop routig for further processors Typology of etwork plays a importat role e.g. Rig, torus, mesh Ofte tie to the distributed memory system Ofte proprietary desig Commercial examples: torus AD: HyperTrasport tel: QuickPath tercoect 2d sem. ' d sem. '

3 O-chip Network The study of buildig etwork i system-o-chip A complete computer system o a chip cludig graphics, peripheral ad memory cotrollers, accelerators PoC: multi-processor system o a chip ultiple compute core i the system ostly proprietary ome example of o-chip etwork: Advaced icrocotroller Bus Architecture (ABA): o-chip itercoect developed by AR Wishboe: OpeCore stadard 2d sem. ' hared memory cores Commo typology for commercial multi-core processors Various combiatio of shared ad private cache/memory $ ai emory hared L2$ D$ Core $ D$ Core e.g. tel Core, Core 2 ai emory 2d sem. ' $ hared L3$ L2$ L2$ D$ Core $ D$ Core e.g. tel Nehalem, ady Bridge, vy Bridge ymmetric ultiprocessors Processor emory symmetric All memory is equally far away from all processors Ay processor ca do ay /O (set up a DA trasfer) -emory bus /O cotroller bridge /O bus /O cotroller Graphics output Processor /O cotroller Networks ychroizatio The eed for sychroizatio arises wheever there are cocurret processes i a system (eve i a uiprocessor system) Two classes of sychroizatio: Producer-Cosumer: A cosumer process must wait util the producer process has produced data utual Exclusio: Esure that oly oe process uses a resource at a give time producer P1 cosumer P2 hared Resource 11 12

4 buf* tail; buf* head; A Producer-Cosumer Example Producer tail Producer postig tem x: Load R tail, 0(tail) tore 0(R tail ), x R tail =R tail +1 tore 0(tail), R tail Problems? head The program is writte assumig istructios are executed i order. Cosumer R tail R tail R head R equetial Cosistecy A emory odel P P P P P P Cosumer: Load R head, 0(head) spi: Load R tail, 0(tail) if R head ==R tail goto spi Load R, 0(R head ) R head =R head +1 tore 0(head), R head process(r) A system is sequetially cosistet if the result of ay executio is the same as if the operatios of all the processors were executed i some sequetial order, ad the operatios of each idividual processor appear i the order specified by the program Leslie Lamport equetial Cosistecy = arbitrary order-preservig iterleavig of memory refereces of sequetial programs A Producer-Cosumer Example cotiued Producer postig tem x: Load R tail, 0(tail) 1 tore 0(R tail ), x R tail =R tail +1 2 tore 0(tail), R tail Ca the tail poiter get updated before the item x is stored? Programmer assumes that if 3 happes after 2, the 4 happes after 1. Problem sequeces are: 2, 3, 4, 1 4, 1, 2, 3 equetial Cosistecy Cosumer: Load R head, 0(head) spi: Load R tail, 0(tail) 3 if R head ==R tail goto spi Load R, 0(R head ) 4 R head =R head +1 tore 0(head), R head process(r) equetial cocurret tasks: T1, T2 hared variables: X, Y (iitially, Y = 10) T1: T2: tore (X), 1 #X ç 1 Load R 1, (Y) tore (Y), 11 #Y ç 11 tore (Y ), R 1 #Y ç Y Load R 2, (X) tore (X ), R 2 #X ç X what are the legitimate aswers for X ad Y? (X,Y ) e {(1,11), (0,10), (1,10), (0,11)}? f y is 11 the x caot be

5 equetial Cosistecy ssues i mplemetig equetial Cosistecy equetial cosistecy imposes more memory orderig costraits tha those imposed by uiprocessor program depedecies ( ) P P P P P P What are these i our example? mplemetatio of C is complicated by two issues T1: T2: tore (X), 1 #Xç1 Load R 1, (Y) tore (Y), 11#Yç11 tore (Y ), R 1 #Y çy Load R 2, (X) additioal C requiremets tore (X ), R 2 #X çx Out-of-order executio capability Load(a); Load(b) yes Load(a); tore(b) yes if a ¹ b tore(a); Load(b) yes if a ¹ b tore(a); tore(b) yes if a ¹ b Does (ca) a system with caches or out-of-order executio capability provide a sequetially cosistet view of the memory? more o this later s s ca prevet the effect of a store from beig see by other processors No commo commercial architecture has a sequetially cosistet memory model! emory Feces structios to serialize memory accesses emory Coherece i Ps Processors with relaxed or weak memory models (i.e., permit Loads ad tores to differet addresses to be reordered) eed to provide memory fece istructios to force the serializatio of memory accesses -1 A 100 cache-1-2 A 100 cache-2 Examples of processors with relaxed memory models: parc V8 (TO,PO): embar parc V9 (RO): embar #LoadLoad, embar #Loadtore embar #toreload, embar #toretore PowerPC (WO): yc, EEO AR: DB (Data emory Barrier) X86/64: mfece (Global emory Barrier) emory feces are expesive operatios, however, oe pays the cost of serializatio oly whe it is required -emory bus A 100 memory uppose -1 updates A to 200. write-back: memory ad cache-2 have stale values write-through: cache-2 has a stale value Do these stale values matter? What is the view of shared memory for programmig? 19 20

6 Write-back s & C Write-through s & C T1 is executed prog T1 T X, 1 T Y,11 cache-1 writes back Y T2 executed cache-1 writes back X cache-2 writes back X & Y cache-1 memory Y =10 X = 1 X = cache-2 Y = X = Y = X = Y = Y = prog T2 LD Y, R1 T Y, R1 LD X, R2 T X,R2 icosistet T1 executed T2 executed prog T1 T X, 1 T Y,11 cache-1 X= 0 Y=10 memory Y =10 X = 1 X = cache-2 Y = Y = Y = Write-through caches do t preserve sequetial cosistecy either prog T2 LD Y, R1 T Y, R1 LD X, R2 T X,R aitaiig Coherece Hardware support is required such that oly oe processor at a time has write permissio for a locatio o processor ca load a stale copy of the locatio after a write è cache coherece protocols Coherece vs. emory Cosistecy A cache coherece protocol esures that all writes by oe processor are evetually visible to other processors, for oe memory address i.e., updates are ot lost A memory cosistecy model gives the rules o whe a write by oe processor ca be observed by a read o aother, across differet addresses Equivaletly, what values ca be see by a load A cache coherece protocol is ot eough to esure sequetial cosistecy But if sequetially cosistet, the caches must be coheret Combiatio of cache coherece protocol plus processor memory reorder buffer used to implemet a give architecture s memory cosistecy model 23 24

7 oopy, Goodma 1983 dea: Have cache watch (or soop upo) DA trasfers, ad the do the right thig oopy cache tags are dual-ported hared emory ultiprocessor emory Bus Used to drive emory Bus whe is Bus aster 1 oopy Physical emory Proc. A R/W D Tags ad tate Data (lies) A R/W oopy read port attached to emory Bus 2 3 oopy oopy DA DK Use soopy mechaism to keep all processors view of memory coheret oopy Coherece Protocols write miss: the address is ivalidated i all other caches before the write is performed read miss: if a dirty copy is foud i some cache, a writeback is performed before the memory is read tate Trasitio Diagram The protocol Each cache lie has state bits state bits Address tag Read miss (P1 gets lie from memory) Read by ay processor (P1 gets lie from memory) reads (P 1 writes back) P 1 itet to write itet to write : odified : hared : valid or writes itet to write (P 1 writes back) state i processor P

8 Two Processor Example (Readig ad writig the same cache lie) Observatio P 1 writes P 2 reads P 2 writes P 1 writes P 2 writes P 1 writes P 1 Read miss P 2 Read miss P 2 reads, P 1 writes back P 1 itet to write P 2 itet to write, P 2 writes back P 2 itet to write P 1 itet to write or writes P 2 itet to write P 2 reads or writes P 1 itet to write Read miss Read by ay processor reads P 1 writes back P 1 itet to write itet to write f a lie is i the state the o other cache ca have a copy of the lie! emory stays coheret, multiple differig copies caot exist or writes itet to write E: A Ehaced protocol icreased performace for private data Optimized oop with Level-2 s Each cache lie has a tag state bits Address tag P 1 write or read reads P 1 writes back Read miss, shared Read by ay processor P 1 itet to write P 1 write itet to write : odified Exclusive E: Exclusive but umodified : hared : valid Other processor reads itet to write, P1 writes back E P 1 read Read miss, ot shared itet to write state i processor P 1 31 $ L2 $ $ L2 $ $ L2 $ $ L2 $ ooper ooper ooper ooper Processors ofte have two-level caches small, large L2 (usually both o chip ow) clusio property: etries i must be i L2 ivalidatio i L2 è ivalidatio i oopig o L2 does ot affect - badwidth What problem could occur? 32

9 tervetio False harig -1 A 200 cache-1 -emory bus A cache-2 memory (stale data) Whe a read-miss for A occurs i cache-2, a read request for A is placed o the bus -1 eeds to supply & chage its state to shared The memory may respod to the request also! Does memory kow it has stale data? -1 eeds to itervee through memory cotroller to supply correct data to cache-2 Out-of-Order Loads/tores & CC load/store buffers sooper Wb-req, v-req, v-rep (//E) Blockig caches Oe request at a time + CC Þ C No-blockig caches pushout (Wb-rep) (-rep, E-rep) (-req, E-req) emory ultiple requests (differet addresses) cocurretly + CC Þ Relaxed memory models CC esures that all processors observe the same order of loads ad stores to a address 33 /emory terface state lie addr data0 data1... datan A cache lie cotais more tha oe word -coherece is doe at the lie-level ad ot word-level uppose 1 writes word i ad 2 writes word k ad both words have the same lie address. What ca happe? Ackowledgemets These slides cotai material developed ad copyright by: Arvid (T) Krste Asaovic (T/UCB) Joel Emer (tel/t) James Hoe (CU) Joh Kubiatowicz (UCB) David Patterso (UCB) Joh Lazzaro (UCB) T material derived from course UCB material derived from course C152, C d sem. '