A collection of open-sourced RISC-V processors

Transcription

1 Riscy Processors A collectio of ope-sourced RISC-V processors Ady Wright, Sizhuo Zhag, Thomas Bourgeat, Murali Vijayaraghava, Jamey Hicks, Arvid Computatio Structures Group, CSAIL, MIT 4 th RISC-V Workshop 1

2 MIT s Riscy Expeditio Advisors Profs. Arvid ad Adam Chlipala Motivatios: Formal Specificatio Formally Verified Processor Implemetatios Memory Cosistecy Models Accelerators Microarchitectural Exploratio ASIC Sythesis eed flexible RISC-V Implemetatios 2

3 Chips with Proofs Full RISC-V Chip lots of effort required Full Chip Proof Build up processors ad proofs modularly to reduce desig ad proof effort RISC-V Modules Modular Proofs Less effort required 3

4 Curret Riscy Offerigs Buildig Blocks for Processor Desig: Riscy Processor Library Riscy BSV Utility Library Referece Processor Implemetatios: Multicycle I-Order Pipelied Out-of-Order Executio (to be released shortly) All implemetatios boot Liux w/ paged virtual memory Ifrastructure: Coectal Tadem Verificatio A flexible way of desigig processors leveragig Bluespec System Verilog (BSV) 4

5 Processor Buildig Blocks Riscy Proc Library Riscy Util Library Decode Reg File EHR Search FIFO ALU Divide RW BRAM Server Util FPU CSR File Multiply MemOp Bridge Cocat Reg Prit Trace Perf Moitor FIFOG MMU Cache 5

6 Coectig Modules Method Defiitio Coectios through glue logic Modules ca act as glue logic Exteral Method Call Direct coectio Modules with exteral method calls are ope modules. Those without are closed modules. 6

7 Iitial Processor Multicycle Basic FSM without Caches Core Decode Reg File ALU CSR File extra logic FPU MMU MemOp Bridge MMU MemOp Bridge FeceReq VMIfo Memory System Mai Memory IO 7

8 Iitial Processor Multicycle Addig Caches ad TLBs Core Decode Reg File ALU CSR File extra logic FPU MemOp MemOp MMU ITLB I$ DTLB MMU D$ Bridge Bridge FeceReq VMIfo Memory System Mai Memory IO 8

9 Iitial Processor Multicycle Split Frot ad Back FSMs Frot Ed Decode Reg File ALU CSR File extra logic extra logic FPU Back Ed ITLB I$ DTLB D$ FeceReq VMIfo Memory System Mai Memory IO 9

10 Processor Implemetatios I-Order Pipelied Frot Ed Pipelied Fetch, Brach Predictio, ad Decode Back Ed Pipelied Register Read, Execute, Memory, ad Write Back Memory System Mai Memory IO 10

11 Processor Implemetatios Out-of-Order Executio Frot Ed Pipelied Fetch, Brach Predictio, ad Decode Back Ed Pipelied Register Read, Register Reamig, Issue, Execute, Memory, ad Write Dispatch, Execute, ad Commit Back Memory System Mai Memory IO 11

12 Processor Implemetatios Out-of-Order Executio Back-Ed Reg Reamig Reorder Buffer Commit Reservatio Statio Ld/St Q Execute Execute Rules Execute Rules Rules Fiish Physical Reg File CSR File DTLB D$ 12

13 How is modular desig possible? RTL modules are ot modularly refiable uder compositio Implemetatio details of oe module may put additioal costraits o aother module Bluespec System Verilog supports composability through: Iterface method abstractio Implicit guards o methods Guarded Atomic Actios 13

14 Bluespec System Verilog (BSV) High-Level Sythesis laguage Executio model built upo guarded atomic actios (called rules) Rule ca oly chage the state of a module if its guard (or coditio) is true The compiler adds logic to specify whe rules fire Rules must have its explicit guard ad all implicit guards for module method calls satisfied Rules must appear to fire atomically (or sequetially oe-rule-at-a-time sematics) 14

15 FIFO Iterface Iterface FIFO#(type t); method Actio eq(t x); method t first; method Actio deq; editerface eq FIFO first deq Implicit guards prevet equeuig ito a full FIFO or dequeuig from a empty FIFO 15

16 Coectig Modules with Rules Buffer 1 deq Move pkt B1 to B2 eq Buffer 2 kill Kill pkt w/ id kill A packet will be killed either before the move i buffer 1, or after the move i buffer 2 Suppose either buffer kills the curret equeuig/dequeuig packet Atomicity bug i Verilog Bluespec compiler itroduces extra logic to prevet cocurret move ad kill 16

17 Processor Desig Flow Riscy Blocks Iitial Coectios focus o fuctioality Modular Refiemet Schedulig Optimizatio BSV Schedulig logic may be hurtig performace EHR trasformatios for performace Specialized processor for desired applicatio 17

18 Schedulig Optimizatio Itroductio Buffer 1 deq Move pkt B1 to B2 eq Buffer 2 kill Kill pkt w/ id kill To eable Move ad Kill to fire cocurretly, they eed a apparet orderig (or schedule) If the buffer s methods do t support the schedule, use EHR refiemet withi the buffers to achieve the ecessary schedulig 18

19 Schedulig Optimizatio method deq if (r!= ivalid); r <= ivalid; retur r; method kill(tag); if (r.tag == tag) r <= ivalid; Buffer 1 Reg r r w kill deq 19

20 Schedulig Optimizatio method deq if (r[1]!= ivalid); r[1] <= ivalid; retur r[1]; method kill(tag); if (r[0].tag == tag) r[0] <= ivalid; Buffer 1 r Ehr r w kill r w deq For more iformatio about EHRs, see The Ephemeral History Register: Flexible Schedulig for Rule-Based Desigs by Daiel Rosebad 20

21 Processor Iterface Mai Memory Req/Resp MMIO Req/Resp mkproc Exteral Iterrupt Cotrol/Cofiguratio HTIF ToHost/FromHost Debuggig Methods Get Verificatio Packet Processor Devices, Accelerators, ad Ifrastructure 21

22 Coectal Ifrastructure PCIe FPGA Boards Host Computer VC707 FPGA RV64G BSV PCIe DRAM HTIF/Fesvr Spike Tadem Verificatio Test Program Loadig Device Emulatio Coectal implemets this coectio 22

23 Coectal Ifrastructure Simulatio Host Computer Host Computer Bluesim RV64G BSV Uix Socket DRAM HTIF/Fesvr Spike Tadem Verificatio Test Program Loadig Device Emulatio Coectal implemets this coectio 23

24 Coectal Ifrastructure Zyq Chips Zyq ARM core Zyq FPGA Fabric RV64G BSV Axi DRAM HTIF/Fesvr Spike Tadem Verificatio Test Program Loadig Device Emulatio ARM core ruig same code as host i previous slide 24

25 Tadem Verificatio Riscy Proc Commit Stage Verificatio Packets pc, istructio, data, exceptios, etc. Spike Sychroize Simulate Compare Ru the same program o two RISC-V implemetatios at oce Geerate verificatio packets at commit stage Use o-determiistic iformatio from the implemetatio uder test for sychroizatio Compare results 25

26 Project Status Available ow: Riscy Processor Library Riscy BSV Utility Library Example multicycle processors Comig soo: High-performace I-Order processor Out-of-Order processor ad modules Multicore processors Plaed work: Formal specificatios Proofs for modules Proofs for processors 26

27 Questios? 27

28 Backup Slides 28

29 Schedulig Optimizatio I Processor Desig Flow Choosig Schedules Typically close to reverse pipelie order, but very depedet o microarchitecture Adaptig modules to schedule Registers that prevet desired schedule should be replaced with EHRs EHRs add bypass paths betwee rules without breakig atomicity For more iformatio about EHRs, see The Ephemeral History Register: Flexible Schedulig for Rule-Based Desigs by Daiel Rosebad 29

30 Schedulig Optimizatio Cosequeces of Schedule Choice Locatio of cocurrecy logic I the Move ad Kill example, which buffer is i charge of killig movig istructios? Oe locatio may be more efficiet tha aother Existece of bypassig logic to skip latecy Schedulig ca allow some redirectig rules to update the fetch pc i the same cycle while other redirectig rules update the fetch pc for the ext cycle Priority betwee cosumers of shared resources Schedulig ca determie priority for ports i a arbiters 30

31 Schedulig Optimizatio Out-of-Order Executio Example Isert Busy Table Orderig of Isert ad Fiish determies where bypass path is implemeted Reservatio Statio Fiish Orderig of Isert ad Execute determies if a istructio ca be executed i the same cycle it iserts the reservatio statio Execute To fuctioal uit Reg File From fuctioal uit Orderig of Execute ad Fiish determies if a istructio ca be executed i the same cycle its registers become ready 31

32 Coectig Modules Buffer 1 deq Move value eq Buffer 2 ic ic Buffer 1 deq behavior do t icremet icremet Icremet Buffer 2 eq behavior do t icremet icremet The implemetatios of these two buffers are ot idepedet i typical HDLs. This prevets modular desig/refiemet. 32