Lecture Topics ECE 341. Lecture # 6. CLA Delay Calculation. CLA Fan-in Limitation

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1 EE 34 Lecture # 6 Instructor: Zeshan hishti zeshan@pdx.edu October 5, 24 Lecture Topics Design of Fast dders arry Looakaheaddders (L) Blocked arry-lookahead dders ultiplication of Unsigned Numbers rray ultiplier Sequential ircuit ultiplier Reference: hapter 9: Sections 9.2 and 9.3 Portland State University L Delay alculation L Fan-in Limitation onsider the expression: c i+ = G i + P i G i- + P i P i- G i P i P i-.p G + P i P i-.p c ll the G i and P i functions can be obtained in parallel in onegate delay ND terms in each c i+ calculation require oneadditional gate delay ORingthe ND terms in each c i+ calculation requires oneadditional gate delay Therefore, Total delay in calculating carryoutputs = + + = 3gate delays Sum outputs require one additional XOR delay after carries are computed Total delay in calculating sumoutputs = 3 + = 4gate delays Performingn-bit L in 4 gate delays, independent of n, good only in theory In practice, L is limited by fan-in constraints c i+ = G i + P i G i- + P i P i- G i P i P i-.p G + P i P i-.p c OR gate & last ND gate in the expression for c i+ require i+2 inputs, each For a 4-bit L, the SB carry-out (c 4 ) requires a fan-in of 5 5 is the practical fan-in limit for most gates In order to add operands larger than 4-bits, we can cascade multiple Ls ascade of Ls is called Blocked arry-lookahead adder n-bit L requires 4 gate delays independent of n

2 Blocked arry-looakhead dder Faster Blocked arry-lookahead adder x 3-28 y 3-28 c c. c bit 4-bit L s 3 s 3 s 29 s 28 x 7-4 L y 7-4 s 4 s 5 s 6 s 7 c 4 x 3- y 3-4-bit L s s s 2 s 3 fter input operands (X, Y and c ) are applied to the 32-bit adder: ll the P i and G i terms in each L calculated in parallel in gate delay c 4 available after 3gate delays c 8 available 2 gate delays after c 4 = 3 + (*2) = 5gate delays c 2 available (2*2) gate delays after c 4 = 3 + (2*2) = 7gate delays c 6 available after (3*2) gate delays after c 4 = 3 + (3*2) = 9gate delays c 32 available after (7*2) gate delays after c 4 = 3 + (7*2) = 7gate delays s 28,s 29,s 3,s 3 available after 7+ = 8gate delays arry-outs ripple from one L block to the next. an we avoid this rippling? c 32-bit Blocked L composed of eight 4-bit L blocks Key Idea:Generate the carry outputs c 4, c 8, c 2, of L blocks in parallel, similar to how c, c 2, c 3, c 4 are generated in parallel withina L block arry-out from a 4-bit block can be given as: c 4 = G 3 + P 3 G 2 + P 3 P 2 G + P 3 P 2 P G + P 3 P 2 P P c This can be re-written as: c 4 = G + P c where G = G 3 + P 3 G 2 + P 3 P 2 G + P 3 P 2 P G and P =P 3 P 2 P P We can similarly compute G, G 2, G 3.. G i & P i are first-level generate & propagate functions, where idenotes the L block G k = implies that the kthl block generates a carry P k = implies that the kthl block propagates a carry arry-out of kthblock = G k + P k G k- + P k P k- G k P k P k-.p G + P k P k- P c For example: c 6 = G 3 + P 3 G 2 + P 3 P 2 G + P 3 P 2 P G + P 3 P 2 P P c Blocked L with First-level Propagates and Generates x 5-2 y 5-2 x -8 y -8 x 7-4 y 7-4 x 3- y 3- c 6 c 2 c 8 c 4 4-bit adder 4-bit adder 4-bit adder 4-bit adder c s 5-2 s -8 s 7-4 s 3- G I 3 P I 3 G I 2 P I 2 G I P I G I P I ultiplication arry-lookahead logic fter input operands (X, Y and c ) are applied to the above 6-bit adder: P i and G i terms withineach L calculated in parallel in gate delay First-level generates (G k ) available after + 2 = 3gate delays arry-outs of L blocks (c 4, c 8, c 2, c 6 ) available after = 5gate delays arries withinl blocks (such as c 5 ) available after = 7gate delays Sum outputs (such as s 5 ) available after 7 + = 8gate delays ompare this with the blocked L formed by cascading, where c 5 and s 5 required 9 and gate delays respectively

3 ultiplication of Unsigned Numbers ultiplication of Unsigned Numbers (contd.) In hand multiplication, we add the shifted versions of multiplicand at the end (column-by-column) lternative would be to accumulate partial products at each stage (row-by-row) Product of two n-bit numbers is at most a 2n-bit number Unsigned multiplication can be viewed as addition of shifted versions of the multiplicand. ultiplication logic for two n-bit numbers can be implement as follows : Initialize the partial product PPto a value of Start from the LSB of multiplier and proceed towards SB, one bit at a time. For each bit position of the multiplier, perform the following step: If the i th bit of the multiplier is, shift the multiplicand by ibit positions and add it to PPiin order to obtain PP(i+) fter n steps, the partial product PPn represents the final product ultiplication of Unsigned Numbers ombanitorial rray ultiplier ultiplicand Bit of incoming partial product (PPi) j th multiplicand bit i th multiplier bit Each box represents a multiplication cell PP (PP) m m m 3 m 2 p q q carry out F carry in PP3 PP2 p 2 q 2 p Bit of outgoing partial product (PP(i+)) q 3 Product = P, 7,P 6,..P p 7 p 6 p 5 p 4 p 3 Typical multiplication cell ultiplicand is shifted by displacing it through an array of adders

4 ombinatorial rray ultiplier (cont.) rray multipliers are highly inefficient: Need nn-bit adders => number of gate counts is proportional to n 2 Impractical for large numbers such as 32-bit or 64-bit numbers typically used in computers Perform only one function, namely, unsigned integer product Solution:Improve gate efficiency by using a mixture of combinatorial array techniques and sequential techniques Instead of nn-bit adders, use one n-bit adder Use a register to hold the accumulated partial product This is called a sequential multiplier Sequential ultiplication Recall the rule for generating partial products: If the i th bit of the multiplier is, add the appropriately shifted multiplicand to the current partial product. ultiplicand is shifted left when being added to the partial product Key Observation: dding a left-shiftedmultiplicand to an unshiftedpartial product is equivalent to adding an unshiftedmultiplicand to a right-shifted partial product Sequential ircuit ultiplier Sequential ultiplication lgorithm n-bit dder Register (initially ) right a a q q n - n - UX dd/noadd control ultiplier ontrol sequencer Initialization: Load multiplicand in register, multiplier in register Initialize and registers to all zeroes Repeat the following steps n times, where n is the number of bits in the multiplier If (LSB of register == ) = + (carry-out goes to register) Treat the, and registers as one contiguous register and shift that register s contents right by one bit position m n - ultiplicand m fter the completion of n steps Register contains high-order half of product Register contains low-order half of product

5 Sequential ultiplication Example Sequential ultiplication Example Sequential ultiplication Example Sequential ultiplication Example Second cycle Second cycle No add Third cycle

6 Sequential ultiplication Example Second cycle No add Third cycle Fourth cycle Product