Homework 3. Assigned on 02/15 Due time: midnight on 02/21 (1 WEEK only!) B.2 B.11 B.14 (hint: use multiplexors) CSCI 402: Computer Architectures

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "Homework 3. Assigned on 02/15 Due time: midnight on 02/21 (1 WEEK only!) B.2 B.11 B.14 (hint: use multiplexors) CSCI 402: Computer Architectures"

Transcription

1 Homework 3 Assigned on 02/15 Due time: midnight on 02/21 (1 WEEK only!) B.2 B.11 B.14 (hint: use multiplexors) 1 CSCI 402: Computer Architectures Arithmetic for Computers (2) Fengguang Song Department of Computer & Information Science IUPUI 1

2 Today s Contents Have learned +, -, x 3.3, 3.4 Optimization of multipliers Booth s Algorithm How to implement division 3 Recall: Multiplier P = 0; for i = 0 to 31 { P += A or Zero; P>>1; } Product 0 = 1 Start 1. Test Product 0 Product 0 = 0 Multiplier 1a. Add Multiplicand to left half of Product & place the result in left half. 2. Shift the Product register right 1 bit. 32nd repetition? No: < 32 repetitions Done Yes: 32 repetitions 4 2

3 Faster Hardware for i = 0 to 3 { C[i] = A[i] + B[i]; } Unroll loop We may use 32 adders C[0] = A[0] + B[0]; C[1] = A[1] + B[1]; C[2] = A[2] + B[2]; C[3] = A[3] + B[3]; Every adder outputs: 32 sum bits and a carry-out bit 1) LSB of the intermediate sum is a bit in the final product. 2) The other 31 bits and the carry-out bit are passed along to the next adder. Q: Why it is faster? 5 A 2-bits Multiplier (C = B x A) The AND gates will produce the partial products. For a 2-bit by 2-bit multiplier, we can just use two half adders to sum the partial products. In general, though, we ll need full adders. Here C 3 -C 0 are the product, not carries! B 1 B 0 x A 1 A 0 A 0 B 1 A 0 B 0 + A 1 B 1 A 1 B 0 C 3 C 2 C 1 C 0 6 3

4 A 4-bits Multiplier (C = B x A) Input 1: Previous sum Input 2: Multiplier i AND Multiplicand 7 Faster Multiplication Hardware Uses multiple adders in parallel =(log 2 32 steps) Cost/performance tradeoff n Several adders can perform in parallel e.g., a0+a1+a2+a3+a4+a5+a6+a7? 8 4

5 A 3 A 2 A 1 A 0 x B 3 B 2 B 1 B 0 B 0 (A 3 A 2 A 1 A 0 ) B 1 (A 3 A 2 A 1 A 0 ) B 2 (A 3 A 2 A 1 A 0 ) B 3 (A 3 A 2 A 1 A 0 ) B 3 (A 3 A 2 A 1 A 0 ) B 2 (A 3 A 2 A 1 A 0 ) B 1 (A 3 A 2 A 1 A 0 ) B 0 (A 3 A 2 A 1 A 0 ) P2 P1 9 Signed Multiplication? Determine sign of the operands, make them positive Use the same hardware of unsigned multiplication Fix up the sign of the output 10 5

6 Multiply MIPS Instruction 32 bits x 32 bits à up to 64 bits Hi and Lo special registers // instead of creating 64-bit register HI: stores most-significant 32 bits LO: stores least-significant 32 bits mfhi mflo Signed multiply mult (signed int), multu (unsigned int) MIPS Instructions mult rs, rt 64-bit product goes to Hi and Lo mfhi rd or mflo rd Move from HI/LO to rd Users could test if HI=0 to see if product overflows 32 bits mul rd, rs, rt (pseudoinstruction) Least-significant 32 bits of product > rd Note: mul will ignore overflow! Note: even if they are R-type operations, they only take 2 operands. 11 How to Make Multiply Even Faster? (A better algorithm) 89 x 9999 =? (calculate it by hand) = 89 ( ) = = = Similarly, apply the idea to binary numbers è Booth s algorithm! 12 6

7 Motivation for Booth s Algorithm Traditional way: x 0110: x nothing (0 in multiplier) + add (1 in multiplier) + add (1 in multiplier) nothing (0 in multiplier) ALU can get same result in more than one way: 0110 = 6 = = Replace a string of 1s with an initial subtract (when we first see a one), and then later add for the bit after the last 1. E.g., x nothing (0 in multiplier) sub (first 1 in multiplier) nothing (middle of string of 1s) + add (prior step had last 1) Booth s Algorithm middle end of run of run beginning of run Current Bit Bit to the Right Explanation Example Op 1 0 Begins run of 1s sub 1 1 Middle of run of 1s none 0 1 End of run of 1s add 0 0 Middle of run of 0s none

8 Booth s algorithm in Details 16 Booths Example 1 (2 x 7) (Assuming 4-bit) Operation Multiplicand Product Extra bit What to do next? > sub 1b. P = P m - + = shift P (sign ext) > nop, shift > nop, shift > add 4b. + = shift Final Result 4 iterations in total 14=2x7 17 8

9 quotient divisor dividend remainder 10 n-bit operands yield n-bit quotient and remainder Division Check for 0 divisor Long division approach (by hand) If divisor dividend bits 1 bit in quotient, then subtract Otherwise (i.e., > dividend bits) 0 bit in quotient, bring down next dividend bit For computers Not as smart as a human Do the subtract, and if remainder < 0, add divisor back Signed integer division? Divide using absolute values (same as x) Adjust sign of quotient and remainder as required 19 Register Setup Remainder register R (initially place dividend in R) (64 bits) Divisor register D (place divisor in left half of D) (64 bits) We place divisor in the left half so we can start subtracting from the most significant dividend bits. Quotient register Q (32 bits) D Divisor 000 R 0000 Dividend 20 9

10 Division Hardware Version 1 D Divisor 000 R 0000 Dividend Initially divisor in left half -Place divisor in left half of Divisor register D divisor -Place dividend in the right half of Remainder register R -So, we can subtract entire D from entire R -The first quotient bit = 0. Initially = dividend in right half 21 Divide Algorithm Version 1 Takes n+1 steps for n-bit Quotient & Remainder. Start: Place Dividend in Remainder 1. Subtract the Divisor register from the Remainder register, and place the result in the Remainder register. Remainder ³ 0 Test Remainder Remainder < 0 2a. Shift the Quotient register to the left, setting the new rightmost bit to 1. 2b. Restore the original value by adding the Divisor register to the Remainder register. Shift the Quotient register to the left, setting the new least significant bit to Shift the Divisor register right1 bit. n+1 repetition? No: < n+1 repetitions Yes: n+1 repetitions Done 22 10

11 7/2è quotient 3 remainder 1 Quotient Example Divisor Dividend in remainder 1 Initial values Q: 0000 D: 0000 R: D = : R = R D Q: 0000 D: 0000 R: ß R D < 0 2b: +D, sl Q, 0 Q: 0000 D: 0000 R: : Shr D Q: 0000 D: R: D = : R = R D Q: 0000 D: R: b: +D, sl Q, 0 Q: 0000 D: R: : Shr D Q: 0000 D: R: D = : R = R D Q: 0000 D: R: b: +D, sl Q, 0 Q: 0000 D: R: : Shr D Q: 0000 D: R: D = : R = R D Q: 0000 D: R: a: sl Q, 1 Q: 0001 D: R: : Shr D Q: 0001 D: 0000 R: D = : R = R D Q: 0001 D: 0000 R: a: sl Q, 1 Q: 0011 D: 0000 R: : Shr D Q: 0011 D: R: bits è 5 iterations: first iteration will always generate Q = 0 bit, because we are subtracting 0-D iteration 23 Improved on Divide Version 2 Half of the bits in the divisor are always zero 32 bits of 64-bit ALU are wasted! Instead of shifting Divisor to right, we can shift Remainder to left (they are equivalent) 1st step quotient bit is always zero, we can save 1 iteration by shift first and then subtract at the beginning. Can eliminate Quotient register by combining with Remainder Start by shifting Remainder left The consequence of combining the two registers together and the new order of the operations in the loop is that the Remainder will be shifted left one extra time. Thus, the final correction step must shift back the remainder in the left half of the register 25 11

12 Optimized Divider Divisor 32 bits 32-bit ALU HI LO Remainder (Quotient) 64 bits Shift Left Write Control One cycle per partial-remainder subtraction Looks a lot like a multiplier! Indeed, same hardware can be used for both 26 Divide Algorithm Version 2 Remainder Divisor Start: Place Dividend in Remainder 0. Shift the Remainder register left 1 bit. 1. Subtract the Divisor register from the left half of the Remainder register, & place the result in the left half of the Remainder register. Remainder ³ 0 Test Remainder Remainder < 0 2a. Shift the Remainder register to the left, setting the new rightmost bit to 1. 2b. Restore the original value by adding the Divisor register to the left half of the Remainder register. Shift the Remainder register to the left, setting the new rightmost bit to 0. nth repetition? No: < n repetitions Done. Shift left half of Remainder right 1 bit. Yes: n repetitions (n = 4 here) 27 12

13 Steps Input: Iteration 1 Divisor (D reg.) 7/2 =? Dividend (R reg.) Operation to do shl R sub D 2 = 1110 Start: Place Dividend in Remainder 0. Shift the Remainder register left 1 bit. Iteration a or 2b? 1. Subtract the Divisor register from the left half of the Remainder register, & place the result in the left half of the Remainder register. Iteration sub D Remainder 0 Test Remainder Remainder < 0 Iteration 2 Iteration a or 2b? sub D 2a. Shift the Remainder register to the left, setting the new rightmost bit to 1. 2b. Restore the original value by adding the Divisor register to the left half of the Remainder register. Shift the Remainder register to the left, setting the new rightmost bit to 0. Iteration a or 2b? nth repetition? No: < n repetitions Iteration sub D Done. Shift left half of Remainder right 1 bit. Yes: n repetitions (n = 4 here) Iteration a or 2b? Final: shift remainder to right 29 MIPS Division Also use special HI/LO registers for result HI: store 32-bit Remainder LO: store 32-bit Quotient Instructions div rs, rt or divu rs, rt No overflow checking, no divide-by-0 checking Software must perform checks if required Use mfhi, mflo to access result 31 13

14 Optimized Divider Divisor 32 bits 32-bit ALU HI LO Dividend (Remainder) (Quotient) 64 bits Shift Left Write Control 32 Optimized Multiply Hardware Multiplicand 32 bits 32-bit ALU HI LO Product (Multiplier) 64 bits Shift Right Read LSB Control 33 14

15 More About Divide Version 2 Same Hardware as Multiply: just let ALU do add or subtract, and let 64-bit register shift left or shift right Hi and Lo registers combined to act as 64-bit register for multiply and divide Signed divide: Simplest is to make both operands positive, then negate Quotient and Remainder if necessary Complexity: What are the signs of Quotient and Remainder? Note1: Quotient negated if Dividend & Divisor have different signs Note2: Dividend and Remainder must have same sign e.g., 7 2 = 3, remainder =? e.g., 7-2 = 3, remainder =? e.g., 7-2 = -3, remainder =? Because Dividend = Quotient x Divisor + Remainder 34 15

COMP 303 Computer Architecture Lecture 6

COMP 303 Computer Architecture Lecture 6 COMP 303 Computer Architecture Lecture 6 MULTIPLY (unsigned) Paper and pencil example (unsigned): Multiplicand 1000 = 8 Multiplier x 1001 = 9 1000 0000 0000 1000 Product 01001000 = 72 n bits x n bits =

More information

Tailoring the 32-Bit ALU to MIPS

Tailoring the 32-Bit ALU to MIPS Tailoring the 32-Bit ALU to MIPS MIPS ALU extensions Overflow detection: Carry into MSB XOR Carry out of MSB Branch instructions Shift instructions Slt instruction Immediate instructions ALU performance

More information

CPS 104 Computer Organization and Programming

CPS 104 Computer Organization and Programming CPS 104 Computer Organization and Programming Lecture 9: Integer Arithmetic. Robert Wagner CPS104 IMD.1 RW Fall 2000 Overview of Today s Lecture: Integer Multiplication and Division. Read Appendix B CPS104

More information

Chapter 3 Arithmetic for Computers (Part 2)

Chapter 3 Arithmetic for Computers (Part 2) Department of Electr rical Eng ineering, Chapter 3 Arithmetic for Computers (Part 2) 王振傑 (Chen-Chieh Wang) ccwang@mail.ee.ncku.edu.tw ncku edu Depar rtment of Electr rical Eng ineering, Feng-Chia Unive

More information

Outline. EEL-4713 Computer Architecture Multipliers and shifters. Deriving requirements of ALU. MIPS arithmetic instructions

Outline. EEL-4713 Computer Architecture Multipliers and shifters. Deriving requirements of ALU. MIPS arithmetic instructions Outline EEL-4713 Computer Architecture Multipliers and shifters Multiplication and shift registers Chapter 3, section 3.4 Next lecture Division, floating-point 3.5 3.6 EEL-4713 Ann Gordon-Ross.1 EEL-4713

More information

Number Systems and Computer Arithmetic

Number Systems and Computer Arithmetic Number Systems and Computer Arithmetic Counting to four billion two fingers at a time What do all those bits mean now? bits (011011011100010...01) instruction R-format I-format... integer data number text

More information

Arithmetic for Computers. Hwansoo Han

Arithmetic for Computers. Hwansoo Han Arithmetic for Computers Hwansoo Han Arithmetic for Computers Operations on integers Addition and subtraction Multiplication and division Dealing with overflow Floating-point real numbers Representation

More information

Fast Arithmetic. Philipp Koehn. 19 October 2016

Fast Arithmetic. Philipp Koehn. 19 October 2016 Fast Arithmetic Philipp Koehn 19 October 2016 1 arithmetic Addition (Immediate) 2 Load immediately one number (s0 = 2) li $s0, 2 Add 4 ($s1 = $s0 + 4 = 6) addi $s1, $s0, 4 Subtract 3 ($s2 = $s1-3 = 3)

More information

9 Multiplication and Division

9 Multiplication and Division 9 Multiplication and Division Multiplication is done by doing shifts and additions. Multiplying two (unsigned) numbers of n bits each results in a product of 2n bits. Example: 0110 x 0011 (6x3) At start,

More information

Review from last time. CS152 Computer Architecture and Engineering Lecture 6. Verilog (finish) Multiply, Divide, Shift

Review from last time. CS152 Computer Architecture and Engineering Lecture 6. Verilog (finish) Multiply, Divide, Shift Review from last time CS152 Computer Architecture and Engineering Lecture 6 Verilog (finish) Multiply, Divide, Shift February 11, 2004 John Kubiatowicz (www.cs.berkeley.edu/~kubitron) lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/

More information

Module 2: Computer Arithmetic

Module 2: Computer Arithmetic Module 2: Computer Arithmetic 1 B O O K : C O M P U T E R O R G A N I Z A T I O N A N D D E S I G N, 3 E D, D A V I D L. P A T T E R S O N A N D J O H N L. H A N N E S S Y, M O R G A N K A U F M A N N

More information

CS/COE 0447 Example Problems for Exam 2 Spring 2011

CS/COE 0447 Example Problems for Exam 2 Spring 2011 CS/COE 0447 Example Problems for Exam 2 Spring 2011 1) Show the steps to multiply the 4-bit numbers 3 and 5 with the fast shift-add multipler. Use the table below. List the multiplicand (M) and product

More information

Chapter 3 Arithmetic for Computers

Chapter 3 Arithmetic for Computers Chapter 3 Arithmetic for Computers 1 Arithmetic Where we've been: Abstractions: Instruction Set Architecture Assembly Language and Machine Language What's up ahead: Implementing the Architecture operation

More information

CS 61C: Great Ideas in Computer Architecture MIPS Instruction Formats

CS 61C: Great Ideas in Computer Architecture MIPS Instruction Formats CS 61C: Great Ideas in Computer Architecture MIPS Instruction Formats Instructors: Vladimir Stojanovic and Nicholas Weaver http://inst.eecs.berkeley.edu/~cs61c/sp16 1 Machine Interpretation Levels of Representation/Interpretation

More information

Computer Architecture. Chapter 3: Arithmetic for Computers

Computer Architecture. Chapter 3: Arithmetic for Computers 182.092 Computer Architecture Chapter 3: Arithmetic for Computers Adapted from Computer Organization and Design, 4 th Edition, Patterson & Hennessy, 2008, Morgan Kaufmann Publishers and Mary Jane Irwin

More information

Arithmetic Logic Unit

Arithmetic Logic Unit Arithmetic Logic Unit A.R. Hurson Department of Computer Science Missouri University of Science & Technology A.R. Hurson 1 Arithmetic Logic Unit It is a functional bo designed to perform "basic" arithmetic,

More information

Chapter 10 - Computer Arithmetic

Chapter 10 - Computer Arithmetic Chapter 10 - Computer Arithmetic Luis Tarrataca luis.tarrataca@gmail.com CEFET-RJ L. Tarrataca Chapter 10 - Computer Arithmetic 1 / 126 1 Motivation 2 Arithmetic and Logic Unit 3 Integer representation

More information

HW2 solutions You did this for Lab sbn temp, temp,.+1 # temp = 0; sbn temp, b,.+1 # temp = -b; sbn a, temp,.+1 # a = a (-b) = a + b;

HW2 solutions You did this for Lab sbn temp, temp,.+1 # temp = 0; sbn temp, b,.+1 # temp = -b; sbn a, temp,.+1 # a = a (-b) = a + b; HW2 solutions 3.10 Pseuodinstructions What is accomplished Minimum sequence of Mips Move $t5, $t3 $t5=$t3 Add $t5, $t3, $0 Clear $t5 $t5=0 Xor $t5, $t5, $t5 Li $t5, small $t5=small Addi $t5, $0, small

More information

CO Computer Architecture and Programming Languages CAPL. Lecture 13 & 14

CO Computer Architecture and Programming Languages CAPL. Lecture 13 & 14 CO20-320241 Computer Architecture and Programming Languages CAPL Lecture 13 & 14 Dr. Kinga Lipskoch Fall 2017 Frame Pointer (1) The stack is also used to store variables that are local to function, but

More information

Chapter 5: Computer Arithmetic

Chapter 5: Computer Arithmetic Slide 1/29 Learning Objectives Computer Fundamentals: Pradeep K. Sinha & Priti Sinha In this chapter you will learn about: Reasons for using binary instead of decimal numbers Basic arithmetic operations

More information

Arithmetic. Chapter 3 Computer Organization and Design

Arithmetic. Chapter 3 Computer Organization and Design Arithmetic Chapter 3 Computer Organization and Design Addition Addition is similar to decimals 0000 0111 + 0000 0101 = 0000 1100 Subtraction (negate) 0000 0111 + 1111 1011 = 0000 0010 Over(under)flow For

More information

Computer Arithmetic Ch 8

Computer Arithmetic Ch 8 Computer Arithmetic Ch 8 ALU Integer Representation Integer Arithmetic Floating-Point Representation Floating-Point Arithmetic 1 Arithmetic Logical Unit (ALU) (2) (aritmeettis-looginen yksikkö) Does all

More information

Computer Arithmetic Ch 8

Computer Arithmetic Ch 8 Computer Arithmetic Ch 8 ALU Integer Representation Integer Arithmetic Floating-Point Representation Floating-Point Arithmetic 1 Arithmetic Logical Unit (ALU) (2) Does all work in CPU (aritmeettis-looginen

More information

ECE232: Hardware Organization and Design. Computer Organization - Previously covered

ECE232: Hardware Organization and Design. Computer Organization - Previously covered ECE232: Hardware Organization and Design Part 6: MIPS Instructions II http://www.ecs.umass.edu/ece/ece232/ Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Computer Organization

More information

The ALU consists of combinational logic. Processes all data in the CPU. ALL von Neuman machines have an ALU loop.

The ALU consists of combinational logic. Processes all data in the CPU. ALL von Neuman machines have an ALU loop. CS 320 Ch 10 Computer Arithmetic The ALU consists of combinational logic. Processes all data in the CPU. ALL von Neuman machines have an ALU loop. Signed integers are typically represented in sign-magnitude

More information

CSCI 402: Computer Architectures. Arithmetic for Computers (4) Fengguang Song Department of Computer & Information Science IUPUI.

CSCI 402: Computer Architectures. Arithmetic for Computers (4) Fengguang Song Department of Computer & Information Science IUPUI. CSCI 402: Computer Architectures Arithmetic for Computers (4) Fengguang Song Department of Computer & Information Science IUPUI Homework 4 Assigned on Feb 22, Thursday Due Time: 11:59pm, March 5 on Monday

More information

Adding Binary Integers. Part 4. Negative Binary. Integers. Adding Base 10 Numbers. Adding Binary Example = 10. Arithmetic Logic Unit

Adding Binary Integers. Part 4. Negative Binary. Integers. Adding Base 10 Numbers. Adding Binary Example = 10. Arithmetic Logic Unit Part 4 Adding Binary Integers Arithmetic Logic Unit = Adding Binary Integers Adding Base Numbers Computer's add binary numbers the same way that we do with decimal Columns are aligned, added, and "'s"

More information

Floating-Point Data Representation and Manipulation 198:231 Introduction to Computer Organization Lecture 3

Floating-Point Data Representation and Manipulation 198:231 Introduction to Computer Organization Lecture 3 Floating-Point Data Representation and Manipulation 198:231 Introduction to Computer Organization Instructor: Nicole Hynes nicole.hynes@rutgers.edu 1 Fixed Point Numbers Fixed point number: integer part

More information

Instruction Set Architecture of. MIPS Processor. MIPS Processor. MIPS Registers (continued) MIPS Registers

Instruction Set Architecture of. MIPS Processor. MIPS Processor. MIPS Registers (continued) MIPS Registers CSE 675.02: Introduction to Computer Architecture MIPS Processor Memory Instruction Set Architecture of MIPS Processor CPU Arithmetic Logic unit Registers $0 $31 Multiply divide Coprocessor 1 (FPU) Registers

More information

Introduction to Digital Logic Missouri S&T University CPE 2210 Multipliers/Dividers

Introduction to Digital Logic Missouri S&T University CPE 2210 Multipliers/Dividers Introduction to Digital Logic Missouri S&T University CPE 2210 Multipliers/Dividers Egemen K. Çetinkaya Egemen K. Çetinkaya Department of Electrical & Computer Engineering Missouri University of Science

More information

MIPS Instruction Format

MIPS Instruction Format MIPS Instruction Format MIPS uses a 32-bit fixed-length instruction format. only three different instruction word formats: There are Register format Op-code Rs Rt Rd Function code 000000 sssss ttttt ddddd

More information

Assembly Programming

Assembly Programming Designing Computer Systems Assembly Programming 08:34:48 PM 23 August 2016 AP-1 Scott & Linda Wills Designing Computer Systems Assembly Programming In the early days of computers, assembly programming

More information

Least Common Multiple (LCM)

Least Common Multiple (LCM) Least Common Multiple (LCM) Task: Implement an LCM algorithm that is able to handle any combination of 8-bit (sign bit included) numbers. Use two's complement format to represent negative values. Provide

More information

Τί είναι η αριθµητική Η/Υ?

Τί είναι η αριθµητική Η/Υ? ΗΜΥ 312 -- ΑΡΧΙΤΕΚΤΟΝΙΚΗ ΗΛΕΚΤΡΟΝΙΚΩΝ ΥΠΟΛΟΓΙΣΤΩΝ ΔΙΑΛΕΞΕΙΣ 14-15: Αριθμητική Η/Υ Διδάσκουσα: ΜΑΡΙΑ Κ. ΜΙΧΑΗΛ Αναπληρώτρια Καθηγήτρια, ΗΜΜΥ (mmichael@ucy.ac.cy) [Προσαρµογή από Computer Architecture, Computer

More information

Mark Redekopp, All rights reserved. EE 352 Unit 3 MIPS ISA

Mark Redekopp, All rights reserved. EE 352 Unit 3 MIPS ISA EE 352 Unit 3 MIPS ISA Instruction Set Architecture (ISA) Defines the software interface of the processor and memory system Instruction set is the vocabulary the HW can understand and the SW is composed

More information

EE 109 Unit 8 MIPS Instruction Set

EE 109 Unit 8 MIPS Instruction Set 1 EE 109 Unit 8 MIPS Instruction Set 2 Architecting a vocabulary for the HW INSTRUCTION SET OVERVIEW 3 Instruction Set Architecture (ISA) Defines the software interface of the processor and memory system

More information

Data Representation Type of Data Representation Integers Bits Unsigned 2 s Comp Excess 7 Excess 8

Data Representation Type of Data Representation Integers Bits Unsigned 2 s Comp Excess 7 Excess 8 Data Representation At its most basic level, all digital information must reduce to 0s and 1s, which can be discussed as binary, octal, or hex data. There s no practical limit on how it can be interpreted

More information

CPS311 - COMPUTER ORGANIZATION. A bit of history

CPS311 - COMPUTER ORGANIZATION. A bit of history CPS311 - COMPUTER ORGANIZATION A Brief Introduction to the MIPS Architecture A bit of history The MIPS architecture grows out of an early 1980's research project at Stanford University. In 1984, MIPS computer

More information

Chapter 4 Section 2 Operations on Decimals

Chapter 4 Section 2 Operations on Decimals Chapter 4 Section 2 Operations on Decimals Addition and subtraction of decimals To add decimals, write the numbers so that the decimal points are on a vertical line. Add as you would with whole numbers.

More information

Step 1: Add the least significant digits together: produces with carry 1.

Step 1: Add the least significant digits together: produces with carry 1. Advanced Arithmetic Advanced Arithmetic Chapter Four 41 Chapter Overview This chapter deals with those arithmetic operations for which assembly language is especially well suited and high level languages

More information

UNIT - I: COMPUTER ARITHMETIC, REGISTER TRANSFER LANGUAGE & MICROOPERATIONS

UNIT - I: COMPUTER ARITHMETIC, REGISTER TRANSFER LANGUAGE & MICROOPERATIONS UNIT - I: COMPUTER ARITHMETIC, REGISTER TRANSFER LANGUAGE & MICROOPERATIONS (09 periods) Computer Arithmetic: Data Representation, Fixed Point Representation, Floating Point Representation, Addition and

More information

Binary Adders. Ripple-Carry Adder

Binary Adders. Ripple-Carry Adder Ripple-Carry Adder Binary Adders x n y n x y x y c n FA c n - c 2 FA c FA c s n MSB position Longest delay (Critical-path delay): d c(n) = n d carry = 2n gate delays d s(n-) = (n-) d carry +d sum = 2n

More information

Lecture 14: Recap. Today s topics: Recap for mid-term No electronic devices in midterm

Lecture 14: Recap. Today s topics: Recap for mid-term No electronic devices in midterm Lecture 14: Recap Today s topics: Recap for mid-term No electronic devices in midterm 1 Modern Trends Historical contributions to performance: Better processes (faster devices) ~20% Better circuits/pipelines

More information

Lecture 5. Computer Arithmetic. Ch 9 [Stal10] Integer arithmetic Floating-point arithmetic

Lecture 5. Computer Arithmetic. Ch 9 [Stal10] Integer arithmetic Floating-point arithmetic Lecture 5 Computer Arithmetic Ch 9 [Stal10] Integer arithmetic Floating-point arithmetic ALU ALU = Arithmetic Logic Unit (aritmeettis-looginen yksikkö) Actually performs operations on data Integer and

More information

Lecture 9. INC and DEC. INC/DEC Examples ADD. Arithmetic Operations Overflow Multiply and Divide

Lecture 9. INC and DEC. INC/DEC Examples ADD. Arithmetic Operations Overflow Multiply and Divide Lecture 9 INC and DEC Arithmetic Operations Overflow Multiply and Divide INC adds one to a single operand DEC decrements one from a single operand INC destination DEC destination where destination can

More information

Number Systems and Conversions UNIT 1 NUMBER SYSTEMS & CONVERSIONS. Number Systems (2/2) Number Systems (1/2) Iris Hui-Ru Jiang Spring 2010

Number Systems and Conversions UNIT 1 NUMBER SYSTEMS & CONVERSIONS. Number Systems (2/2) Number Systems (1/2) Iris Hui-Ru Jiang Spring 2010 Contents Number systems and conversion Binary arithmetic Representation of negative numbers Addition of two s complement numbers Addition of one s complement numbers Binary s Readings Unit.~. UNIT NUMBER

More information

Two-Level CLA for 4-bit Adder. Two-Level CLA for 4-bit Adder. Two-Level CLA for 16-bit Adder. A Closer Look at CLA Delay

Two-Level CLA for 4-bit Adder. Two-Level CLA for 4-bit Adder. Two-Level CLA for 16-bit Adder. A Closer Look at CLA Delay Two-Level CLA for 4-bit Adder Individual carry equations C 1 = g 0 +p 0, C 2 = g 1 +p 1 C 1,C 3 = g 2 +p 2 C 2, = g 3 +p 3 C 3 Fully expanded (infinite hardware) CLA equations C 1 = g 0 +p 0 C 2 = g 1

More information

CS61C : Machine Structures

CS61C : Machine Structures inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 13 Introduction to MIPS Instruction Representation I Lecturer PSOE Dan Garcia www.cs.berkeley.edu/~ddgarcia Anyone seen Terminator? Military

More information

Computer Architecture and Organization

Computer Architecture and Organization 3-1 Chapter 3 - Arithmetic Computer Architecture and Organization Miles Murdocca and Vincent Heuring Chapter 3 Arithmetic 3-2 Chapter 3 - Arithmetic Chapter Contents 3.1 Fixed Point Addition and Subtraction

More information

Experiment Objectives. 2. Preparation. 3. Tasks. 3.1 Task A: String to Integer Conversion

Experiment Objectives. 2. Preparation. 3. Tasks. 3.1 Task A: String to Integer Conversion Experiment 3 1. Objectives In this experiment, you will learn more AVR instructions by writing AVR assembly programs to do string-to-number conversion, positional multiplication, positional division, and

More information

EE 109 Unit 6 Binary Arithmetic

EE 109 Unit 6 Binary Arithmetic EE 109 Unit 6 Binary Arithmetic 1 2 Semester Transition Point At this point we are going to start to transition in our class to look more at the hardware organization and the low-level software that is

More information

BINARY SYSTEM. Binary system is used in digital systems because it is:

BINARY SYSTEM. Binary system is used in digital systems because it is: CHAPTER 2 CHAPTER CONTENTS 2.1 Binary System 2.2 Binary Arithmetic Operation 2.3 Signed & Unsigned Numbers 2.4 Arithmetic Operations of Signed Numbers 2.5 Hexadecimal Number System 2.6 Octal Number System

More information

SPIM Instruction Set

SPIM Instruction Set SPIM Instruction Set This document gives an overview of the more common instructions used in the SPIM simulator. Overview The SPIM simulator implements the full MIPS instruction set, as well as a large

More information

Basic Arithmetic (adding and subtracting)

Basic Arithmetic (adding and subtracting) Basic Arithmetic (adding and subtracting) Digital logic to show add/subtract Boolean algebra abstraction of physical, analog circuit behavior 1 0 CPU components ALU logic circuits logic gates transistors

More information

Week 10: Assembly Programming

Week 10: Assembly Programming Week 10: Assembly Programming Arithmetic instructions Instruction Opcode/Function Syntax Operation add 100000 $d, $s, $t $d = $s + $t addu 100001 $d, $s, $t $d = $s + $t addi 001000 $t, $s, i $t = $s +

More information

Chapter 2 Data Representations

Chapter 2 Data Representations Computer Engineering Chapter 2 Data Representations Hiroaki Kobayashi 4/21/2008 4/21/2008 1 Agenda in Chapter 2 Translation between binary numbers and decimal numbers Data Representations for Integers

More information

CO Computer Architecture and Programming Languages CAPL. Lecture 15

CO Computer Architecture and Programming Languages CAPL. Lecture 15 CO20-320241 Computer Architecture and Programming Languages CAPL Lecture 15 Dr. Kinga Lipskoch Fall 2017 How to Compute a Binary Float Decimal fraction: 8.703125 Integral part: 8 1000 Fraction part: 0.703125

More information

Lecture 6: Signed Numbers & Arithmetic Circuits. BCD (Binary Coded Decimal) Points Addressed in this Lecture

Lecture 6: Signed Numbers & Arithmetic Circuits. BCD (Binary Coded Decimal) Points Addressed in this Lecture Points ddressed in this Lecture Lecture 6: Signed Numbers rithmetic Circuits Professor Peter Cheung Department of EEE, Imperial College London (Floyd 2.5-2.7, 6.1-6.7) (Tocci 6.1-6.11, 9.1-9.2, 9.4) Representing

More information

Arithmetic Operations

Arithmetic Operations Arithmetic Operations Arithmetic Operations addition subtraction multiplication division Each of these operations on the integer representations: unsigned two's complement 1 Addition One bit of binary

More information

Chapter 3: part 3 Binary Subtraction

Chapter 3: part 3 Binary Subtraction Chapter 3: part 3 Binary Subtraction Iterative combinational circuits Binary adders Half and full adders Ripple carry and carry lookahead adders Binary subtraction Binary adder-subtractors Signed binary

More information

68000 Instruction Set (2) 9/20/6 Lecture 3 - Instruction Set - Al 1

68000 Instruction Set (2) 9/20/6 Lecture 3 - Instruction Set - Al 1 68000 Instruction Set (2) 9/20/6 Lecture 3 - Instruction Set - Al 1 Lecture Overview The 68000 Instruction Set continued The understand and effectively use an architecture must understand the register

More information

Chapter 7 Integer Arithmetic

Chapter 7 Integer Arithmetic Chapter 7 Integer Arithmetic 7.1 Introduction 193 7.2 Shift and Rotate Instructions 194 7.2.1 Logical Shifts and Arithmetic Shifts 194 7.2.2 SHL Instruction 195 7.2.3 SHR Instruction 196 7.2.4 SAL and

More information

AT Arithmetic. Integer addition

AT Arithmetic. Integer addition AT Arithmetic Most concern has gone into creating fast implementation of (especially) FP Arith. Under the AT (area-time) rule, area is (almost) as important. So it s important to know the latency, bandwidth

More information

MIPS Instruction Reference

MIPS Instruction Reference Page 1 of 9 MIPS Instruction Reference This is a description of the MIPS instruction set, their meanings, syntax, semantics, and bit encodings. The syntax given for each instruction refers to the assembly

More information

Addition and multiplication

Addition and multiplication Addition and multiplication Arithmetic is the most basic thing you can do with a computer, but it s not as easy as you might expect! These next few lectures focus on addition, subtraction, multiplication

More information

Math 230 Assembly Programming (AKA Computer Organization) Spring 2008

Math 230 Assembly Programming (AKA Computer Organization) Spring 2008 Math 230 Assembly Programming (AKA Computer Organization) Spring 2008 MIPS Intro II Lect 10 Feb 15, 2008 Adapted from slides developed for: Mary J. Irwin PSU CSE331 Dave Patterson s UCB CS152 M230 L10.1

More information

COMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 3. Arithmetic for Computers

COMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 3. Arithmetic for Computers COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 3 Arithmetic for Computers Arithmetic for Computers Operations on integers Addition and subtraction Multiplication

More information

Lesson 1: THE DECIMAL SYSTEM

Lesson 1: THE DECIMAL SYSTEM Lesson 1: THE DECIMAL SYSTEM The word DECIMAL comes from a Latin word, which means "ten. The Decimal system uses the following ten digits to write a number: 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9. Each time

More information

1010 2?= ?= CS 64 Lecture 2 Data Representation. Decimal Numbers: Base 10. Reading: FLD Digits: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9

1010 2?= ?= CS 64 Lecture 2 Data Representation. Decimal Numbers: Base 10. Reading: FLD Digits: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 CS 64 Lecture 2 Data Representation Reading: FLD 1.2-1.4 Decimal Numbers: Base 10 Digits: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 Example: 3271 = (3x10 3 ) + (2x10 2 ) + (7x10 1 ) + (1x10 0 ) 1010 10?= 1010 2?= 1

More information

Xuan Guo. Lecture XIV: Review of Chapter 3 & 4. CSC 3210 Computer Organization and Programming Georgia State University. March 5, 2015.

Xuan Guo. Lecture XIV: Review of Chapter 3 & 4. CSC 3210 Computer Organization and Programming Georgia State University. March 5, 2015. CSC 3210 Computer Organization and Programming Georgia State University March 5, 2015 This lecture Plan for the lecture: Binary Hardware Device Converting from Decimal to other number system Converting

More information

1. Divide by using long division. (8x 3 + 6x 2 + 7) (x + 2)

1. Divide by using long division. (8x 3 + 6x 2 + 7) (x + 2) Bellwork 0-7-4. Divide by using long division. (8x + 6x 2 + 7) (x + 2) Synthetic division is a shorthand method of dividing a polynomial by a linear binomial by using only the coefficients. For synthetic

More information

Integer Subtraction. Chapter 3. Overflow conditions. Arithmetic for Computers. Signed Addition. Integer Addition. Arithmetic for Computers

Integer Subtraction. Chapter 3. Overflow conditions. Arithmetic for Computers. Signed Addition. Integer Addition. Arithmetic for Computers COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Integer Subtraction Chapter 3 Arithmetic for Computers Add negation of second operand Example: 7 6 = 7 + ( 6) +7: 0000 0000

More information

CS 31: Intro to Systems Digital Logic. Kevin Webb Swarthmore College February 3, 2015

CS 31: Intro to Systems Digital Logic. Kevin Webb Swarthmore College February 3, 2015 CS 31: Intro to Systems Digital Logic Kevin Webb Swarthmore College February 3, 2015 Reading Quiz Today Hardware basics Machine memory models Digital signals Logic gates Circuits: Borrow some paper if

More information

UNIT IV: DATA PATH DESIGN

UNIT IV: DATA PATH DESIGN UNIT IV: DATA PATH DESIGN Agenda Introduc/on Fixed Point Arithme/c Addi/on Subtrac/on Mul/plica/on & Serial mul/plier Division & Serial Divider Two s Complement (Addi/on, Subtrac/on) Booth s algorithm

More information

Register Transfer Language and Microoperations (Part 2)

Register Transfer Language and Microoperations (Part 2) Register Transfer Language and Microoperations (Part 2) Adapted by Dr. Adel Ammar Computer Organization 1 MICROOPERATIONS Computer system microoperations are of four types: Register transfer microoperations

More information

Lecture 2: Number Systems

Lecture 2: Number Systems Lecture 2: Number Systems Syed M. Mahmud, Ph.D ECE Department Wayne State University Original Source: Prof. Russell Tessier of University of Massachusetts Aby George of Wayne State University Contents

More information

CS 31: Intro to Systems Digital Logic. Kevin Webb Swarthmore College February 2, 2016

CS 31: Intro to Systems Digital Logic. Kevin Webb Swarthmore College February 2, 2016 CS 31: Intro to Systems Digital Logic Kevin Webb Swarthmore College February 2, 2016 Reading Quiz Today Hardware basics Machine memory models Digital signals Logic gates Circuits: Borrow some paper if

More information

Data Representations & Arithmetic Operations

Data Representations & Arithmetic Operations Data Representations & Arithmetic Operations Hiroaki Kobayashi 7/13/2011 7/13/2011 Computer Science 1 Agenda Translation between binary numbers and decimal numbers Data Representations for Integers Negative

More information

1. NUMBER SYSTEMS USED IN COMPUTING: THE BINARY NUMBER SYSTEM

1. NUMBER SYSTEMS USED IN COMPUTING: THE BINARY NUMBER SYSTEM 1. NUMBER SYSTEMS USED IN COMPUTING: THE BINARY NUMBER SYSTEM 1.1 Introduction Given that digital logic and memory devices are based on two electrical states (on and off), it is natural to use a number

More information

P( Hit 2nd ) = P( Hit 2nd Miss 1st )P( Miss 1st ) = (1/15)(15/16) = 1/16. P( Hit 3rd ) = (1/14) * P( Miss 2nd and 1st ) = (1/14)(14/15)(15/16) = 1/16

P( Hit 2nd ) = P( Hit 2nd Miss 1st )P( Miss 1st ) = (1/15)(15/16) = 1/16. P( Hit 3rd ) = (1/14) * P( Miss 2nd and 1st ) = (1/14)(14/15)(15/16) = 1/16 CODING and INFORMATION We need encodings for data. How many questions must be asked to be certain where the ball is. (cases: avg, worst, best) P( Hit 1st ) = 1/16 P( Hit 2nd ) = P( Hit 2nd Miss 1st )P(

More information

Binary Adders: Half Adders and Full Adders

Binary Adders: Half Adders and Full Adders Binary Adders: Half Adders and Full Adders In this set of slides, we present the two basic types of adders: 1. Half adders, and 2. Full adders. Each type of adder functions to add two binary bits. In order

More information

4/8/17. Admin. Assignment 5 BINARY. David Kauchak CS 52 Spring 2017

4/8/17. Admin. Assignment 5 BINARY. David Kauchak CS 52 Spring 2017 4/8/17 Admin! Assignment 5 BINARY David Kauchak CS 52 Spring 2017 Diving into your computer Normal computer user 1 After intro CS After 5 weeks of cs52 What now One last note on CS52 memory address binary

More information

ECE 2035 Programming HW/SW Systems Fall problems, 7 pages Exam Two 23 October 2013

ECE 2035 Programming HW/SW Systems Fall problems, 7 pages Exam Two 23 October 2013 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

Divisibility Rules and Their Explanations

Divisibility Rules and Their Explanations Divisibility Rules and Their Explanations Increase Your Number Sense These divisibility rules apply to determining the divisibility of a positive integer (1, 2, 3, ) by another positive integer or 0 (although

More information

Principles of Computer Architecture. Chapter 3: Arithmetic

Principles of Computer Architecture. Chapter 3: Arithmetic 3-1 Chapter 3 - Arithmetic Principles of Computer Architecture Miles Murdocca and Vincent Heuring Chapter 3: Arithmetic 3-2 Chapter 3 - Arithmetic 3.1 Overview Chapter Contents 3.2 Fixed Point Addition

More information

Chapter 2 Bits, Data Types, and Operations

Chapter 2 Bits, Data Types, and Operations Chapter 2 Bits, Data Types, and Operations How do we represent data in a computer? At the lowest level, a computer is an electronic machine. works by controlling the flow of electrons Easy to recognize

More information

Mnem. Meaning Format Operation Flags affected ADD Addition ADD D,S (D) (S)+(D) (CF) Carry ADC Add with ADC D,C (D) (S)+(D)+(CF) O,S,Z,A,P,C

Mnem. Meaning Format Operation Flags affected ADD Addition ADD D,S (D) (S)+(D) (CF) Carry ADC Add with ADC D,C (D) (S)+(D)+(CF) O,S,Z,A,P,C ARITHMETIC AND LOGICAL GROUPS 6-1 Arithmetic and logical groups: The arithmetic group includes instructions for the addition, subtraction, multiplication, and division operations. The state that results

More information

EC2303-COMPUTER ARCHITECTURE AND ORGANIZATION

EC2303-COMPUTER ARCHITECTURE AND ORGANIZATION EC2303-COMPUTER ARCHITECTURE AND ORGANIZATION QUESTION BANK UNIT-II 1. What are the disadvantages in using a ripple carry adder? (NOV/DEC 2006) The main disadvantage using ripple carry adder is time delay.

More information

COMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 3. Arithmetic for Computers

COMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 3. Arithmetic for Computers COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 3 Arithmetic for Computers Arithmetic for Computers Operations on integers Addition and subtraction Multiplication

More information

CS61C : Machine Structures

CS61C : Machine Structures inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures $2M 3D camera Lecture 8 MIPS Instruction Representation I Instructor: Miki Lustig 2014-09-17 August 25: The final ISA showdown: Is ARM, x86, or

More information

ECE 341. Lecture # 6

ECE 341. Lecture # 6 ECE 34 Lecture # 6 Instructor: Zeshan Chishti zeshan@pdx.edu October 5, 24 Portland State University Lecture Topics Design of Fast Adders Carry Looakahead Adders (CLA) Blocked Carry-Lookahead Adders Multiplication

More information

IMPLEMENTATION OF TWIN PRECISION TECHNIQUE FOR MULTIPLICATION

IMPLEMENTATION OF TWIN PRECISION TECHNIQUE FOR MULTIPLICATION IMPLEMENTATION OF TWIN PRECISION TECHNIQUE FOR MULTIPLICATION SUNITH KUMAR BANDI #1, M.VINODH KUMAR *2 # ECE department, M.V.G.R College of Engineering, Vizianagaram, Andhra Pradesh, INDIA. 1 sunithjc@gmail.com

More information

MIPS Reference Guide

MIPS Reference Guide MIPS Reference Guide Free at PushingButtons.net 2 Table of Contents I. Data Registers 3 II. Instruction Register Formats 4 III. MIPS Instruction Set 5 IV. MIPS Instruction Set (Extended) 6 V. SPIM Programming

More information

Instructions moving data

Instructions moving data do not affect flags. Instructions moving data mov register/mem, register/mem/number (move data) The difference between the value and the address of a variable mov al,sum; value 56h al mov ebx,offset Sum;

More information

Multiplies the word length <ea> times the least significant word in Dn. The result is a long word.

Multiplies the word length <ea> times the least significant word in Dn. The result is a long word. MATHEMATICAL INSTRUCTIONS Multiply unsigned MULU ,dn Action Notes: Example: Multiplies the word length times the least significant word in Dn. The result is a long word. 1. The lowest word of

More information

Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture

Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture Computer Science 324 Computer Architecture Mount Holyoke College Fall 2009 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture. Idea:

More information

Arithmetic Instructions

Arithmetic Instructions Segment 3C Arithmetic Instructions This topic covers the following instructions: Addition (ADD, INC, ADC) Subtraction (SUB, DEC, SBB,CMP) Multiplication (MUL, IMUL) Division (DIV, IDIV) BCD Arithmetic

More information

Arithmetic and Logical Operations

Arithmetic and Logical Operations Arithmetic and Logical Operations 2 CMPE2c x +y + sum Or in tabular form Binary Addition Carry Out Sum B A Carry In Binary Addition And as a full adder a b co ci sum 4-bit Ripple-Carry adder: Carry values

More information

Processor (I) - datapath & control. Hwansoo Han

Processor (I) - datapath & control. Hwansoo Han Processor (I) - datapath & control Hwansoo Han Introduction CPU performance factors Instruction count - Determined by ISA and compiler CPI and Cycle time - Determined by CPU hardware We will examine two

More information

COMP 122/L Lecture 2. Kyle Dewey

COMP 122/L Lecture 2. Kyle Dewey COMP 122/L Lecture 2 Kyle Dewey Outline Operations on binary values AND, OR, XOR, NOT Bit shifting (left, two forms of right) Addition Subtraction Twos complement Bitwise Operations Bitwise AND Similar

More information