OUTSTANDING PROPERTIES OF THE ESPROS CMOS/CCD TECHNOLOGY AND CONSEQUENCES FOR IMAGE SENSORS

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1 OUTSTANDING PROPERTIES OF THE ESPROS CMOS/CCD TECHNOLOGY AND CONSEQUENCES FOR IMAGE SENSORS OECD CONFERENCE CENTER, PARIS, FRANCE / 8 10 FEBRUARY 2012 Martin Popp, Enrico Marchesi, Beat De Coi, Markus Ledergerber ESPROS Photonics AG, St. Gallerstrasse 135, 7320 Sargans, Switzerland martin.popp@espros.ch KEYWORDS: 3D imaging, IR imaging, low light level imaging, space imagers, system integration ABSTRACT: Over the past 20 years, semiconductor image sensing has become a commodity, in particular due to the possibility of employing commercially available CMOS and CIS processes for the realization of image sensors with good performance. However, if highest optoelectronic performance must be achieved, specialized semiconductor processes are required, which are usually captive. ESPROS Photonics AG (epc) has developed a specialized CMOS process technology, focussing on the specific needs of industrial and scientific imagers markets. The exclusive ESPROS Photonic CMOS process technology offers imager performances with quantum efficiencies exceeding 95% in the NIR range. Innovative combinations of photonic, analog and digital circuitry, with novel devices combining APS/CCD structures and a backside illuminated sensor concept enable most compact system-on-chip designs with significant cost advantages compared to discrete systems. 3D time of flight (TOF), high dynamic range and ultra-highspeed CMOS imagers are only a few applications that will greatly profit from epc's technology offer to today's imager markets. 1. DEVELOPMENT OF A DEDICATED CMOS IMAGER PROCESS Today's CMOS semiconductor technologies have been optimized to maximize production yield and minimize cost per die. However, the key factors for these achievements directly conflict with the possibility to integrate photo sensors with good performance in the near infrared range (NIR) on the same chip. Base silicon wafer materials with high background doping levels and high oxygen concentrations inherently pose limits on the design of photosensitive devices with good performance. This is especially true for the NIR range of the optical spectrum (λ= nm) Large cost savings can be achieved with system integration on packaging or even chip scale levels. Traditionally, imaging systems were designed as discrete circuits resulting in expensive and bulky systems designs. Package-scale photonic chips may help to bring packaging cost down. But the full cost advantage can only be realized if a process technology allows for integration of various subsystems on one chip. In order to combine for example an LED driver with several hundred milliamp driving capacity with a pixel readout and signal processing unit on the same silicon die, a tailored process with superb domain isolation is needed. All of the criteria mentioned above have been addressed and solved by epc's ESPROS Photonic CMOS process Quantum Efficiency Quantum efficiency of a photodetector is typically determined by four factors: absorption properties of the base material, e.g. silicon thickness of the insensitive layer with short recombination times - this limits the short wavelength (Blue/UV) response thickness of the depleted region (plus additional diffusion region below) which defines the cutoff at long wavelength (NIR range) reflection properties of the surface (entrance window) Standard photodetectors are limited in optimizing these parameters by boundary conditions given by the CMOS / CCD process. For example is the insensitive layer given by a Source/Drain or shallow well implant, or the depleted region is limited by commercially reasonable epi thickness and the reflection properties are defined by the BEOL stack which causes dominant variations on QE over λ due to interference. The ESPROS Photonic CMOS process addresses all of these limitations. First of all, by choosing special wafer substrate the depletion width can be extended up to the thickness of the substrate at the end of fabrication, which is 50µm. This results in a superior Quantum efficiency in the IR region, maintaining 80% QE at λ=900nm.

2 1.3. Integrating CMOS Devices In order to enable signal processing on the same die as the photodetector, the baseline CMOS process had to be modified. First of all, the effect of the use of a high-resistive substrate on the CMOS circuitry had to be eliminated. This was achieved by application of a dedicated high-energy implant to create a virtual low resistivity substrate region for the CMOS circuitry part. Additionally, special devices had to be developed in order to handle the higher voltages up to 12V needed to operate the CCD parts of the photodetectors. This was achieved by implementing drain-extended devices to the device portfolio. The resulting device portfolio is shown in Tab. 1. Figure 1. Quantum efficiency of epc detectors On the short end of the wavelength range, the Backside post processing can be optimized to result in ultra-shallow insensitive layers in order to achieve good QE even in the UV region where absorption length in Si is only a few nm. This optimization is completely decoupled from boundary conditions given by the CMOS part of the process since it is addressing the backside of the die. The same holds true for the reflection properties of the entrance window. Being on the backside, a well tailored AR coating can be applied to reduce the reflectivity of the detector in the desired wavelength range. So far, the AR coating has been optimized for the nm wavelength range but other designs are easy to implement. Reflectance [%] Wavelength [nm] 1.2. Minimizing Dark Durrent Silicon no AR AR Coating sim. AR Coating meas. Figure 2. Comparison SI with / without AR coating Due to the use of low doped substrate, the generation current of the bulk is low compared to standard material. Therefore even diodes with very large depletion width of 50µm show low dark current of 20 pa/mm 2, doubling roughly every 8 C. Device type Vop Purpose Nmos 1.8V Digital high speed Pmos 1.8V Digital high speed Nmos 5V Analog circuits Nmos iso 5V Analog circuits, low noise, bootstrap Pmos 5V Analog circuits Nmos DE Pmos DE 12V (Drain) 5V (Gate) 12V (Drain) 5V (Gate) Table 1. Device portfolio 1.4.Low Noise detection HV switch, Charge pump HV switch, Charge pump Pixel read-out is designed by a typical signal chain consisting of floating diffusion, source-follower with reset and row select transistor, input-buffer of an ADC and the ADC itself. We designed a 12bit SAR ADC with a signed input range from -4 to 4V since for the TOF application, the difference of two source follower outputs is sampled which can be both positive or negative. A measurement of this signal chain is shown in Fig 3. FWHM: 2 LSB Figure 3. Read-out noise

3 2. SYSTEM INTEGRATION AND ASSEMBLY 2.1. Packaging Concept The design of a thin, backside illuminated device poses completely different constraints on the topic of packaging and system integration than the standard, frontside illuminated solutions. ESPROS has set up the full fabrication flow to handle thin dies from wafer level, comprising testing, bumping, dicing, sorting & picking. On top of that, we have been able to show with our development partners that these bare die CSPs can be handled on an industrial scale SMD production line by soldering the chips directly on a standard PCB. An example is shown in Fig. 4. Since the solder bumps serve both as mechanical as well as electrical connection, the integrity of the bump connection has to be maintained throughout the life cycle of the devices. A typical case for failure is shown in Fig. 5, where thermal cycling resulted in fatigue of the solder connection. By optimizing various parameters in the chip design of the bumping areas, material selection for the solder bumping process as well as process parameters for the SMD assembly we were able to pass the TC test of 800 Cycles C without any fail, see Fig. 6. TC failures epc601 with solder balls 100 Fails [a.u.] 10 No Underfill Underfill Number of Cycles Figure 6. Histogram TC tests Figure 4. epc600 TOF chip on PCB 2.2. Package Qualification Due to the significant thermal mismatch between Si and PCB materials, strong forces are applied to the die under thermal cycling. This is especially critical for bare die CSP assembled as COB (chip on board), since no interlayer such as a lead frame or adapted mould component can absorb the forces. Figure 5: Disruption of solder ball connection after thermal cycling 3. APPLICATION EXAMPLES 3.1. Intelligent Photodiode Receivers Light barriers, light curtains, and similar industrial sensor products are consumed by the millions in today's automation markets. The receiver side of these systems is mostly based on PIN photodiodes that detect the light from the LED emitter side, either directly or reflected from the scene. The requirements of these applications centre to a high degree around detection reliability. Thus, high sensitivities and a maximal dynamic range are primary goals for such photodetectors. The achievement of both objectives is facilitated by epc's high-qe and low dark current receivers. The actual detectors are only a small part of such industrial optical sensors. Signal condition, signal processing, communication interfaces and auxiliary electronics make for the major share to form a complete sensor systems. Today, these auxiliary systems are built as discrete electronics making the final product comparably large and complex. The price pressure on the markets makes it impossible to continue this traditional route of system architecture. Higher integration levels for the individual receiver elements addresses these issues from various angles: A fully integrated optical front end combined with high performance signal and information processing as well as robust interfaces and even power supplies on-chip reduce manufacturing cost significantly. Furthermore, performance and reliability can be increased and the miniaturization aspect yields a competitive

4 advantage for the system integrator CCD Line Sensor An example for an optical detector which epc designed for a customer, is a 1024 pixel line sensor with the special feature to provide a frame store area to sample up to 7 lines before sequential read-out. The signal handling is done in the charge domain with CCD structures, i.e. the signal electrons are shifted down into the frame store CCD areas. These frame store elements are shielded from direct radiation in order to avoid lag and ghost pictures. Since the charge transfer can be done very fast, it is possible to operate the line imager up to 1 million frames per second in burst mode. The readout is done by CDS (correlated double sampling) stage for each pixel individually. The signal output is performed by analog multiplexing on a video buffer which provides operation up to 50MHz, making a continuous operation at 50kFrames/s possible. The optical sensitive area is 120µm x 1024*7.5µm. Due to the advanced design rules, the whole chip has an area of only ca. 1.6mm * 8.5mm. Figure 8. Point source used to test crosstalk of the epc CCD line sensor Figure 7. CCD line sensor concept Measurement results: Since the detection takes place in the bulk of 50µm close to the backside surface, it was questionable if a good MTF (modulation transfer function) can be preserved for a pixel pitch of 7.5µm, which corresponds to a geometrical aspect ratio of the pixel slice of more than 6:1 in height. The spacial resolution of the line sensor was tested by setting up a small point source (l=630nm). The FWHM of the PSF was determined to be 8µm by the use of a 1.75 µm commercial front-side illuminated detector. The PSF was then compared with the response of the epc901 line imager, see Fig. 8. The FWHM was nearly identical, the cross-talk was only 10%. Figure 9. NN Point source histogram, recorded on commercial 1.75µm pixel imager. The FWHM is 8µm Figure 10. NN Point source histogram epc901 line imager. Note the larger pitch of 7.5µm. Blue: ideal response without cross-talk; yellow: measured response, showing 10% cross-talk

5 3.3. 3D TOF Cameras Today's automation markets as well as growing requirements in safety and comfort for groups and individuals ask for enhanced decision making processes based on spatial 3D information. As the extraction of 3D information from 2D data is challenging and intrinsically limited, various technical approaches are pursued to capture 3D information directly. A promising candidate for doing so is 3D time-of-flight (TOF), which measures flight times of photons in order to calculate spatial distances. However, available systems capable of measuring photon flight times are either mechanically complex such as laser scanners, or they require enormous amounts of active illumination due to lack of high sensitivity photo receivers in the NIR range. Either case leads to rather bulky and costly devices which limits their suitability for larger markets such as automotive, man-machine interfaces, surveillance, machine safety, domotics, and many more. Again, next to the best available detector performance, integration will be a key success factor. The tricky part of the actual photon flight time measurement must be completely integrated on chip level, providing engineers with simple interfaces and therefore enabling them to concentrate on system integration work. With such a market offer, highly integrated 3D-TOF cameras with reasonable image resolution will open up new application fields and may well trigger a small revolution in the quickly growing imager application fields. We used the properties of the Espros Photonic CMOS process to create a System-on-chip for a time-of-flight camera that comprises all necessary subsystems such as Pixel array Analog drivers and Voltage regulators ADC conversion Digital state machine and timing generation for the illumination LED drivers Digital signal processing Non-volatile memory to store configuration parameters A floor plan of the resulting chip is shown in Fig. 11. Note that the size of the chip is only 2.55x2.55mm Figure 11: Floor plan of epc Ultra High Speed Detectors The implementation of CCD structures makes fast charge handling possible, resulting in novel applications like TOF sensors or time gated sensors for fluorescence spectroscopy. The performance of the TOF pixel implementation was evaluated using a pulsed LED light source with a FWHM in the time domain that was characterized to be ca. 10ns. In Fig. 12 the response of the TOF pixel is shown. Having a FWHM of only 16ns very fast signals can be deconvoluted on pixel level. Timing FWHW = 16ns Figure 12: Pulse response of epc TOF pixel 4. CONCLUSIONS AND OUTLOOK The imager market is one of the fastest growing segments within the worldwide semiconductor market. Currently, the drive for this growth originates mainly from mass markets such as consumer electronics or telecommunications. Higher pixel count and ever increasing frames per second have been the the dogma for further

6 development in these markets for a long time. Only recently, additional performance and process optimization aspects have seen increased attention. Industrial and scientific application fields are lagging behind as for many of these areas better optical performance, increased functionality or lower cost of ownership are key drivers rather than mere pixel count. Yet, we believe it is safe to expect a large potential to catch up on modern imager technologies, once technological offers are available that really fit the needs of these markets. The basic building blocks for such a technology haven been around for quite some time. What was missing is the combination of these individual blocks and their integration into a single technology and process portfolio, openly available and affordable for engineering and science. With our ESPROS Photonic CMOS as a key enabler and the associated products and services we have created just this an appealing offer for industrial imager- and associated markets. With best-in-class optical performance, analog-mixedsignal integration options, and cost optimized packaging solutions we lay base for future optosensitive system-on-chip innovations.