Möglichkeiten der Fehlersuche / Fehlerbehebung am fertigen ASIC Chip

Transcription

1 Möglichkeiten der Fehlersuche / Fehlerbehebung am fertigen ASIC Chip am Beispiel des Beetle readout chip GSI Darmstadt former: MPI for Nuclear Physics, Heidelberg

2 Agenda Unsightly behaviours - patches and workaround UV-Laser patch Sticky Charge 80 MHz Crosstalk Readout Baseline Variation Focused Ion Beam (FIB) patch Tristate-Patch Signal Swap Beetle 1.3 on a test PCB 2

3 Sticky Charge: Problem 3

4 Sticky Charge: Simulation 4

5 Sticky Charge: Layout 5

6 Sticky Charge: Laser opening Laser: (UV mode) remove of passivation (Oxide, Nitride, Polyimide) 6

7 Sticky Charge: Timing shift Probe needle test with positive and negative phase shift of reset signal ROAmpReset 7

8 Sticky Charge: New timing 8

9 80 MHz X-talk: Problem Cross talk with a frequency spectrum of 80 MHz present on: Digital signals, e.g. DataValid Analogue signals, e.g. AnalogOut Power supply lines: Vddd, Vdda Comparison: Beetle 1.1 Beetle 1.2 # Flip-flops # Clock buffers Guard ring logic analogue digital 9

10 80 MHz X-talk: Idea & Layout (1) 10

11 80 MHz X-talk: Layout (2) 11

12 80 MHz X-talk: Laser patch 35 µm 50 µm 12

13 EE-Gruppenmeeting 80 MHz X-talk: Pictures 13

14 80 MHz X-talk: Comparison before patch after patch 14

15 Readout Baseline Variation Difference in Vdd between ch. 0 and ch. 127: 24 mv between ch. 0 and ch. 63: 210 mv Observation: shaper bias current affects amplitude of baseline variation Laser patch: probing shaper power supply at different channels 15

16 Tristate: problem Problems with first prototype readout chip Beetle 1.0 Internal data bus between I²C-interface and registers is always zero => all setup and DAC registers are zero => Chip isn t programmable Reason for data bus problem: A bug in the extraction rules causes that a diffusion shortcut in a tristate layout wasn t seen in the LVS check as an error Normally: end of prototype chip testing 16

17 Tristate: wrong layout 17

18 Tristate: simulation 18

19 Tristate: new layout Diffusion of PMOS separated from Vdd Diffusion of NMOS separated from Gnd Additional guard ring around NMOS 19

20 Tristate: way out? Way out of the Beetle 1.0 prototype problem? Tristate patch with a Focused Ion Beam (FIB) All register should be programmable Read out of register settings via I²C is not possible 20

21 EE-Gruppenmeeting Tristate: FIB patch 1 cut 9 interconnections Chip was programmable!!! 21

22 Readout header: parity bit 1 port mode AO[0] I0 I1 I2 I3 I4 I5 I6 I7 P7 P6 P5 P4 P3 P2 P1 P0 4 port mode AO[0] I0 I4 P1 P0 AO[1] I1 I5 P3 P2 AO[2] I2 I6 P5 P4 AO[3] I3 I7 P7 P6 I0 leading bit (always 0) I1 parity of PCN (even) I2 Active EDC I3 parity of reg. CompChTh I4 parity of reg. CompMask I5 parity of reg. TpSelect I6 SEU counter <1> I7 SEU counter <0> Parity bit (I1) is wrong encoded in 4 port mode and Rclk divider = 0 (LHCb mode) all other modes or Rclk divider settings Parity bit is OK problem is understood in verilog not so easy to fix simple workaround: swap position I1 with I5 could be tested on a 1.3 with a FIB patch 22

23 Parity bit - workaround (1) schematic of parity-bit generation (part of MuxScheduler) 23

24 Parity bit - workaround (2) new schematic of parity-bit patch 24

25 Parity bit - workaround (3) Layout modification in FastControl of Beetle (could be done by a FIB) 2 cuts 2 connections ParityPCN TpSelectPar Output device of ParityPCN generation - E_XNor2 (U1126) 25

26 EE-Gruppenmeeting FIB patch (1) ParityPCN TPselectPar Polyimide partly removed with an UV laser 6 holes opened Signal lines still untouched 26

27 FIB patch (2) TPselectPar ParityPCN 27

28 FIB patch (3) And another chip... Swap header bit I1 with I5 done with a FIB patch (FEICO Munich) 28

29 FIB patch (4) 29

30 FIB patch (5) 30