A 50% Lower Power ARM Cortex CPU using DDC Technology with Body Bias. David Kidd August 26, 2013
|
|
- Melvyn Scot Sparks
- 6 years ago
- Views:
Transcription
1 A 50% Lower Power ARM Cortex CPU using DDC Technology with Body Bias David Kidd August 26, HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
2 Agenda DDC transistor and PowerShrink platform overview ARM Cortex-M0 implementation and results Application of DDC technology to HKMG nodes 2 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
3 Deeply Depleted Channel (DDC) Transistor 1 Undoped/lightly doped region Improved matching (low RDF) Higher mobility ( I D,lin ) Higher analog gain ( g m ) Gate Gate 2 V T setting offset region Multiple V T on chip Source 1 2 Drain 3 Screening region Superior scalability Improved drive current ( I eff DIBL) Higher analog gain ( R out ) Strong body coefficient (corner pull-in) One example, not drawn to scale 3 3 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
4 PLVt NLVt Corner Pull-in with Body Bias No Body Bias With Body Bias Typical Fast Corners pull in to typical I O Slow I O I ON I ON Fast I O Typical I O Slow I ON 4 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved. I ON
5 Leakage Power Leakage Power Leakage Power DDC PowerShrink Platform: Save Active and Leakage Power Using Body Bias log DDC performance is superior at matched VDD DDC 1.2V POR Save active power Lower DDC VDD 1.2V log DDC performance degrades due to lowered VDD POR DDC 1.2V 0.9V Same VDD, similar V T,sat Delay log Body bias reduces leakage power Leakage power saving POR DDC 1.2V Lowered VDD, similar V T,sat Delay Match delay Lower DDC V T,sat 0.9V Matched delay V T shifted and corners pulled in by body bias Lowered VDD, lowered V T,sat Delay 5 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
6 NMOS Bias (mv) NMOS Bias (mv) ARM Cortex-M0 CPU Bias Targeting PMOS Bias (mv) Measured ARM Cortex-M0 Speed and power response to bias 375MHz 350MHz TARGET 325MHz Speed PMOS Bias (mv) Increasing Leakage Target 350MHz Many bias voltages achieve the target frequency but power is not optimal at all biases Too Slow Leakage (delta to optimal) 6 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
7 Digital Readout Process Monitor Bias Targeting (55nm Measured) Process Monitor Corner Detection PMOS target NMOS target PMOS measured NMOS measured Process Monitor independently measures NMOS and PMOS corners Digital readout correlates to corner Bias voltage is calculated from readout Bias Target from Monitor NMOS Bias (V) Bias target calculated from monitor readout PMOS Bias (V) 7 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
8 Relative Speed Relative Power Process Monitor Bias Targeting (55nm Measured) Performance Correction Leakage Correction 170% 160% 150% 140% 130% 120% 110% 100% Zero Bias Target Bias Target 1000% 800% 600% 400% 200% 0% Zero Bias Target Bias Performance is corrected to 13% faster than target Fast corner leakage is corrected to the same point as typical 8 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
9 Power (mw) PowerShrink Platform: ARM Cortex-M0 CPU 50% power vs baseline at (leakage and dynamic) Matched performance at Baseline Baseline DDC DDC 65nm CORTEX M0 1.2V 0.9 V Corner Variation 85 C 50% DDC corner variation pull-in with bias Frequency (MHz) 9 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
10 Power (mw) Tunable Power / Performance Matched performance at 50% power 0.9V +35% performance at matched power 1.1V +55% performance at matched voltage 1.2V V Baseline DDC 0.9V 100% power 1.2V Matched Performance 1.1V 1.0V 50% power Frequency (MHz) 1.2V 55% Performance Increase 35% Performance Increase at Matched Power 65nm CORTEX M0 85 C Performance: corner Power: corner 10 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
11 ARM Cortex-M0 Body Bias Network Implementation Minimal routing resources used for bias network Route in columns Double-space bias wires for reliability 1 PMOS wire, 1 NMOS wire Vertical Track Usage per Column Layer Available Tracks Bias Tracks M M Total (0.7%) Bias Columns 11 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
12 Yield (%) Lower SRAM V DD-min Enables Low-V DD Operation V DD-min of 8Mb SRAM lowered by 150mV at 125 C Production 55nm SRAM data Target Yield Voltage (V) 55nm silicon 12 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
13 Lower SRAM Retention Power 50% less leakage in Standby and Retention modes at nominal V BS More than 5X less leakage in Retention mode with V BS = -0.6V Baseline Retention Power 53% lower 87% lower DDC Retention Power 65nm silicon 13 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
14 DDC Technology in Silicon Gate and HKMG Silicon-Gate DDC PowerShrink Memory DRAM Other DDC PowerShrink 90nm, 65nm, 55nm, 40nm Imaging WiFi CPU RF Deeply Depleted Channel (DDC) Technology Metal-Gate DDC PowerShrink 28nm, 20nm CPUs + GPUs SoC Networking FPGA DDC DesignBoost 28nm, 20nm CPUs + GPUs Networking Mixed Signal Display Drivers GPS SoC FPGA Proven, Legacy Technology Nodes Advanced 14 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
15 DDC Technology Modular Implementation 15 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
16 Leakage Power Leakage Power DDC DesignBoost: Target Leakage Power Savings log DDC performance is superior at matched VDD log Recover Leakage by Trading off Performance DDC POR 0.9V Save Leakage Power Increase DDC V T,sat POR DDC Leakage power 0.9V 0.9V saving Improved performance 0.9V Matched performance Same VDD, similar V T,sat Delay Same VDD, higher V T,sat Delay DDC DesignBoost 16 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
17 Normalized Leakage DDC DesignBoost Motivation 100% 90% 80% 70% 60% 50% HVT SVT LVT SLVT C LVT SLVT 40% 30% 20% 10% HVT SVT 0% Low Performance Leakage Low Performance Usage High Performance Leakage High Performance Usage Normalized Speed LVT and SLVT devices contribute a large portion of the leakage power at advanced nodes Leakage power reduction is a key value adder for high performance designs 17 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
18 Relative Power Baseline DDC Baseline DDC DDC DesignBoost Power Savings in HKMG LVT Devices Active Power Leakage Power Small Dynamic Savings Due to better device capacitance Big Leakage Savings Speed Power DDC DesignBoost Target matched performance to reduce Ioff 18 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
19 Power Savings 0.9V DesignBoost 0.9V DesignBoost + Body Bias 0.8V PowerShrink HKMG Power Analysis 0.9V DesignBoost 0.9V with Body Bias 0.8V PowerShrink HKMG design 10% activity factor DDC DesignBoost No design change Body Bias improves power savings PowerShrink platfrom For active power dominated circuits Active Dominated Leakage Dominated 100% SVT 100% LVT All transistors are DDC transistors 125C Speed Power 19 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
20 Summary ARM Cortex-M0 validated at 65nm Matched performance at 50% power +35% performance at matched power +55% performance at matched voltage SRAM validated at 65nm and 55nm 150mV Vmin reduction in production 55nm SRAM Less than 50% static power in standby and retention DDC technology demonstrated at advanced HKMG nodes Lower static power at matched performance Lower active power with body bias 20 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
21 21 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved.
Process and Design Solutions for Exploiting FD SOI Technology Towards Energy Efficient SOCs
Process and Design Solutions for Exploiting FD SOI Technology Towards Energy Efficient SOCs Philippe FLATRESSE Technology R&D Central CAD & Design Solutions STMicroelectronics International Symposium on
More informationMillimeter-Scale Nearly Perpetual Sensor System with Stacked Battery and Solar Cells
1 Millimeter-Scale Nearly Perpetual Sensor System with Stacked Battery and Solar Cells Gregory Chen, Matthew Fojtik, Daeyeon Kim, David Fick, Junsun Park, Mingoo Seok, Mao-Ter Chen, Zhiyoong Foo, Dennis
More informationAdaptive Voltage Scaling (AVS) Alex Vainberg October 13, 2010
Adaptive Voltage Scaling (AVS) Alex Vainberg Email: alex.vainberg@nsc.com October 13, 2010 Agenda AVS Introduction, Technology and Architecture Design Implementation Hardware Performance Monitors Overview
More informationLecture 14. Advanced Technologies on SRAM. Fundamentals of SRAM State-of-the-Art SRAM Performance FinFET-based SRAM Issues SRAM Alternatives
Source: Intel the area ratio of SRAM over logic increases Lecture 14 Advanced Technologies on SRAM Fundamentals of SRAM State-of-the-Art SRAM Performance FinFET-based SRAM Issues SRAM Alternatives Reading:
More informationNear-Threshold Computing: Reclaiming Moore s Law
1 Near-Threshold Computing: Reclaiming Moore s Law Dr. Ronald G. Dreslinski Research Fellow Ann Arbor 1 1 Motivation 1000000 Transistors (100,000's) 100000 10000 Power (W) Performance (GOPS) Efficiency (GOPS/W)
More informationThe FD-SOI technology for very high-speed and energy efficient SoCs. Giorgio Cesana STMicroelectronics
The FD-SOI technology for very high-speed and energy efficient SoCs Giorgio Cesana STMicroelectronics 2 FD-SOI Technology height Bulk Transistor Reaching Limits at 20nm 3 FD-SOI = 2D Limited body bias
More informationLow Voltage Bandgap References and High PSRR Mechanism
Low Voltage Bandgap References and High PSRR Mechanism Vahe Arakelyan 2nd year Master Student Synopsys Armenia Educational Department, State Engineering University of Armenia Moscow March 21-24, 2011 Outline
More informationDesign and Technology Trends
Lecture 1 Design and Technology Trends R. Saleh Dept. of ECE University of British Columbia res@ece.ubc.ca 1 Recently Designed Chips Itanium chip (Intel), 2B tx, 700mm 2, 8 layer 65nm CMOS (4 processors)
More informationLow Power SRAM Techniques for Handheld Products
Low Power SRAM Techniques for Handheld Products Rabiul Islam 5 S. Mopac, Suite 4 Austin, TX78746 5-4-45 rabiul.islam@intel.com Adam Brand Mission College Blvd Santa Clara, CA955 48-765-546 adam.d.brand@intel.com
More informationECE 571 Advanced Microprocessor-Based Design Lecture 24
ECE 571 Advanced Microprocessor-Based Design Lecture 24 Vince Weaver http://www.eece.maine.edu/ vweaver vincent.weaver@maine.edu 25 April 2013 Project/HW Reminder Project Presentations. 15-20 minutes.
More informationIO & ESD protection 1.8V & 3.3V capable general purpose digital IO pad based on 1.8V devices for TSMC 28nm CMOS technology
Data sheet IO & ESD protection 1.8V & 3.3V capable general purpose digital IO pad based on 1.8V devices for TSMC 28nm CMOS technology Sofics has verified its TakeCharge ESD protection clamps on TSMC 28nm
More informationFujitsu Semiconductor s development team focused on forming FLOTOX using only low-temperature processes.
Fujitsu Semiconductor Successfully Embeds Flash Memory onto DDC Technology Further expands scope of the Mie Plant s process technology for low-power devices Yokohama, Japan, December 10, 2013 Fujitsu Semiconductor
More informationMemory Design I. Array-Structured Memory Architecture. Professor Chris H. Kim. Dept. of ECE.
Memory Design I Professor Chris H. Kim University of Minnesota Dept. of ECE chriskim@ece.umn.edu Array-Structured Memory Architecture 2 1 Semiconductor Memory Classification Read-Write Wi Memory Non-Volatile
More informationAdvanced Digital Integrated Circuits. Lecture 9: SRAM. Announcements. Homework 1 due on Wednesday Quiz #1 next Monday, March 7
EE241 - Spring 2011 Advanced Digital Integrated Circuits Lecture 9: SRAM Announcements Homework 1 due on Wednesday Quiz #1 next Monday, March 7 2 1 Outline Last lecture Variability This lecture SRAM 3
More informationFPGA Power Management and Modeling Techniques
FPGA Power Management and Modeling Techniques WP-01044-2.0 White Paper This white paper discusses the major challenges associated with accurately predicting power consumption in FPGAs, namely, obtaining
More informationSYNTHESIS FOR ADVANCED NODES
SYNTHESIS FOR ADVANCED NODES Abhijeet Chakraborty Janet Olson SYNOPSYS, INC ISPD 2012 Synopsys 2012 1 ISPD 2012 Outline Logic Synthesis Evolution Technology and Market Trends The Interconnect Challenge
More informationDVFS Space Exploration in Power-Constrained Processing-in-Memory Systems
DVFS Space Exploration in Power-Constrained Processing-in-Memory Systems Marko Scrbak and Krishna M. Kavi Computer Systems Research Laboratory Department of Computer Science & Engineering University of
More informationMemory Design I. Semiconductor Memory Classification. Read-Write Memories (RWM) Memory Scaling Trend. Memory Scaling Trend
Array-Structured Memory Architecture Memory Design I Professor hris H. Kim University of Minnesota Dept. of EE chriskim@ece.umn.edu 2 Semiconductor Memory lassification Read-Write Memory Non-Volatile Read-Write
More informationVdd Programmable and Variation Tolerant FPGA Circuits and Architectures
Vdd Programmable and Variation Tolerant FPGA Circuits and Architectures Prof. Lei He EE Department, UCLA LHE@ee.ucla.edu Partially supported by NSF. Pathway to Power Efficiency and Variation Tolerance
More informationSoitec ultra-thin SOI substrates enabling FD-SOI technology. July, 2015
Soitec ultra-thin SOI substrates enabling FD-SOI technology July, 2015 Agenda FD-SOI: Background & Value Proposition C1- Restricted July 8, 2015 2 Today Ultra-mobile & Connected Consumer At Any Time With
More informationImplementation of DRAM Cell Using Transmission Gate
Implementation of DRAM Cell Using Transmission Gate Pranita J. Giri 1, Sunanda K. Kapde 2 PG Student, Department of E&TC, Deogiri Institute of Engineering & Management Studies, Aurangabad (MS), India 1
More informationPower Solutions for Leading-Edge FPGAs. Vaughn Betz & Paul Ekas
Power Solutions for Leading-Edge FPGAs Vaughn Betz & Paul Ekas Agenda 90 nm Power Overview Stratix II : Power Optimization Without Sacrificing Performance Technical Features & Competitive Results Dynamic
More informationJames Lin Vice President, Technology Infrastructure Group National Semiconductor Corporation CODES + ISSS 2003 October 3rd, 2003
Challenges for SoC Design in Very Deep Submicron Technologies James Lin Vice President, Technology Infrastructure Group National Semiconductor Corporation CODES + ISSS 2003 October 3rd, 2003 1 Contents
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 23-1 guntzel@inf.ufsc.br Semiconductor Memory Classification
More informationCentip3De: A 64-Core, 3D Stacked, Near-Threshold System
1 1 1 Centip3De: A 64-Core, 3D Stacked, Near-Threshold System Ronald G. Dreslinski David Fick, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman
More informationDEVELOPMENT OF AN AREA-EFFICIENT AND LOW-POWER FIVE-TRANSISTOR SRAM FOR LOW-POWER SOC
DEVELOPMENT OF AN AREA-EFFICIENT AND LOW-POWER FIVE-TRANSISTOR SRAM FOR LOW-POWER SOC by Hooman Jarollahi B.A.Sc., Engineering Science Simon Fraser University, 2008 THESIS SUBMITTED IN PARTIAL FULFILLMENT
More informationMoore s Law: Alive and Well. Mark Bohr Intel Senior Fellow
Moore s Law: Alive and Well Mark Bohr Intel Senior Fellow Intel Scaling Trend 10 10000 1 1000 Micron 0.1 100 nm 0.01 22 nm 14 nm 10 nm 10 0.001 1 1970 1980 1990 2000 2010 2020 2030 Intel Scaling Trend
More informationPOWER EFFICIENT SRAM CELL USING T-NBLV TECHNIQUE
POWER EFFICIENT SRAM CELL USING T-NBLV TECHNIQUE Dhanya M. Ravi 1 1Assistant Professor, Dept. Of ECE, Indo American Institutions Technical Campus, Sankaram, Anakapalle, Visakhapatnam, Mail id: dhanya@iaitc.in
More informationAdvanced Digital Integrated Circuits. Lecture 9: SRAM. Announcements. Homework 1 due on Wednesday Quiz #1 next Monday, March 7
EE24 - Spring 20 Advanced Digital Integrated Circuits Lecture 9: SRAM Announcements Homework due on Wednesday Quiz # next Monday, March 7 2 Outline Last lecture Variability This lecture SRAM 3 Practical
More informationAn FPGA Architecture Supporting Dynamically-Controlled Power Gating
An FPGA Architecture Supporting Dynamically-Controlled Power Gating Altera Corporation March 16 th, 2012 Assem Bsoul and Steve Wilton {absoul, stevew}@ece.ubc.ca System-on-Chip Research Group Department
More information6T- SRAM for Low Power Consumption. Professor, Dept. of ExTC, PRMIT &R, Badnera, Amravati, Maharashtra, India 1
6T- SRAM for Low Power Consumption Mrs. J.N.Ingole 1, Ms.P.A.Mirge 2 Professor, Dept. of ExTC, PRMIT &R, Badnera, Amravati, Maharashtra, India 1 PG Student [Digital Electronics], Dept. of ExTC, PRMIT&R,
More informationDRAM with Boosted 3T Gain Cell, PVT-tracking Read Reference Bias
ASub-0 Sub-0.9V Logic-compatible Embedded DRAM with Boosted 3T Gain Cell, Regulated Bit-line Write Scheme and PVT-tracking Read Reference Bias Ki Chul Chun, Pulkit Jain, Jung Hwa Lee*, Chris H. Kim University
More informationFABRICATION TECHNOLOGIES
FABRICATION TECHNOLOGIES DSP Processor Design Approaches Full custom Standard cell** higher performance lower energy (power) lower per-part cost Gate array* FPGA* Programmable DSP Programmable general
More informationAddressable Test Chip Technology for IC Design and Manufacturing. Dr. David Ouyang CEO, Semitronix Corporation Professor, Zhejiang University 2014/03
Addressable Test Chip Technology for IC Design and Manufacturing Dr. David Ouyang CEO, Semitronix Corporation Professor, Zhejiang University 2014/03 IC Design & Manufacturing Trends Both logic and memory
More informationTHE latest generation of microprocessors uses a combination
1254 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 11, NOVEMBER 1995 A 14-Port 3.8-ns 116-Word 64-b Read-Renaming Register File Creigton Asato Abstract A 116-word by 64-b register file for a 154 MHz
More informationPostsilicon Adaptation for Low-Power SRAM under Process Variation
Postsilicon Calibration and Repair for Yield and Reliability Improvement Postsilicon Adaptation for Low-Power SRAM under Process Variation Minki Cho Georgia Institute of Technology Jason Schlessman Princeton
More informationDesign of Low Power Wide Gates used in Register File and Tag Comparator
www..org 1 Design of Low Power Wide Gates used in Register File and Tag Comparator Isac Daimary 1, Mohammed Aneesh 2 1,2 Department of Electronics Engineering, Pondicherry University Pondicherry, 605014,
More informationLeakage Mitigation Techniques in Smartphone SoCs
Leakage Mitigation Techniques in Smartphone SoCs 1 John Redmond 1 Broadcom International Symposium on Low Power Electronics and Design Smartphone Use Cases Power Device Convergence Diverse Use Cases Camera
More informationOUTLINE Introduction Power Components Dynamic Power Optimization Conclusions
OUTLINE Introduction Power Components Dynamic Power Optimization Conclusions 04/15/14 1 Introduction: Low Power Technology Process Hardware Architecture Software Multi VTH Low-power circuits Parallelism
More informationLecture 4a. CMOS Fabrication, Layout and Simulation. R. Saleh Dept. of ECE University of British Columbia
Lecture 4a CMOS Fabrication, Layout and Simulation R. Saleh Dept. of ECE University of British Columbia res@ece.ubc.ca 1 Fabrication Fabrication is the process used to create devices and wires. Transistors
More informationDigital Integrated Circuits A Design Perspective. Jan M. Rabaey
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Outline (approximate) Introduction and Motivation The VLSI Design Process Details of the MOS Transistor Device Fabrication Design Rules CMOS
More informationFinFETs: Quo Vadis? Niraj K. Jha Dept. of Electrical Engineering Princeton University
FinFETs: Quo Vadis? Niraj K. Jha Dept. of Electrical Engineering Princeton University Talk Outline Quo Vadis FinFET devices? Quo Vadis FinFET standard cells and logic circuits? Addressing the Power Wall
More informationPower, Performance and Area Implementation Analysis.
ARM Cortex -R Series: Power, Performance and Area Implementation Analysis. Authors: Neil Werdmuller and Jatin Mistry, September 2014. Summary: Power, Performance and Area (PPA) implementation analysis
More informationIntroducing the 22FDX. 22nm FD-SOI Platform. from GLOBALFOUNDRIES
Introducing the 22FDX 22nm FD-SOI Platform from GLOBALFOUNDRIES March 2016 Introduction Selecting a next generation technology platform for your new product is a critical decision. Product requirements
More informationCircuits. L3: Fabrication and Layout -1 ( ) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number
EE60: CMOS Analog Circuits L: Fabrication and Layout - (8.8.0) B. Mazhari Dept. of EE, IIT Kanpur Suppose we have a Silicon wafer which is P-type and we wish to create a region within it which is N-type
More informationDevelopment of Low Power and High Performance Application Processor (T6G) for Multimedia Mobile Applications
Session 8D-2 Development of Low Power and High Performance Application Processor (T6G) for Multimedia Mobile Applications Yoshiyuki Kitasho, Yu Kikuchi, Takayoshi Shimazawa, Yasuo Ohara, Masafumi Takahashi,
More informationLow-Power Programmable FPGA Routing Circuitry
1 Low-Power Programmable FPGA Routing Circuitry Jason H. Anderson, Member, IEEE, and Farid N. Najm, Fellow, IEEE Abstract We consider circuit techniques for reducing FPGA power consumption and propose
More informationDesign and Simulation of Low Power 6TSRAM and Control its Leakage Current Using Sleepy Keeper Approach in different Topology
Vol. 3, Issue. 3, May.-June. 2013 pp-1475-1481 ISSN: 2249-6645 Design and Simulation of Low Power 6TSRAM and Control its Leakage Current Using Sleepy Keeper Approach in different Topology Bikash Khandal,
More informationMTJ-Based Nonvolatile Logic-in-Memory Architecture
2011 Spintronics Workshop on LSI @ Kyoto, Japan, June 13, 2011 MTJ-Based Nonvolatile Logic-in-Memory Architecture Takahiro Hanyu Center for Spintronics Integrated Systems, Tohoku University, JAPAN Laboratory
More informationTechnology Platform Segmentation
HOW TECHNOLOGY R&D LEADERSHIP BRINGS A COMPETITIVE ADVANTAGE FOR MULTIMEDIA CONVERGENCE Technology Platform Segmentation HP LP 2 1 Technology Platform KPIs Performance Design simplicity Power leakage Cost
More informationBasic Sample and Hold Element. Prof. Paul Hasler Georgia Institute of Technology
Basic Sample and Hold Element Prof. Paul Hasler Georgia Institute of Technology Sample and Hold Elements Sample and Hold Elements Amplitude (Hold) (Sample) (Hold) Time Sample and Hold Elements Amplitude
More informationGigascale Integration Design Challenges & Opportunities. Shekhar Borkar Circuit Research, Intel Labs October 24, 2004
Gigascale Integration Design Challenges & Opportunities Shekhar Borkar Circuit Research, Intel Labs October 24, 2004 Outline CMOS technology challenges Technology, circuit and μarchitecture solutions Integration
More informationPower Reduction Techniques in the Memory System. Typical Memory Hierarchy
Power Reduction Techniques in the Memory System Low Power Design for SoCs ASIC Tutorial Memories.1 Typical Memory Hierarchy On-Chip Components Control edram Datapath RegFile ITLB DTLB Instr Data Cache
More informationProcess Technologies for SOCs
UDC 621.3.049.771.14.006.1 Process Technologies for SOCs VTaiji Ema (Manuscript received November 30, 1999) This paper introduces a family of process technologies for fabriating high-performance SOCs.
More informationReduce Your System Power Consumption with Altera FPGAs Altera Corporation Public
Reduce Your System Power Consumption with Altera FPGAs Agenda Benefits of lower power in systems Stratix III power technology Cyclone III power Quartus II power optimization and estimation tools Summary
More informationCENG 4480 L09 Memory 2
CENG 4480 L09 Memory 2 Bei Yu Reference: Chapter 11 Memories CMOS VLSI Design A Circuits and Systems Perspective by H.E.Weste and D.M.Harris 1 v.s. CENG3420 CENG3420: architecture perspective memory coherent
More informationRegularity for Reduced Variability
Regularity for Reduced Variability Larry Pileggi Carnegie Mellon pileggi@ece.cmu.edu 28 July 2006 CMU Collaborators Andrzej Strojwas Slava Rovner Tejas Jhaveri Thiago Hersan Kim Yaw Tong Sandeep Gupta
More informationDESIGN AND SIMULATION OF 1 BIT ARITHMETIC LOGIC UNIT DESIGN USING PASS-TRANSISTOR LOGIC FAMILIES
Volume 120 No. 6 2018, 4453-4466 ISSN: 1314-3395 (on-line version) url: http://www.acadpubl.eu/hub/ http://www.acadpubl.eu/hub/ DESIGN AND SIMULATION OF 1 BIT ARITHMETIC LOGIC UNIT DESIGN USING PASS-TRANSISTOR
More information3D systems-on-chip. A clever partitioning of circuits to improve area, cost, power and performance. The 3D technology landscape
Edition April 2017 Semiconductor technology & processing 3D systems-on-chip A clever partitioning of circuits to improve area, cost, power and performance. In recent years, the technology of 3D integration
More informationVery Large Scale Integration (VLSI)
Very Large Scale Integration (VLSI) Lecture 8 Dr. Ahmed H. Madian ah_madian@hotmail.com Content Array Subsystems Introduction General memory array architecture SRAM (6-T cell) CAM Read only memory Introduction
More informationInternational Journal of Scientific & Engineering Research, Volume 5, Issue 2, February ISSN
International Journal of Scientific & Engineering Research, Volume 5, Issue 2, February-2014 938 LOW POWER SRAM ARCHITECTURE AT DEEP SUBMICRON CMOS TECHNOLOGY T.SANKARARAO STUDENT OF GITAS, S.SEKHAR DILEEP
More informationA Novel Methodology to Debug Leakage Power Issues in Silicon- A Mobile SoC Ramp Production Case Study
A Novel Methodology to Debug Leakage Power Issues in Silicon- A Mobile SoC Ramp Production Case Study Ravi Arora Co-Founder & CTO, Graphene Semiconductors India Pvt Ltd, India ABSTRACT: As the world is
More informationLow-Power Technology for Image-Processing LSIs
Low- Technology for Image-Processing LSIs Yoshimi Asada The conventional LSI design assumed power would be supplied uniformly to all parts of an LSI. For a design with multiple supply voltages and a power
More informationDDRO: A Novel Performance Monitoring Methodology Based on Design-Dependent Ring Oscillators
DDRO: A Novel Performance Monitoring Methodology Based on Design-Dependent Ring Oscillators Tuck-Boon Chan, Puneet Gupta, Andrew B. Kahng and Liangzhen Lai UC San Diego ECE and CSE Departments, La Jolla,
More informationZ-RAM Ultra-Dense Memory for 90nm and Below. Hot Chips David E. Fisch, Anant Singh, Greg Popov Innovative Silicon Inc.
Z-RAM Ultra-Dense Memory for 90nm and Below Hot Chips 2006 David E. Fisch, Anant Singh, Greg Popov Innovative Silicon Inc. Outline Device Overview Operation Architecture Features Challenges Z-RAM Performance
More informationEmbedded Memory Alternatives
EE241 - Spring 2005 Advanced Digital Integrated Circuits Lecture 26: Embedded Memory - Flash Slides Courtesy of Randy McKee, TI Embedded Memory Alternatives Courtesy Randy McKee, TI 2 1 3 4 2 5 SRAM 3
More informationEfficient Systems. Micrel lab, DEIS, University of Bologna. Advisor
Row-based Design Methodologies To Compensate Variability For Energy- Efficient Systems Micrel lab, DEIS, University of Bologna Mohammad Reza Kakoee PhD Student m.kakoee@unibo.it it Luca Benini Advisor
More informationUnderstanding the tradeoffs and Tuning the methodology
Understanding the tradeoffs and Tuning the methodology Graham Scott, Technical Lead ARM Cortex Application Processors, Cadence Nandan Nayampally, Director CPU Product Marketing, ARM Inc 1 Agenda Market
More informationEE241 - Spring 2007 Advanced Digital Integrated Circuits. Announcements
EE241 - Spring 2007 Advanced Digital Integrated Circuits Lecture 22: SRAM Announcements Homework #4 due today Final exam on May 8 in class Project presentations on May 3, 1-5pm 2 1 Class Material Last
More informationA Review Paper on Reconfigurable Techniques to Improve Critical Parameters of SRAM
IJSRD - International Journal for Scientific Research & Development Vol. 4, Issue 09, 2016 ISSN (online): 2321-0613 A Review Paper on Reconfigurable Techniques to Improve Critical Parameters of SRAM Yogit
More informationDesign and Analysis of Ultra Low Power Processors Using Sub/Near-Threshold 3D Stacked ICs
Design and Analysis of Ultra Low Power Processors Using Sub/Near-Threshold 3D Stacked ICs Sandeep Kumar Samal, Yarui Peng, Yang Zhang, and Sung Kyu Lim School of ECE, Georgia Institute of Technology, Atlanta,
More informationLow Power SRAM Design with Reduced Read/Write Time
International Journal of Information and Computation Technology. ISSN 0974-2239 Volume 3, Number 3 (2013), pp. 195-200 International Research Publications House http://www. irphouse.com /ijict.htm Low
More informationA 65nm LEVEL-1 CACHE FOR MOBILE APPLICATIONS
A 65nm LEVEL-1 CACHE FOR MOBILE APPLICATIONS ABSTRACT We describe L1 cache designed for digital signal processor (DSP) core. The cache is 32KB with variable associativity (4 to 16 ways) and is pseudo-dual-ported.
More informationOptimizing Standby
Optimizing Power @ Standby Memory Benton H. Calhoun Jan M. Rabaey Chapter Outline Memory in Standby Voltage Scaling Body Biasing Periphery Memory Dominates Processor Area SRAM is a major source of static
More informationYield-driven Near-threshold SRAM Design
Yield-driven Near-threshold SRAM Design Gregory K. Chen, David Blaauw, Trevor Mudge, Dennis Sylvester Department of EECS University of Michigan Ann Arbor, MI 48109 grgkchen@umich.edu, blaauw@umich.edu,
More informationAnalysis of 8T SRAM Cell Using Leakage Reduction Technique
Analysis of 8T SRAM Cell Using Leakage Reduction Technique Sandhya Patel and Somit Pandey Abstract The purpose of this manuscript is to decrease the leakage current and a memory leakage power SRAM cell
More informationSTUDY OF SRAM AND ITS LOW POWER TECHNIQUES
INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET) International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN ISSN 0976 6464(Print)
More informationA 65nm 8T Sub-V t SRAM Employing Sense-Amplifier Redundancy
A 65nm Sub-V t SRAM Employing Sense-Amplifier Redundancy Naveen Verma and Anantha Chandrakasan Massachusetts Institute of Technology ISSCC 2007 Energy Minimization Minimum energy V DD for logic results
More informationOptimizing Standby
Optimizing Power @ Standby Circuits and Systems Jan M. Rabaey Chapter Outline Why Sleep Mode Management? Dynamic power in standby Clock gating Static power in standby Transistor sizing Power gating Body
More informationOPERATIONAL UP TO. 300 c. Microcontrollers Memories Logic
OPERATIONAL UP TO 300 c Microcontrollers Memories Logic Whether You Need an ASIC, Mixed Signal, Processor, or Peripheral, Tekmos is Your Source for High Temperature Electronics Using either a bulk silicon
More informationSynopsys Design Platform
Synopsys Design Platform Silicon Proven for FDSOI Swami Venkat, Senior Director, Marketing, Design Group September 26, 2017 2017 Synopsys, Inc. 1 Synopsys: Silicon to Software Software Application security
More informationUnleashing the Power of Embedded DRAM
Copyright 2005 Design And Reuse S.A. All rights reserved. Unleashing the Power of Embedded DRAM by Peter Gillingham, MOSAID Technologies Incorporated Ottawa, Canada Abstract Embedded DRAM technology offers
More informationInternational Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
IP-SRAM ARCHITECTURE AT DEEP SUBMICRON CMOS TECHNOLOGY A LOW POWER DESIGN D. Harihara Santosh 1, Lagudu Ramesh Naidu 2 Assistant professor, Dept. of ECE, MVGR College of Engineering, Andhra Pradesh, India
More informationSpiral 2-8. Cell Layout
2-8.1 Spiral 2-8 Cell Layout 2-8.2 Learning Outcomes I understand how a digital circuit is composed of layers of materials forming transistors and wires I understand how each layer is expressed as geometric
More informationNovel Nonvolatile Memory Hierarchies to Realize "Normally-Off Mobile Processors" ASP-DAC 2014
Novel Nonvolatile Memory Hierarchies to Realize "Normally-Off Mobile Processors" ASP-DAC 2014 Shinobu Fujita, Kumiko Nomura, Hiroki Noguchi, Susumu Takeda, Keiko Abe Toshiba Corporation, R&D Center Advanced
More informationEnergy-Efficient Cache Memories using a Dual-V t 4T SRAM Cell with Read-Assist Techniques
Energy-Efficient Cache Memories using a Dual-V t SRAM with Read-Assist Techniques Alireza Shafaei and Massoud Pedram Department of Electrical Engineering, University of Southern California, Los Angeles,
More informationJae Wook Lee. SIC R&D Lab. LG Electronics
Jae Wook Lee SIC R&D Lab. LG Electronics Contents Introduction Why power validation on mobile application processor? Then, what to validate? Who is in charge of validation? Power Validation Components
More informationA Low Power SRAM Cell with High Read Stability
16 ECTI TRANSACTIONS ON ELECTRICAL ENG., ELECTRONICS, AND COMMUNICATIONS VOL.9, NO.1 February 2011 A Low Power SRAM Cell with High Read Stability N.M. Sivamangai 1 and K. Gunavathi 2, Non-members ABSTRACT
More informationPower Gate Optimization Method for In-Rush Current and Power Up Time
Power Gate Optimization Method for In-Rush Current and Power Up Time Presenter : Teng, Siong Kiong Ung, Chee Kong Intel Corporation Intel and the Intel logo are registered trademarks of Intel Corporation
More informationESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Today. Memory Bank. Multiport RAM. Simple Idea.
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Multiport SRAM DRAM Today Day 30: November 12, 2014 Memory Core: Part 2 1 2 Memory Bank Multiport RAM 3 4 Mulitport Simple Idea
More informationIMEC CORE CMOS P. MARCHAL
APPLICATIONS & 3D TECHNOLOGY IMEC CORE CMOS P. MARCHAL OUTLINE What is important to spec 3D technology How to set specs for the different applications - Mobile consumer - Memory - High performance Conclusions
More informationUltra-Low-Power Circuits for Wearables
Ultra-Low-Power Circuits for Wearables Philippe Bourban 30.11.2016 Outline ON Semiconductor quick facts Power budget of some wearable devices Things to think about to make ULP circuits A few circuit examples
More informationQualification Strategies of Field Programmable Gate Arrays (FPGAs) for Space Application October 26, 2005
Qualification Strategies of Field Programmable Gate Arrays (FPGAs) for Space Application October 26, 2005 Douglas Sheldon Harald Schone Historical FPGAs have been used in spacecraft for over 10 years.
More informationMoore s s Law, 40 years and Counting
Moore s s Law, 40 years and Counting Future Directions of Silicon and Packaging Bill Holt General Manager Technology and Manufacturing Group Intel Corporation InterPACK 05 2005 Heat Transfer Conference
More informationDESIGN AND IMPLEMENTATION OF 8X8 DRAM MEMORY ARRAY USING 45nm TECHNOLOGY
DESIGN AND IMPLEMENTATION OF 8X8 DRAM MEMORY ARRAY USING 45nm TECHNOLOGY S.Raju 1, K.Jeevan Reddy 2 (Associate Professor) Digital Systems & Computer Electronics (DSCE), Sreenidhi Institute of Science &
More informationAMchip architecture & design
Sezione di Milano AMchip architecture & design Alberto Stabile - INFN Milano AMchip theoretical principle Associative Memory chip: AMchip Dedicated VLSI device - maximum parallelism Each pattern with private
More informationFully Depleted SOI Technologies. Bich-Yen Nguyen
Fully Depleted SOI Technologies Bich-Yen Nguyen Acknowledgements SOITEC Team: Jean-Michel Bidault Nicolas Daval Frederic Allibert Ludovic Ecarnot Konstantin Bourdelle Walter Schwarzenbach Mariam Sadaka
More informationDesign and Implementation of Low Leakage Power SRAM System Using Full Stack Asymmetric SRAM
Design and Implementation of Low Leakage Power SRAM System Using Full Stack Asymmetric SRAM Rajlaxmi Belavadi 1, Pramod Kumar.T 1, Obaleppa. R. Dasar 2, Narmada. S 2, Rajani. H. P 3 PG Student, Department
More informationLab. Course Goals. Topics. What is VLSI design? What is an integrated circuit? VLSI Design Cycle. VLSI Design Automation
Course Goals Lab Understand key components in VLSI designs Become familiar with design tools (Cadence) Understand design flows Understand behavioral, structural, and physical specifications Be able to
More information2731GN-120V Datasheet Class-AB GaN-on-SiC HEMT Transistor
2731GN-120V Datasheet Class-AB GaN-on-SiC HEMT Transistor Microsemi Corporate Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100
More information