A solution path to True optical packet switch

Transcription

1 Optical RAM: A solution path to True optical packet switch Ken-ichi Kitayama Osaka University kitayama@commengosaka-uacjp Sept19, 2009 北山 ECOC2009 Workshop Optics in Computing 1 Osaka Univ

2 Acknowledgments Colleagues of the 5-year-long (2006~2010) R&D program, Optical RAM for all-optical packet switch, supported by NICT NTT Photonics Labs & Basic Research Labs Osaka University Kyushu University NEC Sept19, 2009 北山 ECOC2009 Workshop Optics in Computing 2 Osaka Univ

3 Growth of e-router capacity GEpps, OFC2008, Workshop Sept19, 2009 北山 ECOC2009 Workshop Optics in Computing 3 Osaka Univ

4 What are problems with conventional e-router? Segmented into 8 small fixed-length packets for low-speed parallel proc Large buffer required to store all the small-size packets for the assembly Fill Interframe Gap (IFG) Input buffering, Label proc Output buffering Line Card Line Card Input packets 8 x e-switching planes O/E E/O E/O Large buffer required to store all the input packets for segmentation O/E O O/E E/O O/E DEMUX Line Card MUX E E/O E Large power dissipation due to MUX/DEMUX Sept19, 2009 北山 ECOC2009 Workshop Optics in Computing 4 Osaka Univ

5 High-end e-routers : A product example Cisco will continue to push traditional technology, by GEpps Maximum configuration: 92Tbps Paralleism can be pushed further, by RTucker 72 x LC chassis + 8 x Fabric chassis Is e-router s capacity growth sustainable in speed and power consumption? Is e-router s e router s CO2 footprint acceptable for Green IT? 14kW x 92 ~1 MegaWatt!! Cisco CRS CRS-1 1 with 1000 ports ports, 250 ms(10gbps) buffering per port GEpps, OFC2008, Workshop ECOC2009 Workshop Optics in Computing Sept19, 2009 北山 5 Osaka Univ

6 Challenges of optical packet switch Solution path to the bottlenecks of e-routers Power-consumption bottleneck Speed bottleneck Challenges: Clean-slate photonic-native architecture Totally different from current e-routers,, aiming at small-buffer size, high-speed as well as low-power consumption Sept19, 2009 北山 ECOC2009 Workshop Optics in Computing 6 Osaka Univ

7 Architecture of True optical packet switch Fill Interframe Gap (IFG) Input packets Input buffering, Label proc O/E E/O Line Card Header processor 8 x e-switching planes Optical switch E/O O/E Output buffering Line Card Optical buffer E/O O/E Scheduler Sept19, 2009 北山 ECOC2009 Workshop Optics in Computing 7 Osaka Univ

8 Architecture of optical RAM buffer subsystem Scheduler Write-in address Read-out light source Readout address Input packet Optical add dresser 2-D array optical bit memory (100x100) Coup pler : Serial-to-parallel converter : Parallel-to-serial converter Write-in light source Optical signal Electrical signal Sept19, 2009 北山 ECOC2009 Workshop Optics in Computing 8 Osaka Univ

9 Optically Write/Read techniques i) Addressing in space 2-D PC memory array Signal light ii) Adressing in spectral domain Bias light Signal light Wavelength converter Bias light Sept19, 2009 北山 ECOC2009 Workshop Optics in Computing 9 Osaka Univ

10 InGaAsP PC resonator m-ingaasp 32x6um PhC engineerings intensity Light [ W] ut Memory outp [a u] P in 30 m ]Write Erase 10 2 (Signal-in) (Bias-off) 10 24fJ (2) ON (3) 250ns (1) (4) 3 m P out 10 W W/o erase W erase Reducing adversary thermal effect by smaller PhC area, bandgap narrowing, smoothing PhC surface Fast heat diffusion Protect carrier diffusion using BH Minimum i power of bias 10 WW light Energy of signal light Retention time 24 fj 250 ns Note: 1500B Ethernet frame~300ns@40gbps OFF OFF 300 Time (ns) Sept19, 2009 北山 ECOC2009 Workshop Optics in Computing 10 Osaka Univ

11 Optical bistable operation of PC resonator Bias Signal Read Reset ON pulse in off in off 30 Transm mission 1 0 Ou utput power [5dB/div] Bias Signal Read pulse =15430 nm Optical power Challenges Bias Signal =15428 nm Readout Micro-cavity Output Input power in PhC waveguie [dbm] 30 m Long retention time High-dense integration up to 100k~1M Reset 400nm Output Sept19, 2009 北山 ECOC2009 Workshop Optics in Computing 11 Osaka Univ

12 Switch architectures : Optical RAM vs WC w/ Optical RAM buffer w/o Optical RAM buffer Sept19, 2009 北山 ECOC2009 Workshop Optics in Computing 12 Osaka Univ

13 Packet loss rate Poisson arrival 100 Buffer 40Gbps 4x4 sw, 8 s, M shared buffers with feedback #1 Packet lenghs: 40B (75%), 1500B (25%) 100 #15 Contention cannot be resolved with only wavelength conversion w/o buffer but solved with small buffer Buffer retention time ~200ns shows a low packet loss rate with 15 buffer palnes, 22500B (=180kbits) in the switch up the load of 02 Sept19, 2009 北山 ECOC2009 Workshop Optics in Computing 13 Osaka Univ

14 Power consumption : How far we can go? Currently In 2015~2019 e - Router 1 MW (14nW/bit) (14nW/bit)1/5~1/ 1/2 05 MW /7 OPS 200~300 kw 100~50 kw Using O-E-O buffer Using optical RAM Note: 16x16x 72 40Gbps Sept19, 2009 北山 ECOC2009 Workshop Optics in Computing 14 Osaka Univ

15 Thank you! Questions? Sept19, 2009 北山 ECOC2009 Workshop Optics in Computing 15 Osaka Univ

16 Architecture of optical RAM buffer system Scheduler Write-in address Read-out light source Readout address Input packet Optical add dresser 2-D array optical bit memory Coup pler : Serial-to-parallel converter : Parallel-to-serial converter Write-in light source Optical signal Electrical signal Sept19, 2009 北山 ECOC2009 Workshop Optics in Computing 16 Osaka Univ

17 Optical addressing in space using MMI switch 1550nm CW Phase shifter Applied voltage Wavelength dependence< ±1dB Rise time=14ns, Fall time=12ns Extiction ratio=10db Sept19, 2009 北山 ECOC2009 Workshop Optics in Computing 17 Osaka Univ

18 Optical addressing in spectral domain Tunable laser MZ-SOA 8x8 AWGF Requirements for Tunable laser Compact Easy to integrate other components Low tuning current Response time ~5ns Port 3 Port 4 Compact wavelength routing switch 51mm x 21 mm Port 5 (500 ns/div) Sept19, 2009 北山 ECOC2009 Workshop Optics in Computing 18 Osaka Univ

19 Architecture of optical RAM buffer system Scheduler Write-in address Read-out light source Readout address Input packet Optical add dresser 2-D array optical bit memory Coup pler : Serial-to-parallel converter : Parallel-to-serial converter Write-in light source Optical signal Electrical signal Sept19, 2009 北山 ECOC2009 Workshop Optics in Computing 19 Osaka Univ

20 All-optical SP/PS bidirectional converter Pump pulse PBS 0 Collimator /4 plate Input packet 2 3 Delay lines Time window PBS Parallel output Surfacenormal alloptical switch Pump pulse 0 Output packet 2 3 PBS Parallel input Sept19, 2009 北山 ECOC2009 Workshop Optics in Computing 20 Osaka Univ

21 Optical memory devices All-optical RAM FIFO (First-in-first-out) Slow light Fiber delay line Bit-by-bit memory via bistability Contl of prop length Contl of GV Passive (non-radiative) Active (radiative) Fiber loop Material dispersion Waveguide dispersion Micro-cavity Surfaceemission Waveguide Fiber Semicon Fiber Semicon Semicon Photonic crystal Micro ring Pol bistability MMI-BDL flip-flop sw + fiber Quantum wire EIT, CPO, FWM Photonic Crystal Cell size 10 m m m 2 * m 2 Large Compact Compact Compact Power consumption ~10 W ~100 W ~10mW ~100mW ** 1W/pkt 2W/pkt** - - Access speed *** *** ~10ps ~10ps 7ps <100ps A few ns A few ns A few ns *** A few ns *** Access Parallel/ serial Parallel/ serial 2-D parallel Parallel Parallel Parallel Parallel Parallel Notes -sensitive PDL PDL FIFO Narrow bandwidth **** All-optical shift register Discrete time Short time storage Large-scale s/p conv Small capacity Small capacity * <10x10 m 2 + I/O=>30x30 m 2 ** Depending on optical amplifier count *** Speed of optical switch **** < 20GHz Note: SRAM: <06 m 2, <1 W, <2ns w/o O-E-O Sept19, 2009 北山 ECOC2009 Workshop Optics in Computing 21 Osaka Univ

22 Rule of thumb Buffer size for packet routers #1: Larger the buffer size is, the lower the packet loss probability becomes #2: TCP requires the buffer capacity B; B = RTT x Link capacity Note1: For RTT=250 ms@40gbps, B=10 Gbits => 36Mbit-SRAM x 300 Note2: OC192 (10Gbps) line card has a 16Gbits buffer (13k Ether packets) Recent findings Good news for all packet routers! Buffer size can be reduced to B=RTT x Link capacity/ n (n: connection count) Ex Buffer size for 1Mbps flows x can be reduced from 10Gbits to 50Mbits Paced TCP can further reduce the buffer size down to10~20 packets Issues Paced TCP Access:25Mbps Is this only the case with ADSL? What happens to > gigabit access? Is it practical that TCP has to be replaced with another TCP at end hosts? M Enachescu, Y Ganjali, A Goel, N McKeown, and TRoughgarden Part III: Routers with very small buffers ACM/SIGCOMM CCR, 2005 MWang, Globecom2007, G06P04 (Washington DC, Dec208) Sept19, 2009 北山 ECOC2009 Workshop Optics in Computing 22 Osaka Univ

23 Architecture of conventional e-router Segmented into 8 small fixed-length packets for low-speed prallel proc Large buffer required to store all the small-size packets for the assembly Fill Interframe Gap (IFG) Input buffering, Label proc Output buffering Line Card Line Card Input packets 8 x e-switching planes O/E E/O E/O Large buffer required to store all the input packets for segmentation O/E O O/E E/O O/E ~1 MegaWatt / 10??? DEMUX Line Card MUX E E/O E OPS with 1000 ports, with optical RAM buffer Large power dissipation due to MUX/DEMUX Sept19, 2009 北山 ECOC2009 Workshop Optics in Computing 23 Osaka Univ