Software Stacks for Mixed-critical Applications: Consolidating IEEE AVB and Time-triggered Ethernet in Next-generation Automotive Electronics

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1 Sofware Sacks for Mixed-criical Applicaions: Consolidaing IEEE 8.1 and Time-riggered Eherne in Nex-generaion Auomoive Elecronics Soeren Rumpf, Till Seinbach, Franz Korf, Thomas C. Schmid Deparmen of Compuer Science Hamburg Universiy of Applied Sciences, Germany {ill.seinbach, korf, Absrac Real-ime Eherne varians are expeced o build he fuure communicaion infrasrucure in cars. Firs camera based driver assisance funcions will communicae using IEEE 8.1 s credi-based shaping. Bu for he sric iming requiremens of auomoive conrol-raffic, s curren iming guaranees are insufficien. The upcoming IEEE 8.1Qbv sandard proposes synchronous ime-riggered raffic o overcome hese limiaions. This paper presens a low fooprin microconroller based communicaion archiecure, ha suppors boh raffic classes in parallel while using sandard hardware componens. I allows firs realisic performance analyses of coexisen raffic shaping sraegies in a sofware based implemenaion. I. INTRODUCTION Today s auomobiles uilise an increasing number of elecronic conrol unis (ECUs) o implemen he various safey and comfor funcions offered in recen cars. For each applicaion a se of ECUs, physically disribued over he whole vehicle, is required. This archiecure demands a communicaion infrasrucure ha is able o ranspor daa wih high predicabiliy and exac iming. For legacy reasons, several differen communicaion echnologies, each opimised for specific use-cases, are used oday. Examples are he Conroller Area Nework (CAN) [1], Media Oriened Sysems Transpor (MOST) [] or FlexRay []. This echnology diversiy led o a highly heerogeneous in-car nework ha is exremely complex, difficul o develop, configure and mainain, and in erms of bandwidh consumpion a is limis. Real-ime Eherne is a promising soluion o reduce he complexiy imposed by oday s heerogenous, gaeway-based auomoive neworks, while providing addiional bandwidh for upcoming feaures. Eherne will ener he auomobile hrough in-car mulimedia and camera based driver assisance sysems wih moderae iming guaranees in he range of microseconds, which is a ypical use-case for he Eherne Audio/Video Bridging () proocol suie []. This firs generaion uses Eherne as an addiional communicaion infrasrucure, which runs in parallel o he well-esablished communicaion echnologies (e.g. CAN, FlexRay, MOST,...) and provides he bandwidh required by new driver assisance funcions, for example camera based advanced driver assisance sysems (ADAS). The second generaion of swiched real-ime Eherne based communicaion srucures in cars will provide a backbone for a subse of applicaions of differen in-car domains. While in his archiecure some ECUs will be equipped wih an Eherne inerface, oher ECUs will sill be conneced wih he backbone via a CAN o Eherne gaeway. Some of he applicaions ha will be ransferred o Eherne in he second generaion require a laency below 1 ms over up o seven hops. These rigid real-ime requiremens canno be achieved wih oday s proocol suie. Recenly, he sandardisaion of scheduled raffic was sared o improve o saisfy he requiremens of ulra low laency and jier []. IEEE 8.1Qbv (Enhancemens for Scheduled Traffic) adds synchronous imeriggered messages o he even-based shaping of. This raffic is based on a coordinaed ime-division muliple access (TDMA) scheme and prevens concurren access of ougoing line cards o achieve a deerminisic ransmission. The concurren uilisaion of he same physical Eherne by differen raffic classes, like, ime-riggered, and sandard bes-effor raffic, causes effecs of inerference ha have o be carefully regarded when designing auomoive neworks. To evaluae he conceps of Eherne wih addiional ime-riggered scheduling, we conribue a prooype archiecure and implemenaion of he raffic shaping conceps in a sofware sack for an ARM9 based sysem-onchip. Using his archiecure, firs design conceps for in-car neworks wih upcoming sandards such as IEEE 8.1Qbv [] can be evaluaed on a hardware plaform ha is based on sandard componens and offers realisic performance and emporal characerisics, comparable wih cerified auomoive hardware. The focus of his work is o provide a prooype plaform for various use-cases. For example, gaeways beween real-ime Eherne and legacy fieldbuses ha require a variey of differen service classes. This paper is organised as follows: In Secion II, we inroduce he conceps of Eherne and ime-riggered Eherne and presen previous and relaed work. Secion III presens he concep and archiecure. In Secion IV, deails from he implemenaion as well as he evaluaion resuls are shown and discussed. Finally, Secion V concludes our work and gives an oulook on our fuure research.

2 Class-A Chassis Class-B Bes- Effor 1 riy Selecion Bes-Effor Egress Credi Shaper (CBS) Egress... cycle Diagnosis Cam RC BE BE BE E-Swich RC BE BE BE cycle RC BE E-Swich Time-Triggered Message Rae-Consrained Message Bes-Effor Message Fig. 1. IEEE 8.1Qav Sender/Forwarding: Transmission selecion scheme Fig.. riising and ime-riggered media access in ime-riggered Eherne A. IEEE 8.1 II. BACKGROUND & RELATED WORK The IEEE 8.1 Audio/Video Bridging () [] suie consiss of proocols for low laency sreaming over 8 neworks. Besides exensions for nework managemen, i defines precise ime synchronisaion (IEEE 8.1QAS) wih a synchronisaion error of less han 1 µs over a maximum of seven hops [6], [7], dynamic sream reservaion (IEEE 8.1Qa) and real-ime raffic shaping (IEEE 8.1Qav) for ime sensiive applicaions. IEEE 8.1Qav defines queuing and forwarding rules for real-ime sreams using sric prioriies and credi based shaping (CBS). For laency requiremens up o a maximum of ms over seven hops, sream reservaion (SR) class-a was defined. SR class-b guaranees laency requiremens of up o ms. All oher raffic is reaed as bes-effor raffic using legacy Eherne frames. Transmission selecion and raffic shaping in IEEE 8.1Qav uses a credi based shaping (CBS) algorihm wih prioriies. The ransmission of a SR class frame is only allowed when he amoun of available credis is greaer or equal. An upper and lower bound of he credi based shaper limis he sreams bandwidh and bursiness. Figure 1 shows he scheme for ransmission selecion. To realise a dynamic online regisraion of new real-ime sreams, Eherne defines he IEEE 8.1Qa [8] Sream Reservaion Proocol (SRP). I provides a hree sep signalling process (i.e., sream adverisemen, regisraion and deregisraion) o reserve he required resources along he pah beween sender and receiver. B. Time-riggered Eherne Besides several oher real-ime exensions for sandard Eherne, e.g. PROFINET [9], Eherne (AS68) [1] is a ime-riggered exension for Eherne based communicaion wih low laency and jier. AS68 is sandardized by he Sociey of Auomoive Engineers (SAE) [11]. I feaures hree differen raffic classes: For ime-riggered () communicaion, pre-configured schedules assign dedicaed ransmission slos o each paricipan. This coordinaed ime-division-muliple-access (TDMA) muliplexing sraegy allows deerminisic ransmission wih predicable delay. I prevens congesion on ougoing line cards and enables isochronous communicaion wih low laency and jier. To realise he TDMA concep, a failsafe synchronisaion proocol, wih an error below 1 µs, implemens a global ime among all paricipans. In addiion o synchronised ime-riggered messages, wo even-riggered message classes are defined: Rae-consrained (RC) raffic is inended for he ransmission of messages wih moderae iming requiremens. I limis he sreams bandwidh and prioriises according o he sraegy of he ARINC-66 (AFDX) proocol [1]. The characerisics of RC raffic are comparable wih s SR Classes A and B. Bes-effor (BE) raffic conforms o sandard Eherne messages ha are ransmied wih he lowes prioriy. The laer allows he inegraion of hoss ha are unaware of he realime proocol and remain unsynchronised. These nodes communicae using bes-effor messages. Figure shows he media access policy for messages of differen raffic classes. Due o he early sae of IEEE 8.1Qbv, in his paper he ime-riggered raffic class of AS68 is used in conjuncion wih IEEE 8.1Qav [1]. Neverheless, he naure of imeriggered raffic will allow o ransfer he resuls o an upcoming IEEE sandard wih scheduled raffic. C. Relaed & Previous Work In previous performance assessmens, srenghs and weaknesses of ime-riggered Eherne and were revealed and an approach wih and ime-riggered messages on a shared infrasrucure as conribued in his work was proposed [1]. There are already microconroller based sofware sacks available. XMOS offers an reference design [1] ha in conras o he concep of his work relies on a mulicore-plaform and does no suppor scheduled raffic. Their xcore archiecure disribues he applicaion and he sack on differen processor cores o allow inerference free execuion of differen asks. Oher sraegies han ime-riggered messages o improve end-o-end laency in neworks are analysed by Imiaz, Jasperneie and Weber [16]. In place of scheduled raffic, he auhors argue in favour of smaller frames o reduce he impac of congesion. The general feasibiliy of a sofware based ime-riggered real-ime communicaion sack was shown in previous work [17]. Furher, he concep of a credi based shaper (CBS) wih suppor for ime-riggered scheduling was previously evaluaed using even-based simulaion [18].

3 1 Time-riggered Virual Links (VL) Timeriggered Scheduler () Class-A Class-B Bes- Effor 1 riy Selecion Bes-Effor Egress Time Aware CBS Clock Schedule Por Time-riggered + + Bes-Effor Egress VL VL VL VL... VL 1 Daaflow Conrolflow Fig.. Transmission Selecion Algorihm for and ime-riggered raffic. CBS uses clock and schedule, enabling communicaion wih no inerference III. CONCEPT & ARCHITECTURE A sofware sack for mixed-criical applicaions requires reliable iming o schedule message ransmission and ask execuion o ensure ha criical applicaions mach heir given boundaries. The synchronisaion process is imporan for imeriggered proocols and herefor mus be suppored by he archiecure. Furhermore, he bandwidh of 1 Mbi/s per por demands a memory archiecure ha is able o manage high daa hroughpu. Due o faul olerance hrough redundancy, he sysem has o handle ransmission and recepion on muliple pors concurrenly. A. Time Aware Credi Shaper Figure shows our concep for a ime aware credi based shaper (CBS) which joins scheduled ime-riggered raffic and raffic shaped using he IEEE 8.1Qav algorihms. Timeriggered raffic is no allowed o be delayed by any oher frame, hough he frames mus have he highes prioriy. This requiremen conflics wih he service class A of IEEE 8.1Qav ha uses he highes prioriy for is end-o-end performance guaranees. Due o he modified prioriies in our concep, changes in he queueing and scheduling sraegy of he frames mus be made. In our concep, he ime-riggered send-windows and he domain wide synchronised clock are used as inpu for he Credi Shaping (CBS) algorihm (see Figure ). This allows he algorihm o checks wheher a ransmission can be finished before he nex window sars. If no frame fis, he ransmier remains idle unil he ransmission of he nex scheduled frame begins. This idle ime someimes referred o as guard band guaranees ha and bes-effor frames will never inerfere wih frames. The new ime aware CBS will inroduce furher delays for all raffic classes of. For example, if an frame is ready o be ransmied and oo large o be sen before he sar of he nex window, he frame will be queued. In previous work we already showed ha wih a valid schedule he laency guaranee of SR class A ( ms over 7 hops) is wice as long ( ms) as in he original sandard [18]. B. Pariion An exended scheduler has o be designed o avoid congesion in he mixed-criical applicaions, using ime-riggered Eherne and. The concep behind his scheduler is o reassign prioriies o give ime-riggered raffic he highes prioriy followed by classes A & B and bes-effor raffic. Since he ime-criical ime-riggered slos are saic and known before runime, he scheduler is configured wih he imeriggered iming, so ha he unused scheduling ime can be used o schedule and bes-effor raffic (see Figure ). C. Archiecure Besides he sack componens wih he dynamic sream reservaion module (IEEE 8.1Qa), here are buffers for each Sream Reservaion (SR) class where class A has he second highes prioriy, and an inerval lengh of 1 µs and a maximum laency of ms over seven hops o hold incoming and ougoing frames. Boh sacks share he synchronisaion module, bes-effor modules, and have a scheduler which ensures ha here is no frame inerference beween and ime-riggered Eherne packes. The resuling archiecure is shown in Figure. In addiion, he archiecure uses a dedicaed Sream Reservaion Proocol (SRP) module ha works according o IEEE 8.1Qa [8] o implemen an online signalling proocol for he real-ime service classes of. This module mus work independen from he real-ime scheduling and is no allowed o inerfere wih real-ime raffic. Thus he plaform mus provide sric prioriies o preven inerference by he sream reservaion frames. For he communicaion beween he sack and he mixed-criical applicaions he archiecure inroduces a dedicaed -API ha is derived from he implemenaion of he API of he Eherne proocol.

4 Configuraion Applicaion Applicaion Applicaion Time-Triggered Sack Scheduler & RC Buffer E API Synchronizaion RX TX Mixed Scheduler BE Buffer Hardware Absracion Layer Hardware API Sack Sream Reservaion Proocol CBS Scheduler SR Class A & B Buffer Applicaion Layer Link Layer Physical Layer Inerarrival Time [us] Time [ms] Fig.. Mixed criical sack archiecure, ime-riggered Eherne and Fig.. Inerarrival ime a he applicaion layer using he presened approach a he sender and receiver side IV. IMPLEMENTATION & EVALUATION RESULTS A. Plaform The concep is based on a highly inegraed hardware plaform using a sysem-on-chip design developed by Hilscher [19]. The modular plaform design provides four independenly configurable communicaion channels for various communicaion echnologies like Eherne or CAN [1] wih dedicaed Arihmeic Logic Uni (ALU). The ALU is programmable o implemen MAC (Medium Access Conroller), PEC (Proocol Execuion Conroller) and, especially for Eherne, PHY (Physical inerface) funcionaliy. The ALUs of all channels operae concurrenly. For he applicaion code and sofware sacks an ARM96EJ CPU is inegraed which runs a MHz. I provides a memory managemen uni, 8 kb daa- and 16 kb insrucion cache, 8 kb ighly coupled daa memory and a kb ROM holding he boo loader and a real-ime kernel. I also provides an inernal memory of 1 kb RAM. The daa ransfer beween he communicaion channels and he CPU is provided by a daa swich, which replaces he usual AMBA (Advanced Microconroller Bus Archiecure). This swich is able o open up o five communicaion channels a he same ime and hereby allows o send and receive muliple frames on differen pors concurrenly. A dedicaed sysem ime module provides imesamps for incoming frames and is used o schedule he ime-riggered code execuion. I is clocked wih 1 MHz and uses an adjusable incremen in a resoluion of 8 ns o compensae deviaion and drif of he oscillaor. This precisely adjusable clock is used o manage and mainain a sable ime base for he clock synchronisaion. Comparing he memory consumpion of he sofware sack modules, he Eherne par requires 1 kb. The implemenaion adds 19.1 kb. The consumpion of he sub modules is lised in Table I. Since hey combine he major funcions of, he CBS (9 %), (. %) and MRP (1.8 %) modules are he larges. B. Evaluaion To quanify he overhead imposed by he sream reservaion proocol, CPU uilisaion for he periodic updae and he processing of incoming MRP frames is measured. The periodic ask requires.98 µs per updae. As i is riggered only once per second i is negligible. The processing of MRP frames adds. µs o he sandard recepion rouine. As he number of MRP frames correlaes o he number of paricipans, burss of MRP frames can occur in large neworks. In his case he sream reservaion may be delayed as he frame processing ime exceeds he ransmission ime. The MRP proocol is based on bes-effor raffic and allows hese small delays. Furhermore he quanified overhead imposed by he CBS (Credi Shaper) and he accuracy of he iner-arrival imes on he sender and receiver side is measured. Wih a minimum execuion ime of 16. µs and a maximum of 7. µs he CBS processing of a class A sream resuls in a oal CPU uilisaion of 6. %. The iner-arrival ime a he applicaion TABLE I MEMORY CONSUMPTION OF THE MODULES REQUIRED FOR Memory Module Consumpion [kb] % Talker.7. Credi Shaper API Timer.. MRP MMRP.9. MVRP.8. SRP Toal

5 layer of class A frames (see Fig. ) shows a sligh jier of ± µs which is caused by he send and receive rouines. Since he bandwidh is calculaed correcly and he imer which calls he send rouine precisely riggers every 1 µs, his jier is wihin an accepable range for a CBS sofware implemenaion. The jier is by magniudes below he jier imposed by concurren raffic [18]. V. CONCLUSION & OUTLOOK Fuure in-car communicaion infrasrucures are expeced o rely on real-ime Eherne. For he challenging imingrequiremens of such Eherne based backbones, specialised sofware sacks for mixed-criical applicaions are required, o allow sric emporal precision and deerminisic ransmission. Wih his paper we show a concep for a ime aware credi based shaper and conribue a low fooprin microconroller based communicaion archiecure supporing synchronous ime-riggered and asynchronous even-riggered raffic in parallel while using sandard hardware componens. Our approach joins IEEE 8.1 s credi-based shaper wih a scheduler ha provides suppor for ime-riggered raffic, allowing he inegraion of he upcoming IEEE 8.1Qbv sandard. Our prooype implemenaion using a sysem-on-chip design wih an ARM9 CPU running a only MHz shows he feasibiliy of he concep. I uses a minimal sysem wih a simple prioriy based scheduler and hardware resources comparable wih hose uilised in upcoming series cars. Wihou furher opimisaion he implemenaion of s credi based shaper uilises approximaely 7 % of he available compuaion ime. Togeher wih he sream reservaion proocol he sacks fingerprin is below kb. The Evaluaion of he sack reveals a jier of approximaely 1 µs measured in he recepion rouine of he receiver. This is he absolue jier when using he presened implemenaion as sending and receiving device. As in average he iner-arrival ime is 1 µs, he sack is in compliance wih he reserved bandwidh coningens. In fuure work we will improve he performance of he implemenaion. Furher, we will analyse how specialised Eherne hardware can suppor he raffic shaping o reduce CPU uilisaion and sofware complexiy. ACKNOWLEDGEMENTS This work is funded by he Federal Minisry of Educaion and Research of Germany (BMBF) wihin he RECBAR projec. REFERENCES [1] Inernaional Organizaion for Sandardizaion, Road vehicles Conroller Area Nework (CAN), ISO, Genf, ISO 11898,. [] MOST Cooperaion, Media Oriened Sysems Transpor. [Online]. Available: hp:// [] FlexRay Consorium, Proocol Specificaion, FlexRay Consorium, Sugar, Specificaion..1, Oc. 1. [] IEEE 8.1 Task Group, IEEE 8.1 Audio/Video Bridging (). [Online]. Available: hp:// hml [] IEEE 8.1 TSN Task Group, IEEE 8.1Qbv - Enhancemens for Scheduled Traffic. [Online]. Available: hp:// pages/8.1bv.hml [6] M. D. J. Teener and G. M. Garner, Overview and iming performance of ieee 8.1as, in IEEE Inernaional Symposium on Precision Clock Synchronizaion for Measuremen, Conrol and Communicaion (ISPCS 8). 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C. Schmid, A Real-ime Eherne Prooype Plaform for Auomoive Applicaions, in 11 IEEE Inernaional Conference on Consumer Elecronics - Berlin (ICCE- Berlin). Piscaaway, New Jersey: IEEE Press, Sep. 11, pp. 1. [18] P. Meyer, T. Seinbach, F. Korf, and T. C. Schmid, Exending IEEE 8.1 wih Time-riggered Scheduling: A Simulaion Sudy of he Coexisence of Synchronous and Asynchronous Traffic, in 1 IEEE Vehicular Neworking Conference (VNC). Piscaaway, New Jersey: IEEE Press, Dec. 1, pp. 7. [19] J. Lipfer, Technical Daa Reference Guide - nex/1, Hilscher GmbH, Dec. 8. [Online]. Available: hp://