International SpaceWire Conference 17 th 19 th September A SpaceWire Implementation of Chainless Boundary Scan Architecture for Embedded Testing

Transcription

1 International SpaceWire onference 7 th 9 th September 2007 A SpaceWire Implementation of hainless Boundary Scan Architecture for Embedded Testing Mohammed Ali* Mohammed.Ali@astrium.eads.net Dr. Omar Emam Omar.emam@astrium.eads.net * Work carried out as part of PhD Leicester Univeristy International SpaceWire onference. 7 th 9 th September 2007, Dundee, Scotland. 25/09/2007 p

2 Introduction urrently Astrium Ltd uses JTAG boundary scan to perform embedded testing. This has been successful on missions such as Inmarsat 4 and Skynet 5. This presentation proposes a novel boundary scan architecture hainless Boundary Scan (Patent filed) which is well suited to SpaceWire based systems. What is JTAG boundary Scan and how does it work? International SpaceWire onference. 7 th 9 th September 2007, Dundee, Scotland. 25/09/2007 p2

3 JTAG Boundary Scan- Background JTAG Stands for: Joint Test Action Group The Group was setup in 985 in Europe (Known as JETAG) In 986, It expanded to include members outside of Europe and hence dropped the E from JETAG to become JTAG) The IEEE49. std. was approved on the 5 th September 990 and is known as: IEEE Standard Test Access Port and Boundary Scan Architecture How does boundary scan work? International SpaceWire onference. 7 th 9 th September 2007, Dundee, Scotland. 25/09/2007 p3

4 Boundary Scan ell Boundary-scan Boundary-scan register register formed formed from from silicon silicon nails nails cells. cells. P-IN S-IN P-OUT S-OUT Internal core logic Memory element called scan-cell Data registers BP Identity register * TDO Instruction register TK TMS Instruction register TAP controller TRST* * = OPTIONAL within IEEE Std. 49. International SpaceWire onference. 7 th 9 th September 2007, Dundee, Scotland. 25/09/2007 p4

5 Example: Performing interconnect Testing External Interconnects Between two Is I I2 Boundary-scan register formed from silicon nails cells Internal ore Logic 0 0 Internal ore Logic BP ID REG* TDO BP ID REG* TDO INST REG INST REG Test Access Port Test Access Port TMS TRST* TRST* TK International SpaceWire onference. 7 th 9 th September 2007, Dundee, Scotland. 25/09/2007 p5

6 Daisy-chaining Boundary Scan omponents & Issues TDO 2 TDO 3 TDO TDO 4 TMS TK Issues: Breaks in the chain onnecting many components into small number of chains (conventional test equipment provides 4 hains). Throughput, management of different logic and different supply levels, redundancy. International SpaceWire onference. 7 th 9 th September 2007, Dundee, Scotland. 25/09/2007 p6

7 Time for a change International SpaceWire onference. 7 th 9 th September 2007, Dundee, Scotland. 25/09/2007 p7

8 Typical based Architecture Memory Sensor P P2 Sensor P3 P Processor Array Memory 2 International SpaceWire onference. 7 th 9 th September 2007, Dundee, Scotland. 25/09/2007 p8

9 hainless Boundary Scan 2 Test Equipment or Ground Station Any comms link BIST ontroller Memory 3 4 Key Target Hardware n = omponent n International SpaceWire onference. 7 th 9 th September 2007, Dundee, Scotland. 25/09/2007 p9

10 to Boundary Scan Adapter Data Bus Packet Packet Interpreter Interpreter Packet Packet Assembler Assembler Block Block A Packet Packet ommand Bus TRLs TAP Macro command Interpreter & I/F adapter Block TAP I/F Boundary Scan TAP ontroller and registers Block B External TAP I/F omponent omponent external external I/Os I/Os O D E O D E O D E O D E I/Fs Physical Layer Host device internal logic (e.g. DSP ASI) if adapter is not stand-alone. Block can either be standalone or form part of either Block A or Block B. Micro-cmd Test data trl signals Internal ore Logic BP ID REG* INST REG TAP ontroller 0 TDO TMS TK TRST* - Boundary Scan Adapter Internal TAP trl I/F External TAP I/F International SpaceWire onference. 7 th 9 th September 2007, Dundee, Scotland. 25/09/2007 p0

11 Hybrid Solution D7 External TAP I/F hainless based Architecture 2 3 BIST ontroller Memory Operator ommand & Data I/F Stand-alone Stand-alone - - Boundary Boundary Scan Scan Adapter Adapter IP IP with with Boundary Boundary Scan Scan Gateable Gateable (G8R) (G8R) TAP TAP 2 TAP 3 TAP 4 - Boundary Scan Adapter IP D D4 Spare D5 omponent with standard boundary scan Standard Boundaryscan Architecture. D to D6 D2 D6 omponents with built-in - Boundary Scan Adapter IP D3 Hybridised hainless and Standard Boundary Scan Architecture International SpaceWire onference. 7 th 9 th September 2007, Dundee, Scotland. 25/09/2007 p

12 onclusion hainless Boundary scan using based architecture provides the following advantages: Tests can still be performed even after one or more components have been configured in functional mode or if a failure of a component occurs. The boundary scan vectors can be transported across the network in macro-command and data packets without having to translate them into IEEE49. signal compatible format. Allows in-orbit testing possible as no additional test infrastructure is required. International SpaceWire onference. 7 th 9 th September 2007, Dundee, Scotland. 25/09/2007 p2