High Parallelism Memory Test Advances based on MicroSpring Contact Technology

Transcription

1 High Parallelism Memory Test Advances based on MicroSpring Contact Technology Thomas Homorodi- Director of Marketing Robert Martin Technical Sales Eng. Southwest Test Workshop June 2001

2 Contents Introduction to FormFactor FormFactor Mission 100 mm Four Touchdown Probe Solution Cost of Ownership Specifications Performance Electrical Scrub alignment over temperature MicroSpring array durability Summary and Conclusions p. 2

3 Introduction to FormFactor FormFactor Established 1993 Livermore, CA 325 Employees WaferProbe Probe Card Products PH50, PH75 and new PH100 T1/T2.1 MicroSpring contact technology High parallelism memory and C4 probing p. 3

4 FormFactor Mission Reduce the cost of test through: Increased parallelism Improved productivity Reduced maintenance and cleaning Meet new technology needs: Reduced pad size and pitch Improved electrical and mechanical performance Support new tester platforms Extend technology developed for DRAM to provide solutions for FLASH and logic probing p. 4

5 Trends in High Parallelism Probing Die in Parallel Current and Historic Trends Test Parallelism $ $$ $$$ $$$$ p. 5

6 Test Cost of Ownership Analysis 8 Virtual FAB - 25,000 wafer starts per month Product - 128M SDRAM Good Die Value = $4 Die Size = 50mm 2 Test time increases 15% per 2x test parallelism Compare the following situations: Test Parallelism Tester Cost 32 DUT $1.8M 64 DUT $2.2M 117 DUT $3.5M p. 6

7 High Parallelism Probing Reduces Touchdowns required Number of Touchdowns PH50 PH75 PH100 x32 x64 x117 p. 7

8 High Parallelism Probing Reduces Test Cost per DUT $0.25 $0.20 $0.15 $0.10 $0.05 $0.00 Total Test Cost per Good Die PH50 PH75 PH100 x32 x64 x117 p. 8

9 High Parallelism Probing Delivers Overall Cost Savings $200 5 Year Test Cell Equipment Costs $150 $100 $50 $0 Millions PH50 PH75 PH100 x32 x64 x117 p. 9

10 PH100-4 Touchdown Solution: Spring Technology and Active Area: T1-105 mm x 110 mm T mm array diagonal Planarity < 38 microns across array Both support: Lead on center and edge pad designs Odd # of rows and columns p. 10

11 PH100-4 Touchdown Solution: Probe Head: Multilayer ceramic 7544 I/O resources Supports maximum resources of Probe One and T5375 x128 test parallelism possible p. 11

12 MicroSpring Test Interface System Planarizers Controlled impedance PCB Resilient Microspring Interposer T1 Probe Array T2.1 Probe Array Space transformer with Microspring TM probes p. 12

13 MicroSpring Interposer Printed circuit board to ceramic interface Wide range of compliance Capable of 15 mil adjustment range p. 13

14 PH DUTs, 128M SDRAM p. 14

15 MicroSpring Array Performance Measured on the API PRVX 2 Electrical Performance -C(res) Alignment and planarity of x117 array Scrub Mark Verification on API wafer WoRx Alignment across array at 25 and 88C 4797 MicroSprings were measured on API PRVX 2 p. 15

16 1600 PH100 Path Resistance Number of MicroSprings Path Resistance (Ohms) p. 16

17 PH100 Alignment Error from Pad Center 1200 Number of MicroSprings MicroSpring Radial Error (um) p. 17

18 PH100 Planarity Number of MicroSprings Planarity (um) p. 18

19 Scrub Alignment vs. Temperature Scrub mark alignment Distance from center of pad to center of scrub API waferworx: 1170 Duts x 42 pads/dut = 49,140 scrub marks 3 wafers probed at 25 C and 88 C Delta scrub alignment 25 C vs. 88 C p. 19

20 Scrub Alignment at 25 C Scrub Position at Ambient - Prober Error Removed p. 20

21 Scrub Alignment at 88 C Scrub Position at 88C - Prober Error Removed p. 21

22 Delta Scrub Alignment 25 C to 88 C p. 22

23 Summary and Conclusions Increases in parallelism significantly reduce overall cost of test MicroSpring technology is capable of supporting large, high pin count, array areas FormFactor s PH100 will support the next generation of high parallelism probe arrays while maintaining stability over time and temperature p. 23

24 Special Thanks Alec Gomez Teradyne Touchdowns on x117 PC John Strom API WaferWorx analysis Chris Buckholtz FormFactor Experiment support p. 24