POWER4 Test Chip. Bradley D. McCredie Senior Technical Staff Member IBM Server Group, Austin. August 14, 1999

Transcription

1 Bradley D. McCredie Senior Technical Staff Member Server Group, Austin August 14, 1999

2 Presentation Overview Design objectives Chip overview Technology Circuits Implementation Results

3 Test Chip Objectives Technology feasibility Understand product level Silicon technology Vehicle for small device level experiments from manufacturing as well as design Understand product level packaging technology Critical circuit learning Logic circuitry Clocks I/O Arrays Power delivery Design team skills building 40% of product design team contributed to the POWER4 test chip design Many facets of the design exercised to product level requirements Tools learning > 80% of point tools exercised Execute methodology on a large chip

4 Test Chip Overview Powered on 12/17/98 Included in : Experiments from each unit of the POWER4 chip (called s) L1, L2, trace and SLB caches Product level pumped I/O design implemented Product level clock design implemented Experiments to stress power delivery Engineering and service processor interface On chip tester Chip characteristics: 379 mm 2 35 million transistors 2,217 chip signal I/Os Built to product level test requirements

5 Test Chip Logic Diagram tns_noise_shell tc_fuse tb_lbist_tc tb_abist_tc z_io g_global_clock ths_therm_sense PO PI 2 2 yss_self_sync (8 per "core" mesh and 8 in the "GPS" area) tng_noise_gen Noise Generator Block x16 4 x 16 Noise Control Block x24 noise run tpg_pattern_gen.vhdl 10 x 64 pattern enable pattern controls 640 t_lbus.vhdl 256 t_rbus.vhdl SCom Mode Reg (gmode0) io mux selects 14 1 ts_tte_stop 4 RR PI RR PO L31 PI L31 PO GX PI GX PO L30 PI L30 PO dut selects z_rr_dut IO COP z_l3b1_dut attention lines z_gx_dut td_core z_io_dut z_l3b0_dut Error 4 Collection 10 triggers (a and b) trace_run trace_run 1 20 ECC e_ecc_dut s_isu_dut f_fpu_dut i_ifu_dut x_fxu0_dut d_idu_dut l_slb_dut l_l1d_dut v_l1_dut ISU FPU IFU twd_wire_dut WIRED FXU0 IDU t_lbao.vhdl trc_result_chk.vhdl ta_trace.vhdl 10 x trace array/controls 256 SLB t_rbao.vhdl L1D L2 3 6 SCom Mode Reg (gmode1) SCom Mode Reg (gmode2) 103 fuses PO PI result controls error enable ttc_test_engine 1 1 Test Engine 1

6 fxu Testchip Die Photo Pattern Generator Noise Generators(3) isu wire dut ifu fpu idu l1d l2 Result Checker Trace Function Noise(3) Cop Noise(2) Noise (2) Tech. Exp. Tech. Exp. Tech. Exp. Noise Generators (1)

7 Test Chip Infrastructure Logic On chip tester 640 bit wide, 16 cycle deep vector generation and compare Vector ordering, selection, and loop control is programmable Cycle accurate result compare Random pattern generation mode with MISER Noise generation Cycle by cycle programmable noise generation Chip contains 384 noise generation macro's Each macro noise amplitude and signature is programmable Each cycle noise generator macros can dissipate a total of 0-100W Chip interface, debug infrastructure and test Chip accessed and programmed using product level support processor Manufacturing level test infrastructure implemented On-chip logic analyzer implemented for debug purposes Product level clock controls implemented

8 Technology CMOS 8S Technology 0.18 micron general lithography Silicon on insulator substrate 7 layers of metal, all Cu SRAM cell size: 4.23 sq microns Vdd = 1.5V Package Technology Glass substrate No thin film required > mil C4 chip to substrate connections C4 connections on an 8mil pitch

9 Circuit design verification Clocks High frequency PLL design compared to low jitter reference source On chip clock distribution latency and skew measured I/O Elastic and non-elastic I/O implemented and measured Performance of both I/O types "chip" limited Arrays L1, L2 and SLB implemented and measured The performance and density critical L2 cache design is solid Power/Noise experiments Noise amplitude measured under several different current excitations Package impedance empirically determined for full GHz bandwidth

10 Clock source experiment Ref clk in PLL Clock Distr. Clock out Ref clk out Bypass 800 MHz Clock Jitter No Noise Noise Group 1 CLOCK OUT W/BYPASS CLOCK OUT W/PLL REF CLK OUT W/BYPASS Noise Group 2 Noise Group

11 Measured Clock Skew Volts 70 ps skew (worst chip) 26 points probed Time (ps)

12 I/O Test Chip contains product like I/O architecture Approximately 800 elastic I/O signals Approximately 1400 synchronous I/O Elastic I/O performance Voltage A5 Pattern OF Pattern Synchronous I/O performance Voltage No Noise FFFFFFFF FFFF0000 F

13 L2 Cache Test Results L2 cache macro: 2 cycle access latency Row and column redundancy Array efficiency > 75% Includes ABIST Wafer/Chip MAX ABIST FREQ (MHz) VDD (V) CHUCK TEMP (deg C) FY/4, FY/7, FY/7, PY/5,

14 Measured Noise Results - Time Domain FFFF0000_all - PLL FFFFFFFF_all - PLL P-P Noise (mv) P-P Noise (mv) Frequency (MHz) Frequency (MHz) IDC 16 c4 cap No IDC 16 c4 cap No IDC 8 c4 cap No IDC 1 c4 cap No IDC No c4 cap 4 IDC 16 c4 cap No IDC 16 c4 cap No IDC 8 c4 cap No IDC 1 c4 cap

15 Measured Noise Results - Freq. Domain " Impedance " Impedance vs Frequency 4 IDC 16 c4 Caps No IDC, C4 caps Frequency

16 Voltage Schmoo ecc fxu200 ifu301 ifur1 isu2 idu slb1 fpumax wire V 1.3 V 1.5 V 1.6 V 1.8 V 2.0 V 2.2 V

17 Temperature Schmoo ecc fxu200 ifu301 ifur1 isu2 idu slb1 fpumax wire C 30 0C 80 0C 100 0C

18 Noise Schmoo ecc fxu200 ifu301 isu2 idu slb1 l1d fpumax wire W 60A Delta I (2) 60A Delta I (1) 105W 90W 45W

19 Summary We have demonstrated that the POWER4 Clock, I/O, array and power delivery designs support GHz operation Significant portions of the POWER4 product design have been implemented and tested The POWER4 service processor interface, manufacturing test and debug design has been implemented and tested The POWER4 design team has built a product like chip utilizing the product design tools and methodology