Radiation Tolerant FPGA Update

Transcription

1 Radiation Tolerant FPGA Update Ken O Neill Director of Marketing, Space and Aviation Microsemi SOC Group MRQW January 28, Microsemi Corporation.. 1

2 Agenda Current Status In-Service Radiation Tolerant FPGAs Next-Generation FPGA for Space Applications Qualification Plans Conclusion and Next Steps 2014 Microsemi Corporation. 2

3 In-Service RT FPGAs Update RTSX-SU Over 2,000 SEU-hardened flip flops EAR controlled, no longer ITAR Flight heritage since 2005 RTAX-S/SL/DSP Over 20,000 SEU-hardened flip flops Over 500kbits on-board SRAM Up to 120 multiply-accumulate blocks EAR controlled, no longer ITAR Flight heritage since 2007 Mars Reconnaissance Orbiter RTSX-SU on board (2005) Cosmo Skymed 1 4 RTAX on board (2007) RT ProASIC3 First Flash-based FPGA in space Reprogrammable and non-volatile EAR controlled, no longer ITAR Now QML class Q qualified NASA IRIS RT ProASIC3 on board (2013)

4 TM Next Generation Radiation-Tolerant FPGAs 2014 Microsemi Corporation..

5 RT FPGAs Migrating to High Speed Processing Logic Density 150 KLE 20 KLE RTAX-S / DSP Command and Control Medium Speed Processing High Speed Processing 150 KLE 5 Mbit SRAM 126 GMults / second 75 Gbit / second SERDES bandwidth 9 KLE RT ProASIC3 2 KLE RTSX-SU Frequency of Operation 2014 Microsemi Corporation. 5

6 Next Generation Space FPGAs Designed for high-bandwidth data processing in payload applications Abundant high-performance programmable logic fabric Embedded high speed multiply-accumulate blocks Ample on-board memory with fast access time, two block sizes High performance I/Os SERDES, LVDS, DDR2, Based on 65nm Flash low power process Naturally resistant to configuration upsets Non-volatile configuration live at power-up, no external boot memory needed Low static power RTG4 radiation enhanced for GEO and deep space Total ionizing dose, Single event effects, Latch-up immunity 2015 Microsemi Corporation.. 6

7 RTG4 Family Resources RT4G075 RT4G150 RT4G200 LUT4 + TMR/SET FF 77, , ,896 User IO (non-serdes) RAM24K Blocks uram1.5k Blocks RAM Mbits UPROM Kbits x18 Multiply-Accumulate Blocks SERDES lanes DDR2/3 SDRAM Controller (with ECC) 2x32 2x32 2x32 Globals PLLs (Rad Tolerant) Spacewire Clock & Data Recovery Circuits PCI Express Endpoints Packages CG1432 CG1657 CG Microsemi Corporation. 7

8 Radiation Specifications Total Dose > 100 KRad TID Single Event Effects No configuration failures (to be tested to > 110 MeV-cm 2 /mg) No single event latch-up (to be tested to > 110 MeV-cm 2 /mg) Mitigation for single event upsets Flip-flops with TMR and asynchronous self-correction (LET TH > 37 MeV-cm 2 /mg) Flip-flops in the logic fabric Flip-flops in embedded features Mathblocks etc On-chip SRAM (RAM24K and uram1.5k) Built-in EDAC 1E-10 errors/bit-day, GEO solar min Mitigation of single event transients Logic cells hardened with SET filter SET filter can be individually enabled / disabled for higher performance Target 1E-8 errors/bit-day, GEO solar min 2015 Microsemi Corporation.. 8

9 TID Mitigation in RTG4 Flash FPGAs Traditional Sense-Switch interconnect V T changes as device accumulates TID Results in T PD increase Example RT ProASIC3 has 10% T PD degradation at around 30Krad RTG4 TID - Tolerant interconnect Accumulation of TID causes V T changes in PFG and NFG floating-gate devices However, interconnect pass transistor stays strongly turned on as long as PFG is stronger than NFG Minimal change in T PD with accumulated TID to > 100Krad 2015 Microsemi Corporation.. 9

10 RT4G150 Device Floorplan 2 CCC 2 PLL DDR CALIB CCC -EIPS Serial Sub-system EIP-Clusters CCC -EIPS 2 CCC 2 PLL DDR CALIB SERDES, PCS, PCI-Express Logic Cells Mathblocks DDRIOs Bank L1 MSIODs Bank L2 FDDR Controller IIP (LSRAM, usram, Math) IIP (LSRAM, usram, Math) Clock VS IIP (LSRAM, usram, Math) IIP-Clusters Clock HS IIP (LSRAM, usram, Math) Clock VS IIP (LSRAM, usram, Math) IIP (LSRAM, usram, Math) Factory Segment and User Segment BL ACCESS FDDR Controller DDRIOs Bank R1 HVGEN MSIODs Bank R2 SDRAM DDRx Controller Block RAM (24Kb) μram (1.5Kb) MSIODs Bank L3 2 CCC 2 PLL CCC -EIPS MSIOs Bank B1 Clock VS IIP-Clusters IO-Clusters uproms WL ACCESS MSIOs Bank B2 Clock VS uprom- EIPS MSIOs Bank B3 CCC -EIPS Bank J1 JTAG and SPI pins RTG4 Control MSIODs Bank R3 2 CCC 2 PLL PLL and CCC 2015 Microsemi Corporation. 10

11 RTG4 Logic Module TMR Protected Simplified Diagram Dedicated STMR Flip-flop to enable efficient TMR hardening With enable, global asynchronous set/reset, and local synchronous set/reset Fast carry chain to complement Mathblock performance Arithmetic functions (add/subtract) Target 300 MHz for 32-bit functions (no SET filter) Target 250 MHz for 32-bit function (SET filter deployed) Industry standard LUT4 for efficient synthesis High utilization LUT4 and flip-flop in same module can be used independently Hierarchical routing architecture enables >95% module utilization 2015 Microsemi Corporation. 11

12 RTG4 Mathblock A[17:0] D ADD_SUB EN B[17:0] D + X D OVFL / CO S N [43:0] EN D[43:0] EN C[43:0] D SHIFT17 D >> 17 EN EN SEL_CASC S N-1 [43:0] 18 x 18 multiplier with advanced accumulate New 3-input adder function: (C + D) +/- (A * B) High performance for signal processing throughput 250 MHz with SET mitigation 300 MHz without SET mitigation Optional SEU-protected registers on inputs and outputs (including C input) 2015 Microsemi Corporation. 12

13 RTG4 Memory Blocks Radiation Tolerant Resistant to multi-bit upset Built-in optional EDAC (SECDED) LSRAM up to 24 KBit Dual-port and two-port options High performance synchronous operation Example usage Large FFT memory uram up to 1.5 KBit Three Port Memory Synchronous Write Port Two Asynchronous or Synchronous Read Ports Example usage Folded FIR filters and FFT twiddle factors Mixed port sizes Write and read port sizes can be different 300 MHz performance CLKA ADDRA[ ] WDATAA[17:0] WENA CLKB ADDRB[ ] WDATAB[17:0] WENB WCLK WADDR[ ] WDATA[17:0] WEN RCLKA RADDRA[ ] RENA RCLKB RADDRB[ ] RENB RAM24K uram1.5k RDATAA[17:0] ECC_STATA RDATAB[17:0] ECC_STATB RDATAA[17:0] ECC_STATA RDATAB[17:0] ECC_STATB 2015 Microsemi Corporation. 13

14 General Purpose IO Single ended standards LVCMOS from 1.2V to 3.3V LVTTL PCI Voltage reference standards (600+ Mbps) Includes on-chip termination SSTL2, SSTL18 and SSTL15 For DDR2/DDR3 SDRAM memories HSTL18 and HSTL15 For SRAM memories Differential I/O standards Includes on-chip termination True LVDS (600+ Mbps) Mini-LVDS, M-LVDS, RSDS, LVPECL 2015 Microsemi Corporation. 14

15 SpaceWire Hardened Clock Recovery Selected from pad_ccc_clk<3:0> Data Strobe D MUX S MUX dmux#_out smux#_out Delay Cell rxclk<#> To Global Clock Network Rx Recovery sel_rx_#<3:2> sel_rx_#<1:0> del_sel<4:0> Data and Strobe can connect to LVDS or LVTTL input pins Optional Single Event Transient filtering 2015 Microsemi Corporation. 15

16 3.125Gbps SERDES PMA Based on PCIe Gen 1 PHY RT Performance = Gbps Up to eight x4 units PCI Express Protocol x1, x2, x4 64-bit AXI /AHB PCI Express Interface 4 X16 PIPE 8B/10B Encoding / Decoding PCS Programmable Logic TXDn RXDn 1 PMA 4 x 20-bit EPCS SRIO Or Custom Protocol Serializer / Deserializer Clock Recovery XAUI Bridge XGMII Or Custom Protocol <= 3.125GHz <= 156MHz 2015 Microsemi Corporation. 16

17 Performance Summary General purpose logic 250 MHz system performance with SET mitigation deployed 300 MHz system performance without SET mitigation 300 MHz DSP support performance (adders, delays, etc.) Mathblock 250 MHz pipelined performance with SET mitigation deployed 300 MHz pipelined performance without SET mitigation RAM18K and uram1k > 300 MHz IO > 600 Mbps LVDS and 667 Mbps DDRx SDRAM data SERDES to Gbps Overall 250 MHz general system performance with SET mitigation deployed 300 MHz signal processing performance without SET mitigation 2015 Microsemi Corporation. 17

18 RTG4 Packaging Summary Flip chip assembly Hermetically-sealed cavity Internally-mounted BME decoupling capacitors Thermal adhesive between die and seal lid (passed RGA <5,000ppm, passed outgas to NASA spec) BME decoupling capacitors placed inside Kovar Lid RTG4 Die Under fill (passed RGA <5,000ppm, passed outgas to NASA spec) 2015 Microsemi Corporation. 18

19 RTG4 Product Availability RT devices for space flight applications Initial device: RT4G150 Early access to software and documents via Lead Customer Program: NOW Sample RT4G150 silicon: March 2015 RT4G150 development kit: April 2015 Mil Std 883 class B flight units: 1Q CY2016 QML class Q qualification: 4Q CY2016 QML class V qualification: 2017 RTG4 Lead Customer Program Start product evaluation and provide feedback Early access software: NOW RTG4 user guides: NOW Power calculator: NOW Open to new participants send to RTG4_LCP@microsemi.com 2015 Microsemi Corporation. 19

20 Qualification Plans Mil Std 883 Class B qualification Starts 4 th quarter, CY2015 Completes 1 st quarter, CY2016 Qualification will use RT4G150 in CG1657 packages 3 wafer lots 3 assembly lots 1,000 hour HTOL QML class Q qualification Technology insertion package currently in preparation phase Intent is to achieve QML-Q by end of CY2016 QML class V qualification It is our intention to achieve QML class V Working with DLA, SMC / Aerospace, NASA, JPL to ensure requirements are clear and understood 2015 Microsemi Corporation.. 20

21 RTG4 Conclusions and Next Steps Non-volatile RT FPGA for payload data processing High density, high performance, low power RTG4 FPGA Lead customer program with software access NOW Sample RT4G150 silicon: March 2015 RT4G150 development kit: April 2015 Mil Std 883 class B flight units: 1Q CY2016 QML class Q qualification: 4Q CY2016 Next steps Mil Std 883 class B qualification: 1Q CY2016 QML class Q qualification: 4Q CY2016 QML class V qualification: Microsemi Corporation. 21

22 Microsemi Space Forum Detailed discussions on Microsemi space products discrete, power, RF, ASIC, FPGA, timing Space product roadmap Design tips and tricks Qualification and reliability updates Radiation testing results and mitigation strategies Package development and roadmap Development and verification tools Downloads at Next events June 2015 USA (Los Angeles, Washington DC area) June 2015 Europe (Noordwijk, Netherlands) August 2015 India (Bangalore, Ahmedabad) 2015 Microsemi Corporation. 22