Current status of SOI / MPU and ASIC development for space

Transcription

1 The 23rd Microelectronics Workshop Current status of SOI / MPU and ASIC development for space Nov. 11 th 2010 Electronic Devices and Materials Group Aerospace Research and Development Directorate, JAXA Hiroyuki SHINDOU shindou.hiroyuki@jaxa.jp

2 Development history of MPU/ASIC JAXA has developed LSIs with the latest technology for commercial market. 4k/10k G/A (2µm rule) 8/16bit MPU k G/A (1µm rule) 32bit MPU (H32/V70) M G/A (0.35µm rule) 64bit MPU (25MHz) 2000 Year 4M gate Standard cell (0.18µm rule) 64bit MPU (200MHz) >4M gate Standard cell (0.15µm-SOI) 64bit MPU (>300MHz) 2010 For <0.18µm technology, SEE*s are main concern for LSIs for space applications. FD-SOI** is attractive for space because of its SEE hardness as compared with bulk technology. *Single Event Effect **Fully depleted Silicon on insulator 1

3 Oki 0.15um FD-SOI Structure & Process Process parameters of 0.15µm FD-SOI Gate length [µm] 0.15 Gate oxide [nm] 2.5 SOI thickness [nm] 40 BOX thickness [nm] 145 Up to 6 metal is available Low Leakage (LL) I off < 2E-12 A/um Less floating body effect compared with PD STI (Shallow Trench Isolation) is applied. RHBD* techniques JAXA/HIREC developed is applied for space products. (MPU, ASIC, FPGA etc.) *Radiation Hardness By Design methodology. 2

4 Basic concept of RHBD 1.0 A Y Redundant Tr Pairs RHBD Inverter Error X-Section [µm 2 /bit] Ar 対策なし ( リファレンス ) Conventional 対策あり ( エラーなし 上限値 ) RHBD Inverter Kr Xe LET [MeV/(mg/cm 2 )] The redundant transistor pairs completely prevent the SET* pulse generations on the output terminal. This concept can be easily extended for any logic gates and circuits. *SET: Single Event Transient 3

5 Topics 1 SOI MPU development 4

6 Milestone (HR5000S) JFY2008 Synthesis & layout JFY2009 JFY2010 Chip manufacturing Tape out Assembly & evaluation Minor design modification 1 st Si Chip manufacturing & evaluation Qualification will be completed this month. QT 2 nd Si Nov The 22nd Microelectronics Tsukuba 5

7 JAXA qualified 64bit MPU (HR5000) MPU core (MIPS64 5kf) 64bit RISC (with FPU) 200MHz (320MIPS) 32kB(Inst.)+32kB(data) cache CPU Bus UART DMA Timer CPU Bus Slave PCI Host Bridge Interrupt Controller Memory Controller PCI Bus MIPS64 5kf architecture with on-chip peripherals. 0.18µm commercial CMOS process. 200MHz operation (320MIPS) JAXA qualified. (Mar. 2007) 6

8 Key feature of SOI MPU (HR5000S) HR5000S (SOI version of HR bit MPU) MIPS64 5kf architecture with on-chip peripherals. 0.15µm FD-SOI CMOS process. 50MHz operation* 304 pin QFP package. RHBD techniques is applied to both the logical circuit and the cache memory to improve SEU tolerance. Logic : >64 [MeV/(mg/cm 2 )] Cache :>64 [MeV/(mg/cm 2 )] *PLL circuit for space use is not applied. Now under development. 7

9 HR5000S circuit layout 5mm D-Cache Tag RAM I-Cache Tag RAM D-Cache Data RAM D/I Cache Way RAM I-Cache Data RAM MPU Logic cells 10mm The chip size was adjusted to 5mm x 10mm though RHBD was applied to the cache memory. 8

10 HR5000 vs HR5000S (Area & Power) 1.0 HR5000 HR5000S I-Cache Data RAM I-Cache Tag RAM I I Cache Way RAM 0.0 Area Power 50MHz D Cache Way RAM D-Cache MPU Logic Tag RAM cells HR um CMOS 1.8V / 3.3V Relative value comparison between HR5000 and HR5000S D-Cache Data RAM HR5000S 0.15um FD-SOI 1.5V / 3.3V 9

11 SEE test results LET [MeV/(mg/cm 2 )] Test Program Fluence [Particles/cm 2 ] MPU evaluation board 25 [MHz] operation Test programs were continuously executed while doing the irradiation to monitor anomaly events (Cache / Logic). Heavy-Ion Irradiation* Test Results for MPU evaluation board # of Error (Cache) # of Error (Logic) 0.6 Whetstone 1.11e # of SEL Whetstone 1.05e Quick sort 1.16e Whetstone 1.14e Quick sort 1.06e *Test was performed at Japan Atomic Energy Agency (JAEA), Japan 10

12 Predicted SEU rate on orbit Predicted SEU rate in radiation environment of SSO and GEO (Calculated from the Irradiation test data for the cell library.) Logic (F/F) SRAM Total LET th [MeV/(mg/cm 2 )] >64.0 >64.0 Cross Section [cm 2 /bit] < 2.1E-11 < 3.0E-12 # of cells used for HR5000S Predicted SEU rate (Case 1 : 692 km, deg. Sun-synchronous orbit) Solar Min. [SEUs/device/day] < 4.3E-15 < 2.7E-15 < 7.0E-15 Solar Max. [SEUs/device/day] < 2.1E-15 < 1.4E-15 < 3.5E-15 Predicted SEU rate (Case 2 : 36,000 km, 0.0 deg. Geostationary orbit) Solar Min. [SEUs/device/day] < 2.0E-14 < 1.3E-14 < 3.3E-14 Solar Max. [SEUs/device/day] < 1.0E-14 < 6.4E-15 < 7.4E-15 Excellent SEU tolerance! 11

13 Topics 2 SOI ASIC development 12

14 RHBD 0.15µm SOI-ASIC Characteristics Qualification will be completed this month. Process Design Kit (PDK) has already been released. Standard cells I/Os Supply voltage Stand-by power (2 input NAND) Delay (2 input NAND) Toggle frequency (D-F/F) - Low power type (Normal Vth) - High Speed type (Low Vth) Digital I/Os, PCI, LVDS 1.5V Core / 3.3V IO 42.3 pw (Low power type) pw (High speed type) 46.1 psec (Low power type) 36.9 psec (High speed type) GHz (Low power type) GHz (High speed type) 42 type of RHBD sequential logic cells, 293 type of combinational 25 degree C, 25 degree C, 1.5V 25 degree C, 1.5V Fanout=1 Usable gate 3,720 Kgate (@10x10 mm) Area utilization = 65% SEU/TID >64 [MeV/(mg/cm 2 )], 1kGy(Si) 13

15 SOI ASIC design status for space The evaluation of 7 kinds of ASIC designs is now in progress to achieve near future space missions. Design phase : 3 designs ES chip evaluation : 2 designs On-board evaluation : 2 designs A Y Redundant Tr Pairs RHBD Inverter (SET free) 0.15um SOI + RHBD 14

16 Summary Development of MPU based on 0.15um FD-SOI technology is in progress.qt will be finished soon. The evaluation of ASIC designs for space is now in progress. SOI technology with RHBD technique will become one of the important technologies to make sure the space mission succeed. 15