Using ModelSim in EDK:

Transcription

1 Using ModelSim in EDK: EDK supports two simulators, ModelSim and NCsim. In this tutorial ModelSim will be discussed. This tutorial will discuss how to setup the EDK and ISE libraries, in order for ModelSim to be able to simulate the project. The simulation flow will then be discussed, referring the various simulation files produced by the EDK tool. The testbench and its various components that the simulator uses will be discussed. Then finally simulating external memory will be discussed and the memory model needed to do so. Compiling the EDK and ISE simulation libraries using the wizard: Upon downloading the ModelSim, you will have to compile the EDK and ISE simulation libraries. There is a utility within EDK to compile the simulation libraries. In EDK, select Simulation -> Compile Simulation Libraries, this is seen below. This will compile both the EDK and ISE libraries. These libraries are large, so compilation will be time consuming, however, it is only needed after every major release install. The EDK Simulation flow: The simulator uses the VHDL or Verilog Hardware Description Language (HDL) models of your embedded hardware design. These system models are bases on processor and peripheral cores that are provided in the EDK simulation libraries and the underlying logic provided by the ISE simulation libraries. The simulation models are generated using XPS and SimGen. Firstly, you will have to tell the simulator where to find the simulation libraries. To do this, go to Edit -> Preferences within the XPS. In the Application Preferences window, specify your EDK and your ISE simulation library paths. 1

2 In this tutorial, the ModelSim simulation is used, the HDL language is VHDL, the behavioural simulation will be done and the template testbench will be created by the tools. To set this up go to Project -> Project options, and in the HDL and Simulation tab, Set this up as seen below: Note: For users that do not have both VHDL and Verilog ModelSim licences and wish to simulate a design containing, for example the MPMC which is in Verilog. To work around this issue un-select the Allow Mixed Language Behavioural Files in the HDL and Simulation tab above. This will create the Structural files (Netlist) for the MPMC; this will create an MPMC wrapper file in the simulation directory that can be used in the behavioural simulation. 2

3 Finally, SimGen is used to generate the models. To do this, go to Simulation -> Generate Simulation HDL Files seen below. Files of interest, generated by the tools: After the SimGen is run, this will create all the relevant HDL models into your project directory. The tool will also create a system_setup.do file. This file makes using the ModelSim easier as it defines macros and commands to load a design and automate the setup of signal displays for viewing. The system_setup.do file will call the system.do file. The system.do file contains all the pre-compiled library files that the simulator will in your simulation, this is denotes by the vmap command. To compile your top system HDL file and all the sub-module files such as MicroBlaze wrapper files, the vcom command is used. The system.do file will also call the system_init.do file, this file instantiates the BRAM with your software code. Finally, if the template testbench is selected this will create a testbench (system_tb.v) file in the simulation directory. This is described in the next section. Given that the tools generate all the relevant files a run.do file can be created. The run.do file will call all the relevant ModelSim commands. An example run.do file is seen below: do system_setup.do c w log -r /* run 30 us 3

4 The testbench tells the simulator what clock to use and how to set-up the reset correctly to match your hardware described in the MHS file. The testbench will also configure the software into the BRAM. The syntax between Verilog and VHDL for instantiating the software is different. To instantiate the software in Verilog the dut_conf () function is called. In VHDL, the configuration hierarchy must be specified an example of this is seen below: configuration top_conf of top_tb is for behavior for all: edk_project use configuration work.edk_project_conf; end for; end for; end top_conf; Modifying the Testbench to incorporate a Memory Model: As the testbench provided by the tool is just a template, this will have to be modified to suit specific simulation. In this section the testbench will be modified to simulate the external memory. In this tutorial the external memory is DDR2 SDRAM. In order to simulate the DDR2 SDRAM, the memory model HDL files must be source from Micron. You can obtain the part number of the memory for your memory from viewing the boards User Guide, for example the ML507 part number is Micron MT4HTF3264HY-53E. To obtain the model for this go to the Micron website; and enter the part number in the search box. Save the downloaded the memory model HDL files into your project directory. In the downloaded memory model folder the files of interest are the: ddr2.v ddr2_module.v ddr2_parameters.vh 4

5 This memory model must be instantiated into your testbench. This is seen below: ddr2_module ddr2_sodimm(.ck (fpga_0_ddr2_sdram_ddr2_ck_pin),.ck_n (fpga_0_ddr2_sdram_ddr2_ck_n_pin),.cke (fpga_0_ddr2_sdram_ddr2_cke_pin[0:0]),.s_n (fpga_0_ddr2_sdram_ddr2_cs_n_pin[0:0]),.ras_n (fpga_0_ddr2_sdram_ddr2_ras_n_pin),.cas_n (fpga_0_ddr2_sdram_ddr2_cas_n_pin),.we_n (fpga_0_ddr2_sdram_ddr2_we_n_pin),.ba (fpga_0_ddr2_sdram_ddr2_ba_pin),.addr (fpga_0_ddr2_sdram_ddr2_a_pin),.odt (fpga_0_ddr2_sdram_ddr2_odt_pin),.dqs (fpga_0_ddr2_sdram_ddr2_dqs),.dqs_n (fpga_0_ddr2_sdram_ddr2_dqs_n),.dq (fpga_0_ddr2_sdram_ddr2_dq) ); Note: There may be some port mis-matches between your project and the memory model. These adjustments will have to be made within the testbench. The next step is to modify the run.do file so that the memory model HDL files will be compiled, also some compile options are sent to the HDL file, such as device type, speed and data width, the updated run.do file is seen below: do system_setup.do c vlog +define+sg37e +define+x16 +define+sodimm../../512mb_ddr2/ddr2.v../../512mb_ddr2/ddr2_module.v vsim -novopt -t ps -L unisims_ver system_tb glbl w add wave -p ddr2_sodimm/* log -r /* run 150 us Line 3 will compile the ddr2.v and the ddr2_module.v files. The options passed to these files are the device size (sg37e), data width (x16), device type (SODIMM). This will differ for each memory model, be sure that this is correct for your memory device. This information can be obtained from the datasheet for each individual memory device. Line 4 will tell the simulator the precision of the simulation in this case ps (Pico seconds) and since some Verilog HDL is used, the Verilog unisim library must be compiled. The add wave p ddr2_sodimm/* will display all signals at the top level of the memory model. 5

6 The log r /* will simulate all back-end signals. Since the external memory is used, the simulation will need to be run for a bit longer and the memory controller will need time to calibrate. Finally, copy the ddr2_parameters.vh into the simulation directory folder. The simulator will use this file to determine the timing of the memory model. Now, Launch the ModelSim for the XPS. To do this go to Simulation -> Launch HDL Simulator. Once the Simulator is open type do run.do file to run the run.do file. 6