The 9S12 in Expanded Mode - External Ports Huang Chapter 14

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Godfrey Griffith
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1 The 9S2 in Epanded Mode - Eternal Ports Huang Chapter 4 Accessing Eternal Memory and Ports on the 9S2 in Epanded Mode In epanded mode, the 9S2 has a multipleed 6-bit address and data bus. With a 6-bit address bus, the 9S2 can access 2 6 = 65, 536 bytes o data With a 6-bit data bus, the 9S2 can access 6 bits (two bytes) in a single bus cycle In epanded mode, the 9S2 uses Port A and Port B as the multipleed address/data bus Timing is controlled by the E clock When the E clock is low, the 9S2 places the address on the multipleed bus Port A is used or address bits 5-8 Port B is used or address bits 7- When the E clock is high, the 9S2 uses the multipleed bus or data bus: Port A is used or the even byte Port B is used or the odd byte For eample, i accessing the siteen-bit word at address 4 (the bytes at addresses 4 and 4), Port A will access the byte at address 4, and Port B will access the byte at address 4. Simple Parallel Input Port We want a port which will read 8 bits o data rom the outside Such a port is similar to Port A or Port B when all pins are set up as input We need some hardware to drive the input data onto the data bus at the time the 9S2 needs it to be there to read it The hardware needs to keep the data o the bus at all other times so it doesn t interere with data rom other devices A tri-state buer can be used or this purpose A tri-state buer has three output states: logic high, logic low, and high impedance (high-z)

2 In high-z state it is like the buer is not connected to the output at all, so another device can drive the output a tri-state output acts like a switch when the switch is closed, the output logic level is the same as the input logic level, and when the switch is open, the buer does not change the logic level on the output pin A tri-state buer has a control input which, when active, drives the input logic levels onto the output pins, and when inactive, opens the switch. e e = e = (a) A tri-state buer (b) Equivalent circuit e Z Z e (c) Truth table (d) Implementation A Simple Parallel Input Port When should the tri-state buer be enabled to drive the data bus? The 9S2 will access the buer by reading rom an address. We must assign an address or the tri-state buer We must have hardware to demultiple the address rom the data, and to determine when the 9S2 is reading rom this address The 8-bit input will be connected to 8 bits o the 6-bit address/data bus o the 9S2 - I the address o the input is even, we need to connect the output o the buer to the even (high) byte o the bus, which is connected to AD5-8 (what was Port A) - I the address o the input is odd, we need to connect the output o the buer to the odd (low) byte o the bus, which is connected to AD7- (what was Port B) The 9S2 needs the data on the bus on the high-to-low transition o the E-clock

3 We must enable the tri-state buer when. The address o the buer is on the address bus 2. The 9S2 is reading rom this address 3. The 9S2 is reading the high byte i the address is even, or the low byte i the address is odd 4. E is high For eample, consider an input port at address 4 (an even address, or high byte): A Simple Parallel Output Port We want a port which will write 8 bits o data to the outside Such a port is similar to Port A or Port B when all pins are set up as output We need some hardware to latch the output data at the time the 9S2 puts the data on the data bus We can use a set o 8 D lip-lops to latch the data The D inputs will be connected to the data bus

4 The clock to latch the lip-lops should make its low-to-high transition when the 9S2 has the appropriate data on the bus The 9S2 will access the lip-lops by writing to an address. We must assign an address or the lip-lops We must have hardware to demultiple the address rom the data, and to determine when the 9S2 is writing to this address The 8-bit inputs o the D lip-lops will be connected to 8 bits o the 6-bit address/data bus o the 9S2 - I the address o the output is even, we need to connect the lip lop inputs to the even (high) byte o the bus, which is connected to AD5-8 (what was Port A) - I the address o the output is odd, we need to connect the lip lop inputs to the odd (low) byte o the bus, which is connected to AD7- (what was Port B) The hardware should latch the data on the high-to-low transition o the E-clock Our hardware should bring the clock o the lip-lops low when. The address o the lip-lops is on the address bus 2. The 9S2 is writing to this address 3. The 9S2 is writing the high byte i the address is even, or the low byte i the address is odd 4. E is high For eample, consider an output port at address 4 (an odd address, or low byte):

5 An Output Port Which Can Be Read Suppose we set up the 9S2 Port B or output, and we write a number to Port B When we read rom Port B, we will read back the number we wrote This is a useul diagnostic We can make our output port have this same perormance by connecting the output o the lip-lops back into the data bus through a tri-state buer We should enable this tri-state buer when the 9S2 is reading rom the address o the output port For eample, consider the output port at address 4:

6 Writing to address 4 will bring CS_W low. On the high to low transition o E, CS_W will go high, latching the data into the lip lops Reading rom address 4 will bring CS_R low This will drive the data rom the lip lops onto the data bus The HC2 will read the data on the lip lops on the high to low transition o the E clock

7 The RTL diagram o the Input-Output Port A simulation o the Input-Output Port

A Simple Parallel Input Port

308 Apr. 8, 2002 A Simple Parallel Input Port We want a port which will read 8 bits of data from the outside Such a port is similar to or Port B when all pins are set up as input We need some hardware