USE isplsi 1016EA FOR NEW COMMERCIAL & INDUSTRIAL DESIGNS

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1 isplsi 1 In-System Programmable High Deity PLD Features Functional Block Diagram HIGH-DENSITY PROGRMMBLE LOGIC High-Speed Global Interconnect PLD Gates 3 I/O Pi, Four Dedicated Inputs 9 Registers Wide Input Gating for Fast Counters, State Machines, ddress Decoders, etc. Small Logic Block Size for Random Logic Security Cell Prevents Unauthorized Copying HIGH PERFORMNCE E CMOS TECHNOLOGY fmax = 1 MHz Maximum Operating Frequency fmax = MHz for Industrial and Military/883 Devices tpd = Propagation Delay TTL Compatible Inputs and Outputs Electrically Erasable and Reprogrammable Non-Volatile E CMOS Technology % Tested IN-SYSTEM PROGRMMBLE In-System Programmable (ISP ) 5-Volt Only Increased Manufacturing Yields, Reduced Time-to- Market, and Improved Product Quality Reprogram Soldered Devices for Faster Debugging COMBINES ESE OF USE ND THE FST SYSTEM SPEED OF PLDs WITH THE DENSITY ND FLEX- IBILITY OF FIELD PROGRMMBLE GTE RRYS Complete Programmable Device Can Combine Glue Logic and Structured Desig Three Dedicated Clock Input Pi Synchronous and synchronous Clocks Flexible Pin Placement Optimized Global Routing Pool Provides Global Interconnectivity ispdesignexpert LOGIC COMPILER ND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRMMING Superior Quality of Results Tightly Integrated with Leading CE Vendor Tools Productivity Enhancing Timing nalyzer, Explore Tools, Timing Simulator and ispnlyzer PC and UNIX Platforms Output Routing Pool Description Logic rray Global Routing Pool (GRP) D Q D Q D Q D Q GLB B7 B B5 B4 B3 B B1 B CLK Output Routing Pool The isplsi 1 is a High-Deity Programmable Logic Device containing 9 Registers, 3 Universal I/O pi, four Dedicated Input pi, three Dedicated Clock Input pi and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The isplsi 1 features 5-Volt in-system programming and in-system diagnostic capabilities. It is the first device which offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the isplsi 1 device is the Generic Logic Block (GLB). The GLBs are labeled, 1.. B7 (see figure 1). There are a total of 1 GLBs in the isplsi 1 device. Each GLB has 18 inputs, a programmable ND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. ll of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. Copyright Lattice Semiconductor Corp. ll brand or product names are trademarks or registered trademarks of their respective holders. The specificatio and information herein are subject to change without notice. LTTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 9714, U.S.. ugust Tel. (53) 8-8; 1-8-LTTICE; FX (53) 8-855; 1_9 1

2 Specificatio isplsi 1 Functional Block Diagram Figure 1. isplsi 1 Functional Block Diagram I/O I/O 1 I/O I/O 3 I/O 4 I/O 5 I/O I/O 7 I/O 8 I/O 9 I/O I/O 11 I/O 1 I/O 13 I/O 14 I/O SDI/IN SDO/IN 1 ispen Input Bus Generic Logic Blocks (GLBs) Output Routing Pool (ORP) Megablock The device also has 3 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with 3-state control. dditionally, all outputs are polarity selectable, active high or active low. The signal levels are TTL compatible voltages and the output drivers can source 4 m or sink 8 m. Eight GLBs, 1 I/O cells, two dedicated inputs and one ORP are connected together to make a Megablock (see figure 1). The outputs of the eight GLBs are connected to a set of 1 universal I/O cells by the ORP. The isplsi 1 device contai two of these Megablocks Global Routing Pool (GRP) Y Y1/RESET* SCLK/Y Clock Distribution Network CLK CLK 1 CLK IOCLK IOCLK 1 IN 3 MODE/IN I/O 31 I/O 3 I/O 9 B7 B B5 B4 B3 B B1 B Output Routing Pool (ORP) lnput Bus *Note: Y1 and RESET are multiplexed on the same pin 139B(1a)-isp.eps I/O 8 I/O 7 I/O I/O 5 I/O 4 I/O 3 I/O I/O 1 I/O I/O 19 I/O 18 I/O 17 I/O 1 The GRP has as its inputs the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. ll of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the isplsi 1 device are selected using the Clock Distribution Network. Three dedicated clock pi (Y, Y1 and Y) are brought into the distribution network, and five clock outputs (CLK, CLK 1, CLK, IOCLK and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (B on the isplsi 1 device). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device.

3 Specificatio isplsi 1 bsolute Maximum Ratings 1 Supply Voltage V cc to +7.V Input Voltage pplied... - to V CC +1.V Off-State Output Voltage pplied... - to V CC +1.V Storage Temperature to C Case Temp. with Power pplied to 15 C Max. Junction Temp. (T J ) with Power pplied... C 1. Stresses above those listed under the bsolute Maximum Ratings may cause permanent damage to the device. Functional operation of the device at these or at any other conditio above those indicated in the operational sectio of this specification is not implied (while programming, follow the programming specificatio). DC Recommended Operating Conditio SYMBOL PRMETER MIN. MX. UNITS VCC VIL VIH Supply Voltage Input Low Voltage Input High Voltage Commercial Industrial Military/883 Capacitance (T =5 o C, f=1. MHz) T = C to +7 C T = -4 C to +85 C T C = -55 C to +15 C Vcc + 1 V V V Table - 5isp w/mil.eps SYMBOL PRMETER MXIMUM 1 UNITS TEST CONDITIONS C 1 Dedicated Input Capacitance Commercial/Industrial 8 pf V CC =5.V, V IN =.V Military pf V CC =5.V, V IN =.V C I/O and Clock Capacitance pf V CC =5.V, V I/O, V Y =.V 1. Guaranteed but not % tested. Data Retention Specificatio Data Retention Erase/Reprogram Cycles PRMETER MINIMUM MXIMUM UNITS Years Cycles Table - Table - 8B 3

4 Specificatio isplsi 1 Switching Test Conditio Input Pulse Levels GND to 3.V Input Rise and Fall Time 3 % to 9% Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load See figure 3-state levels are measured.5v from steady-state active level. Table - 3 Output Load Conditio (see figure ) Test Condition R1 R CL 47Ω 39Ω 35pF B ctive High 39Ω 35pF ctive Low 47Ω 39Ω 35pF ctive High to Z 39Ω 5pF C at V OH -.5V ctive Low to Z 47Ω 39Ω 5pF at V OL +.5V DC Electrical Characteristics Table - 4 Figure. Test Load Device Output Over Recommended Operating Conditio + 5V R1 R CL* *CL includes Test Fixture and Probe Capacitance. SYMBOL PRMETER CONDITION MIN. TYP. 3 MX. VOL VOH IIL IIH IIL-isp IIL-PU IOS 1 ICC,4 Output Low Voltage Output High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current isp Input Low Leakage Current I/O ctive Pull-Up Current Output Short Circuit Current Operating Power Supply Current I OL =8 m I OH =-4 m V V IN V IL (MX.) 3.5V V IN V CC V V IN V IL (MX.) V V IN V IL V CC = 5V, V OUT =.5V V IL =.5V, V IH = 3.V Commercial f TOGGLE = 1 MHz Industrial/Military 17 Test Point UNITS V V µ µ µ µ m m m 1. One output at a time for a maximum duration of one second. V out =.5V was selected to avoid test problems by tester ground degradation. Characterized but not % tested.. Measured using four 1-bit counters. 3. Typical values are at V CC = 5V and T = 5 o C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Coumption section of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum I CC. Table -7-1 w/mil 4

5 Specificatio isplsi 1 External Timing Parameters Over Recommended Operating Conditio PRMETER TEST 5 # DESCRIPTION UNITS COND. MIN. MX. MIN. MX. tpd1 tpd fmax (Int.) 1 3 Data Propagation Delay, 4PT bypass, ORP bypass Data Propagation Delay, Worst Case Path Clock Frequency with Internal Feedback MHz 1 fmax (Ext.) 4 Clock Frequency with External Feedback( MHz tsu + tco1) fmax (Tog.) 5 Clock Frequency, Max Toggle MHz tsu1 tco1 th1 tsu tco th tr1 trw1 ten tdis twh twl tsu5 th5 B C GLB Reg. Setup Time before Clock, 4PT bypass GLB Reg. Clock to Output Delay, ORP bypass GLB Reg. Hold Time after Clock, 4 PT bypass GLB Reg. Setup Time before Clock GLB Reg. Clock to Output Delay GLB Reg. Hold Time after Clock Ext. Reset Pin to Output Delay Ext. Reset Pulse Duration Input to Output Enable Input to Output Disable Ext. Sync. Clock Pulse Duration, High Ext. Sync. Clock Pulse Duration, Low I/O Reg. Setup Time before Ext. Sync. Clock (Y1, Y) I/O Reg. Hold Time after Ext. Sync. Clock (Y1, Y) Unless noted otherwise, all parameters use a GRP load of 4 GLBs, PTXOR path, ORP and Y clock.. Refer to Timing Model in this data sheet for further details. 3. Standard 1-Bit loadable counter using GRP feedback. 4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 5%. 5. Reference Switching Test Conditio Section. Table -3-1/1,9C 5

6 Specificatio isplsi 1 External Timing Parameters Over Recommended Operating Conditio PRMETER TEST 5 # DESCRIPTION UNITS COND. MIN. MX. MIN. MX. tpd1 tpd fmax (Int.) 1 3 Data Propagation Delay, 4PT bypass, ORP bypass Data Propagation Delay, Worst Case Path Clock Frequency with Internal Feedback MHz 1 fmax (Ext.) 4 Clock Frequency with External Feedback( MHz tsu + tco1) 5 38 fmax (Tog.) 5 Clock Frequency, Max Toggle 4 83 MHz tsu1 tco1 th1 tsu tco th tr1 trw1 ten tdis twh twl tsu5 th5 B C GLB Reg. Setup Time before Clock, 4PT bypass GLB Reg. Clock to Output Delay, ORP bypass GLB Reg. Hold Time after Clock, 4 PT bypass GLB Reg. Setup Time before Clock GLB Reg. Clock to Output Delay GLB Reg. Hold Time after Clock Ext. Reset Pin to Output Delay Ext. Reset Pulse Duration Input to Output Enable Input to Output Disable Ext. Sync. Clock Pulse Duration, High Ext. Sync. Clock Pulse Duration, Low I/O Reg. Setup Time before Ext. Sync. Clock (Y1, Y) I/O Reg. Hold Time after Ext. Sync. Clock (Y1, Y) Unless noted otherwise, all parameters use a GRP load of 4 GLBs, PTXOR path, ORP and Y clock.. Refer to Timing Model in this data sheet for further details. 3. Standard 1-Bit loadable counter using GRP feedback. 4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 5%. 5. Reference Switching Test Conditio Section. Table -3-1/8,C

7 Specificatio isplsi 1 Internal Timing Parameters 1 PRMETER Inputs tiobp tiolat tiosu tioh tioco tior tdin GRP tgrp1 tgrp4 tgrp8 tgrp1 tgrp1 GLB t4ptbp t1ptxor tptxor txoradj tgbp tgsu tgh tgco tgr tptre tptoe tptck ORP torp torpbp # DESCRIPTION I/O Register Bypass I/O Latch Delay I/O Register Setup Time before Clock I/O Register Hold Time after Clock I/O Register Clock to Out Delay I/O Register Reset to Out Delay Dedicated Input Delay GRP Delay, 1 GLB Load GRP Delay, 4 GLB Loads GRP Delay, 8 GLB Loads GRP Delay, 1 GLB Loads GRP Delay, 1 GLB Loads 4 Product Term Bypass Path Delay 1 Product Term/XOR Path Delay Product Term/XOR Path Delay XOR djacent Path Delay 3 GLB Register Bypass Delay GLB Register Setup Time before Clock GLB Register Hold Time after Clock GLB Register Clock to Output Delay GLB Register Reset to Output Delay GLB Product Term Reset to Register Delay GLB Product Term Output Enable to I/O Cell Delay GLB Product Term Clock Delay ORP Delay ORP Bypass Delay 1. Internal Timing Parameters are not tested and are for reference only.. Refer to Timing Model in this data sheet for further details. 3. The XOR djacent path can only be used by Hard Macros UNITS MIN. MX. MIN. MX

8 Specificatio isplsi 1 Internal Timing Parameters 1 PRMETER Outputs tob toen todis Clocks tgy tgy1/ tgcp tioy1/ tiocp Global Reset tgr # DESCRIPTION Output Buffer Delay I/O Cell OE to Output Enabled I/O Cell OE to Output Disabled Clock Delay, Y to Global GLB Clock Line (Ref. clock) Clock Delay, Y1 or Y to Global GLB Clock Line Clock Delay, Clock GLB to Global GLB Clock Line Clock Delay, Y1 or Y to I/O Cell Global Clock Line Clock Delay, Clock GLB to I/O Cell Global Clock Line Global Reset to GLB and I/O Registers 1. Internal Timing Parameters are not tested and are for reference only.. Refer to Timing Model in this data sheet for further details UNITS MIN. MX. MIN. MX

9 Specificatio isplsi 1 Internal Timing Parameters 1 PRMETER Inputs tiobp tiolat tiosu tioh tioco tior tdin GRP tgrp1 tgrp4 tgrp8 tgrp1 tgrp1 GLB t4ptbp t1ptxor tptxor txoradj tgbp tgsu tgh tgco tgr tptre tptoe tptck ORP torp torpbp # DESCRIPTION I/O Register Bypass I/O Latch Delay I/O Register Setup Time before Clock I/O Register Hold Time after Clock I/O Register Clock to Out Delay I/O Register Reset to Out Delay Dedicated Input Delay GRP Delay, 1 GLB Load GRP Delay, 4 GLB Loads GRP Delay, 8 GLB Loads GRP Delay, 1 GLB Loads GRP Delay, 1 GLB Loads 4 Product Term Bypass Path Delay 1 Product Term/XOR Path Delay Product Term/XOR Path Delay XOR djacent Path Delay 3 GLB Register Bypass Delay GLB Register Setup Time before Clock GLB Register Hold Time after Clock GLB Register Clock to Output Delay GLB Register Reset to Output Delay GLB Product Term Reset to Register Delay GLB Product Term Output Enable to I/O Cell Delay GLB Product Term Clock Delay ORP Delay ORP Bypass Delay -8 - UNITS MIN. MX. MIN. MX. 1. Internal Timing Parameters are not tested and are for reference only.. Refer to Timing Model in this data sheet for further details. 3. The XOR djacent path can only be used by Hard Macros

10 Specificatio isplsi 1 Internal Timing Parameters 1 PRMETER Outputs tob toen todis Clocks tgy tgy1/ tgcp tioy1/ tiocp Global Reset tgr # DESCRIPTION Output Buffer Delay I/O Cell OE to Output Enabled I/O Cell OE to Output Disabled Clock Delay, Y to Global GLB Clock Line (Ref. clock) Clock Delay, Y1 or Y to Global GLB Clock Line Clock Delay, Clock GLB to Global GLB Clock Line Clock Delay, Y1 or Y to I/O Cell Global Clock Line Clock Delay, Clock GLB to I/O Cell Global Clock Line Global Reset to GLB and I/O Registers 1. Internal Timing Parameters are not tested and are for reference only.. Refer to Timing Model in this data sheet for further details UNITS MIN. MX. MIN. MX

11 Specificatio isplsi 1 isplsi 1 Timing Model I/O Cell GRP GLB ORP I/O Cell Feedback Ded. In I/O Pin (Input) Reset Y1, Y #55 # I/O Reg Bypass # Input GRP D Register Q Loading Delay RST #1-5 #7, 9, 3, 31, 3 GRP 4 4 PT Bypass GLB Reg Bypass ORP Bypass #8 #33 Clock Distribution #51, 5, 53, 54 #5 PT XOR Delays #34, 35, 3 #55 Control RE PTs OE #4, 43, CK 44 Derivatio of tsu, th and tco from the Product Term Clock 1 GLB Reg Delay D Q RST #38, 39, 4, 41 tsu = Logic + Reg su - Clock (min) = (tiobp + tgrp4 + tptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)) = (# + #8 + #35) + (#38) - (# + #8 + #44) 5.5 = ( ) + (1.) - ( ) th = Clock (max) + Reg h - Logic = (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + tptxor) = (# + #8 + #44) + (#39) - (# + #8 + #35) 3. = ( ) + (3.5) - ( ) tco = Clock (max) + Reg co + Output = (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) = (# + #8 + #44) + (#4) + (#45 + #47) 1. = ( ) + (1.5) + ( + ) Derivatio of tsu, th and tco from the Clock GLB 1 tsu = Logic + Reg su - Clock (min) = (tiobp + tgrp4 + tptxor) + (tgsu) - (tgy(min) + tgco + tgcp(min)) = (# + #8 + #35) + (#38) - (#5 + #4 + #5) 5. = ( ) + (1.) - ( ) th = Clock (max) + Reg h - Logic ORP Delay = (tgy(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + tptxor) = (#5 + #4 + #5) + (#39) - (# + #8 + #35) 3.5 = ( ) + (3.5) - ( ) tco = Clock (max) + Reg co + Output = (tgy(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) = (#5 + #4 + #5) + (#4) + (#45 + #47) 1.5 = ( ) + (1.5) + ( + ) #37 #4 #45 #47 I/O Pin (Output) #48, Calculatio are based upon timing specificatio for the isplsi

12 Specificatio isplsi 1 Maximum GRP Delay vs GLB Loads isplsi 1- GRP Delay () Power Coumption GLB Loads Figure 3. Typical Device Power Coumption vs fmax ICC (m) isplsi 1-8 isplsi 1-9/ isp.eps Power coumption in the isplsi 1 device depends on two primary factors: the speed at which the device is operating, and the number of Product Terms used. Figure 3 shows the relatiohip between power and operating speed. isplsi 1 fmax (MHz) 8 Notes: Configuration of Four 1-bit Counters Typical Current at 5V, 5ßC 9 1 ICC can be estimated for the isplsi 1 using the following equation: ICC = 31 + (# of PTs *.45) + (# of nets * Max. freq *.9) where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max. freq = Highest Clock Frequency to the device The ICC estimate is based on typical conditio (VCC = 5.V, room temperature) and an assumption of GLB loads on average exists. These values are for estimates only. Since the value of ICC is seitive to operating conditio and the program in the device, the actual ICC should be verified. 1

13 Specificatio isplsi 1 Pin Description NME PLCC PIN NUMBERS TQFP PIN NUMBERS I/O - I/O 3, 1, 17, 18, 9,, 11, 1,, 1, 17, 18, I/O 4 - I/O 7 19,, 1,, 13, 14,, 1, 19,, 1,, I/O 8 - I/O 11 5,, 7, 8, 19,, 1,, 5,, 7, 8, I/O 1 - I/O 9, 3, 31, 3, 3, 4, 5,, 9, 3, 31, 3, I/O 1 - I/O 19 37, 38, 39, 4, 31, 3, 33, 34, 37, 38, 39, 4, I/O - I/O 3 41, 4, 43, 44, 35, 3, 37, 38, 41, 4, 43, 44, I/O 4 - I/O 7 3, 4, 5,, 41, 4, 43, 44, 3, 4, 5,, I/O 8 - I/O 31 7, 8, 9, 1,, 3, 4 7, 8, 9, IN 3 4 ispen SDI/IN MODE/IN SDO/IN SCLK/Y Y Y1/RESET JLCC PIN NUMBERS DESCRIPTION Input/Output Pi - These are the general purpose I/O pi used by the logic array. Dedicated input pi to the device. Input Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK optio become active. Input This pin performs two functio. It is a dedicated input pin when ispen is logic high. When ispen is logic low, it functio as an input pin to load programming data into the device. SDI/IN also is used as one of the two control pi for the isp state machine. Input This pin performs two functio. It is a dedicated input pin when ispen is logic high. When ispen is logic low, it functio as a pin to control the operation of the isp state machine. Input/Output This pin performs two functio. It is a dedicated input pin when ispen is logic high. When ispen is logic low, it functio as an output pin to read serial shift register data. Input This pin performs two functio. It is a dedicated clock input when ispen is logic high. This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device. When ispen is logic low, it functio as a clock pin for the Serial Shift Register. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. This pin performs two functio: Dedicated clock input. This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device. ctive Low () Reset pin which resets all of the GLB and I/O registers in the device. GND 1, 3 17, 39 1, 3 VCC 1, 34, 8 1, 34 Ground (GND) V CC 1. Pi have dual function capability. Table - C-1-isp 13

14 Specificatio isplsi 1 Pin Configuration isplsi 1 44-Pin PLCC Pinout Diagram I/O 7 I/O I/O 5 I/O 4 IN 3 GND I/O 3 I/O I/O 1 I/O I/O I/O 3 isplsi 1 44-Pin TQFP Pinout Diagram I/O 8 I/O 9 I/O 3 I/O Y 11 VCC 1 isplsi 1 ispen 1 SDI/IN I/O I/O 1 I/O Top View I/O 4 I/O 5 I/O I/O 7 GND 1 SDO/IN 1 1. Pi have dual function capability. I/O 8 I/O 9 I/O 3 I/O 31 Y VCC I/O 8 I/O 9 I/O I/O 11 I/O 18 I/O 17 I/O 1 IN /MODE 1 Y1/RESET VCC Y/SCLK 1 I/O I/O 14 I/O 13 I/O 1 ispen 1 SDI/IN I/O I/O 1 I/O I/O 7 I/O I/O 5 I/O 4 IN 3 GND I/O 3 I/O I/O 1 isplsi 1 Top View I/O I/O I/O 18 I/O isp1 I/O 1 IN/MODE 1 Y1/RESET VCC Y/SCLK 1 I/O I/O 14 I/O 13 I/O I/O 3 I/O 4 I/O 5 I/O I/O 7 GND 1 SDO/IN 1 I/O 8 I/O 9 I/O I/O Pi have dual function capability /TQFP 14

15 Specificatio isplsi 1 Pin Configuration isplsi 1 44-Pin JLCC Pinout Diagram I/O 7 I/O I/O 5 I/O 4 IN 3 GND I/O 3 I/O I/O 1 I/O I/O 19 I/O 8 I/O 9 I/O 3 I/O 31 Y VCC ispen 1 SDI/IN I/O I/O 1 I/O I/O 3 isplsi 1/ I/O 4 I/O 5 I/O Top View I/O 7 GND 1 SDO/IN 1 1. Pi have dual function capability. I/O 8 I/O 9 I/O I/O 11 I/O 18 I/O 17 I/O 1 IN /MODE 1 Y1/RESET VCC Y/SCLK 1 I/O I/O 14 I/O 13 I/O isp/JLCC

16 Specificatio isplsi 1 Part Number Description isplsi 1 XXX X XXX X Device Family isplsi Device Number Speed 1 = 1 MHz fmax 9 = 9 MHz fmax 8 = 8 MHz fmax = MHz fmax Ordering Information Family isplsi Family isplsi Grade Blank = Commercial I = Industrial /883 = 883 Military Process Package J = PLCC T44 = TQFP H = JLCC Power L = Low 1-8B-isp1 fmax (MHz) tpd () Ordering Number Package 9 1 COMMERCIL 1 isplsi 1-1LJ 44-Pin PLCC isplsi 1-9LJ 44-Pin PLCC 9 1 isplsi 1-9LT44 44-Pin TQFP 8 isplsi 1-8LJ 44-Pin PLCC 8 isplsi 1-8LT44 44-Pin TQFP isplsi 1-LJ isplsi 1-LT44 INDUSTRIL fmax (MHz) tpd () Ordering Number Package isplsi 1-LJI 44-Pin PLCC MILITRY/883 Note: Lattice Semiconductor recognizes the trend in military device procurement towards using SMD compliant devices, as such, ordering by this number is recommended. 44-Pin PLCC 44-Pin TQFP isplsi 1-LT44I 44-Pin TQFP Family fmax (MHz) tpd () Ordering Number SMD # Package isplsi isplsi 1-LH/ MXC 44-Pin JLCC Table isp1 1