System Level Design. Technology. El Mostapha Aboulhamid Frederic Rousseau. Edited by. CRC Press. Taylor &. Francis Croup

Transcription

1 System Level Design wit5net Technology Edited by El Mostapha Aboulhamid Frederic Rousseau CRC Press Taylor & Francis Croup Boca Raton London New York CRC Press is an imprint of the Taylor Bt Francis Croup, an informa business

2 Contents Preface xi About the Editors xiii Contributor Biographies xv, 1 Introduction 1 Frederic Rousseau, James Lapalme, and El Mostapha Aboulhamid 11 Needs of a Complete and Efficient Design Environment The NET Framework Characteristics Expected from a Design Environment ESysNET: A NET Framework Based Design Environment Our Design, Simulation and Verification Flows DesignFlowwithESysNET Modeling and Specification Our System Design Flow Analysis of the Design Flow SimulationFlowwithESysNET Building the Simulation Model Separation of Concerns between Models and Simulation Towards a Multi-Level Simulation Model Observer-Based Verification Flow with ESysNET 20 14) Overview of the Observer-Based Verification Flow Building and Binding the Verification Engine to the Simula tion Model Comparison with the Same Verification Flow in SyslemC Towards a Powerful Verification Flow Conclusion and Book Organization 23 1 Modeling and Specification 27 2 High-Level Requirements Engineering for Electronic System-Level Design 29 Nicolas Gorse 21 Introduction Background Framework 31 v

3 SPIRIT System Level Design with NET Technology 222 Software Engineering Approaches Proposed Solution Formalism Linguistic Pre-Processing Consistency Validation Elicitation of Missing Functionalities Experimental Results Automatic Door Controller Industrial Router RapidIO Linking to a UML-Based Methodology Integrated Methodology Case Study Conclusion 52 The Semantic Web Applied to IP-Based Design: A Discussion on IP-XACT 55 James Lapalme, El Mostapha Aboulhamid, and Gabriela Nicolescu 31 Introduction Models ofarchitecture and XML GSRC and MoML Colif and Middle-ML Premadona SPIRIT IP-XACT Metadata Format Tight Generator Interface (TGI) Semantic Consistency Rules (SCR) The Semantic Web Resource Description Framework RDF Schema Web Ontology Language (OWL) SPARQL Tool for the Semantic Web: Editors and Jena SWRL and Jena rules XML and Its Shortcomings Multiple Grammars Documentation-Centric Biased Grammar Model Limited Metadata Advantages of the Semantic Web Richer Semantic Expressivity Separation between Semantics and Encoding Federated Data Model Simpler Data Manipulation Case Study - 79

4 371 Advantages Applied to Version Management (SPIRIT 12 to SPIRIT 14) Advantages Applied to Modeling Impact on TGI Implications for SPIRIT Semantic Constraint Rules (SCRs) Dependency XPath Cost of Adoption Future Research Conclusion 88 4 Translating Design Pattern Concepts to Hardware Concepts 89 Luc Charest, Yann-Gael Guehe'neuc, and Yousra Tagmouti 41 Introduction Object-Oriented Translations Translation of Classes and Their Members Translation of Object Encapsulation Translation of Object Instantiation Translation of Object Method Calls Translation of Polymorphism Translation of Inheritance and Casting Operations Constraint and Assumptions for Design Pattern Synthesis Constraint: Dynamism of the Hardware Assumption: Compiled Once Assumption: Limited Number of Objects Assumption: Pattern Automatic Recognition Problem Translation Cost versus Performance Design Pattern Mappings Creational Patterns Structural Patterns Behavioral Patterns Operational Description of Design Patterns PADL in a Nutshell PADL in Details PADL by Examples MIP ESysNET Code Generation Ill 46 Related Work & Background Ill 461 Object Oriented Synthesis & Patterns in Hardware Ill 462 Original Patterns Conclusion 113 II Simulation and Validation Using Transaction-Based Models for System Design and Simulation 117 Amine Anane, El Mostapha Aboulhamid, Julie Vachon, and Yvon Savaria vii

5 viii System Level Design with NET Technology 51 Introduction 1' 7 52 Motivations 53 Transaction Model STM Concurrent Execution I STM Implementation Techniques STM Implementation Examples STMImplementationUsingNET SXM Transactional Memory NSTM Transactional Memory PostSharp STM Framework Experimental Results I50 56 Conclusion and Future Work Simulation at Cycle Accurate and Transaction Accurate Levels 155 FredMc Pitrot and Patrice Gerin 61 Introduction Short Presentation of the Cycle Accurate and Transaction Accurate Abstraction Levels Cycle Accurate Simulation General Description System Properties Formal Model Simulator Implementation Transaction Accurate Simulation General Description Basic Concepts Native Simulation for MPSoC Summary and Conclusions An Introduction to Cosimulation and Compilation Methods 177 Mathieu Dubois, Frederic Rousseau, and El Mostapha Aboulhamid 71 Introduction Cosimulation Preliminaries: Managed and Unmanaged Code Same Binary File Shared Memory TCP/IP COM Static Function Pinvoke Managed Wrapper Comparison of Cosimulation Implementations Compiler Framework Common Intermediate Format 191

6 732 Interna] Data Structures Code Generation Compiled RTL Compiled TLM Conclusion 2()2 8 Timing Specification in Transaction Level Models 203 Alena Tsikhanovich, El Mostapha Aboulhamid, and Guy Bois 81 Summary Expressing Timing Timing Analysis Linear Constraint Systems Max Constraint Systems Max-Linear Systems Min-Max Constraint Systems Min-Max-Linear Constraint Systems Assume-Commit Constraint Systems Discussion Min-Max Constraint Linearization Algorithm Min-Max Constraint Linearization Algorithm Optimization Experimentations Timing in TLM Timing Modeling at CP+T Level Communication Exploration at PV and PV+T Levels Conclusion 238 III PracticalUseofESysNET ESysNET Environment 241 James Lapalme and Michel Metzger 91 Introduction Modeling My First Model Modeling Concepts Process Method Signals Simulation Simulator Semantics and Construction Semantics Verification Overview Case-Study Model: The AHB-Lite Bus How to Specify Properties Verifying Temporal Properties during Simulation 275 ix

7 x System Level Design with NET Technology 945 Linking Different Tools Observing Results Conclusion 279 References 281 Index 297