Testing Gated Mode on Hybrid 4.1

Transcription

1 Testing Gated Mode on Hybrid 4.1 1

2 Injection Scheme of SuperKEKB RF frequency 508 MHz 2503 bunches noisy bunches 100ns apart 20 µs frame ~ cooling: 4ms noisy / ~ 400 packets ~ 16 ms clean continuous injection every 20 ms ~ 400 revolutions with two noisy bunches mask noisy bunches: PXD deadtime = 20% the best solution: gate the DEPFET during the passage of the noisy bunches 100ns gate, with some rise and fall times, twice per frame 2 1/21/2015 Eduard Prinker, 7 th Belle II VXD Workshop

3 Laser, MIP always create charge noisy bunches create (junk) electrons within the PXD detector these junk electrons have to be removed while the number of stored electrons in the internal Gate should not be changed! by means of surface structuring, various deep implants and appropriate voltage combinations the internal Gate can be protected 3

4 Principle of DEPFET Gated Mode Applying appropriate voltages to Clear and Gate one can apply an electronic shutter: Clear pulse to all pixels during the noisy bunch injection (every 10µs, ΔU = 15V) Keep the Gate in the off state (+5V) Two questions for our Test-Set-up: 1. Can we protect charge in the internal Gate from being cleared? 2. How much of the junk charge will arrive in the internal Gate? 4

5 DEPFET: Potential Distribution in Collection Phase n+ implant 1 µm below surface charge moving perpendicular to equipotential surfaces deep n-implant creates a potential minimum for e - under the gate ( internal gate ) 5

6 Shielding of internal gate clear region is much larger than internal gate good for dumping electrons into the clear internal gate potential barrier caused by the reach through of the drain to the source (saddle point: capacitive coupled) 6

7 Selectivity of the Clear Process Real Clear External Gate in on state Suppressed Clear External Gate in off state Electrons can overcome the small potential barrier (<0.5V) by thermionic emission external gate shifts the potential of the internal gate by capacitive coupling e - stay in internal gate The difference is due to the applied voltage at the external gate 7

8 Experimental Set-Up only calibration DCDBpipeline Power Supply 8

9 Hybrid Board H Read-Out with DCDBpipeline SwitcherB18v2 DCDRO PXD6 Matrix Switch the DEPFET into blind mode by changing 1. the GateOn, ClearLow and ClearHigh voltages which are supplied to the Switcher 2. the operation mode is controlled by a Trigger (TLU plus Pulse Generator) 9

10 Test Sequence PC sequence FPGA SWB synchronized with the same clock as DCDPipeline S w i t c h e r DCDB pipeline P X D endless loop Program RAM Frame 1 R&C Frame 2 RnC Frame 3 RnC+L Frame 4 RnC Frame 5 Gated Frame 6 Gated Frame 7 Gated Sequence RAM Read&Clear ReadnoClear ReadnoClear +Laser Gated Mode Gated Mode +Laser Frame 8 RnC 10

11 Normal Operation 1 st row for gate activation rising edge of StrG has to be after falling edge of SwitcherClk clear pulse is only working when gate is switched on PMOS-gate on low = active 11

12 Gated mode without read-out one row remains sensitive on noisy bunches Enabling Gated Mode: SwitcherClk off, switch StrC to high, StrG continues running Minimum length of 8 falling StrG 12

13 Gated mode without read-out: Switcher input Read & Clear Read no Clear Gated Mode clk StrC StrG Trigger 13

14 Gated mode without read-out: Switcher output Read & Clear Read no Clear Gated Mode Clear Gate Trigger 14

15 Gated mode with read-out Enabling Gated Mode with read-out: SwitcherClk on high level & continues running, falling edge of StrG Clear changes to high level immediately on non-active channels Rolling shutter mode continued, no clear on activated channels 15

16 Test Program To evaluate if the gated-mode works, readout of 8 consecutive DEPFET frames for each trigger Experiment A: Signal Charge Restore Laser impinges on DEPFET pixels in sensitive mode hit pixel collects charge Enter gated mode, measuring charge in reference frame Goal: no charge loss from internal gate to clear Experiment B: Junk Charge Generation Laser impinges on DEPFET pixels in blind mode internal Gate is shielded Exit blind mode in consecutive frames Goal: hit pixel collects no charge from laser into internal gate 16

17 Experiment A: Signal Charge Restore Frame n Frame 0 Frame 1 Frame 2 Frame 3 Frame 4 Frame 5 Frame 6 Frame 7 Normal sequence Read & Clear ReadnoClear ReadnoClear + Laser ReadnoClear Gated Mode Gated Mode Gated Mode ReadnoClear 17

18 Gated Mode w/o RO Signal Charge Restore Clear 18V Ghost pixel? Read&Clear ReadnoClear ReadnoClear + Laser ReadnoClear 1,6µs Gated Gated Gated ReadnoClear Pedestals calculated for each frame separately Laser 1.4µs, 500mV 18

19 Gated Mode w/o RO Signal Charge Restore Clear 15V Read&Clear ReadnoClear ReadnoClear + Laser ReadnoClear Gated Gated Gated ReadnoClear 19

20 Gated Mode with RO Signal Charge Restore Clear 18V Read&Clear ReadnoClear ReadnoClear + Laser ReadnoClear Gated Gated Gated ReadnoClear 20

21 Gated Mode with RO Signal Charge Restore Clear 11V Read&Clear ReadnoClear ReadnoClear + Laser ReadnoClear Gated Gated Gated ReadnoClear 21

22 Experiment B: Junk Charge Generation Frame n Frame 0 Frame 1 Frame 2 Frame 3 Frame 4 Frame 5 Frame 6 Frame 7 Normal sequence Read & Clear ReadnoClear ReadnoClear ReadnoClear Gated Mode Gated Mode + Laser Gated Mode ReadnoClear 22

23 Gated Mode with RO Junk Charge Generation Clear 18V Read&Clear ReadnoClear ReadnoClear ReadnoClear Gated Gated + Laser Gated ReadnoClear Charge from rows switched on during gated mode (laser 1,4 µs) 23

24 Gated Mode with RO Junk Charge Generation Clear 11V Read&Clear ReadnoClear ReadnoClear ReadnoClear Gated Gated ReadnoClear Gated + Laser 24

25 sampling during clear pulse Pedestal Map GM with RO JC 11V switch into gated mode switch into readnoclear 25

26 Pedestal DistributionGM with RO JC 11V sampling with long clear ~30ns switch-off gated mode 26

27 NoiseGM with RO JC 11V 27

28 Conclusion & Outlook Hybrid4-Set-Up works although ideal combination of voltages and sequences not yet found Confident that we can show that laser induced charge is preserved during gating or shielded if laser is applied during gating Next steps: measurements with radioactive source in order to calibrate laser optimize settings (DEPFET voltages) checking switcher sequences applying different pedestal corrections 28

29 Thank you for your attention 29

30 Back-up Slides 30

31 Noise Map GM with RO JC 11V linear Mapping 31

32 Noise Map GM with RO JC 11V normal Mapping 32

33 Test Sequences Program RAM: contains all information in which order different sequences have to be run through endless loop until stop 16-bit program code Address Sequence Read & Clear Read no Clear Read no Clear + Laser Read no Clear Gated Mode Gated Mode Gated Mode Read no Clear Sequence RAM: contains all Trigger, Clk, StrG & StrC information for the whole sequence in binary format #4:trigger,#3:StrC, #2: StrG,#1:Clk 0,0,1,0 0,0,1,0 0,0,1,0 0,0,1,0 0,0,1,0 0,0,1,0 0,0,0,0 0,0,0,0 0,0,0,0 0,0,0,0 0,0,0,0 0,0,0,0 FPGA sequentially reads binary code and translates it into microcode same clock as for DCDBpipeline extra start-up sequence resets SwitcherB & prohibits DCDB RO during this time 33

34 SwitcherB strobe logic of one channel 34

35 Signal Loss during Gated Mode Charge loss depends on the Clear On and Gate Off voltage For Gate Off > 5V there is no charge loss Measurements by Felix Müller / Master Thesis 35