Histogram equalization of images

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1 CSL316 Digital Hardware Design Laboratory Project Report Indian Institute of Technology, Delhi Histogram equalization of images Pawan Jain (2003CS10177) Atul Bansal (2003CS10157) Cycle 1 Teaching Assistant: Mr. Anant Vishnoi Instructor: Prof. M. Balakrishnan 1

2 Contents TOPIC PAGE NO. 1. Specifications 3 2. High level description 4 3. The Algorithm 5 4. Overall Block Diagram 7 5. Circuit Description The Input-Output module The Datapart Histogram Generator Cumulative Histogram Generator Computation Part Transformation of input image The Control Part Simulation UCF File Implementation Results Conclusion 39 2

3 1. Specifications: 1.1 Input: The input is a monochrome uncompressed bitmap image file. Monochrome image consists of a pixel matrix. Each of the pixels is assumed to be encoded in 8-bits (Gray scale). This is ensured by the uncompressed nature of the input image file. There are two ways of transferring the image to the FPGA. One is to use the INCODE tool for transferring the image. But this will limit the maximum size of the image file to 256 pixels. Second option is to use the serial COM port to transfer the image s pixels one bit at a time. This will require programming the serial COM port in Visual C++ (Windows) or C++ (Linux). 1.2 Output: The output consists of an image whose pixel matrix is the result of normalization of the pixel matrix of the input image using the histogram equalization algorithm. The format of the output image will be same as that of the input image. 1.3 User interface: The user will input a text file containing the input image (max 255 pixels) pixel by pixel in a pre-specified format. Our module processes it after which the user can upload a file from the fpga board which will contain the output image pixel by pixel in the same format. 3

4 2. High level description: This circuit basically performs the histogram equalization to improve the quality of the input image. The computation basically proceeds in the following steps: Image download : In this step the image is downloaded and stored in a ram on the fpga. 1. Computation of Histogram: In this step the histogram of the image is constructed, the value of the histogram at any point I is equal to the no. of pixels in the image whose gray scale is equal to I. 2. Computation of Cumulative histogram: In this step the cumulative histogram is computed. The value of the cumulative histogram is equal to the sum of all the values of the histogram up to that point. 3. Computation of Transform function:- The transform function is computed from the cumulative histogram and a calculator module to get the transform function. The transform function is stored in a ram. If the value of the ram at I th address is equal to j then each pixel in the image is whose value is I has to be changed to j 4. Application of the transform function to obtain the new image:- In this step the output image is calculated in a ram after applying the transform function to the input image. Here the ram storing the output image is same as ram storing the cumulative histogram. This is done to save the no. of clb s required in the fpga. 5. Uploading the image to the PC using microcontroller :- In this step the image is uploaded to the PC from the ram using the read/write module. 4

5 3. The UNDERLYING THEORY: The ALGORITHM (Source: 1. For an N x M image of G gray-levels (often 256), create two arrays H and T of length G initialized with 0 values. 2. Form the image histogram: scan every pixel and increment the relevant number of H If pixel X has intensity p, perform H [ p] = H[ p] Form the cumulative image histogram H c. We may use the same array H to store the result. H [ 0] = H[0] H [ p] = H[ p 1] + H[ p] (1) 5

6 4. Set for p = 1,..., G-1. G 1 T[ p] = H[ p] MN Note the new gray-scale is assumed the same as the input image. i.e. q k = G-1 and q 0 = 0. (2) 5. Rescan the image and write an output image with gray-levels q, setting q = T[ p] (3) 6

7 4. The OVERALL BLOCK DIAGRAM Figure 1: The block diagram 7

8 5. CIRCUIT DESCRIPTION The design is completely modular. The various modules used are described with the input/output signals and functionality below: 5.1 The INPUT-OUTPUT module On the outline, the module looks like what is shown below. Figure 2: The Input-Output Module Inputs: WR_L, RST, RD_L, MY, HISGEN, TR[7:0], PICDATAOUT[7:0], K[7:0] Outputs: RDADDR[7:0], PICDATAOUT[7:0], CNTROUT[7:0] 8

9 Its internals are shown below: The Main Computation Unit: Figure 3: Internals of the Input-Output Module 9

10 5.1.1 Functionality This module performs two functions: a Image download This module takes its inputs as defined above from the microcontroller. The user can download the image file in the prescribed format from the PC to a RAM in the FPGA through the microcontroller using this module. The input data is stored in the PICRAM inside this module starting from address zero. Thus the size of the image file is limited to 256 pixels as the maximum depth allowed for a RAM in the fpga used is 256. The download is performed by the user through the INCODE program. If the user wants to perform a computation again then he can reset this module using the RST signal given as the input. This signal has to be kept low while the data is being downloaded b Image upload The command for image upload is given by the user in using INCODE. This module writes the data to be uploaded on the bidirectional bus named AD. The data is put on the bus AD after each positive edge of the RD_L signal coming from the microcontroller. 10

11 5.1.2 Signals description 5.1.2a Inputs (a) WR_L This signal comes from the microcontroller, when it goes from zero to one the input is latched in the ram and he counter keeping the coutnt of the no, of data samples already arrived. (b) RD_L This signal also comes from the microcontroller. When this input goes from 0 to 1 The data is put on the bidirectional bus and and the counter keeping the count of the no. of the read requests is incremented. (c) RST This signal resets the counters so that the module may be reused for downloading/uploading a new image file. (d) PICDATAIN This module provides the input which is to be written in the ram when the acive edge of the WR_L comes. (e) HISGEN when this signal is up then the module give the value of the data stored the ram On the picdata out signal. 11

12 (f) K[7:0] This signal comes gives the address of the ram when this module is in hisgen mode. (g) MY When this signal is up then the entire circuit is in process of calculating the output image from the transform function calculated in the outram b Outputs (a) RDADDR [7:0] This bus gives the urrent value of the read counter. (b) CNTROUT [7:0] Thus bus gives the current value of the write counter. (c) PICDATAOUT This gives the output of the ram which contains the value of the pixels of the image in the input. 5.2 The DATAPART 12

13 The next page shows the complete Datapart. 13

14 Figure 4: The datapart The various parts of the datapart are: Histogram Generator This part generates the histogram from the given input picture RAM. Figure 5: The histogram generator This part of the data part computes the histogram from the image stored in the PICRAM as follows: For every value in the PICRAM the corresponding position in the cumulative ram is incremented resulting in generation of histogram in 256 cycles. The counter J is used when data is to be read from HISRAM. In that case sel_2 signal is zero (this signal comes from microcontroller). 14

15 5.2.2 Cumulative Histogram Generator Figure 6a: The cumulative histogram calculation 15

16 Figure 6b: The cumulative histogram storage This part of the circuit works in two modes:- In the first mode the previous value of the CUMRAM is added to the current value of the HISRAM to get the new value of the cumulative histogram. This goes on for 256 cycles to generate the cumulative histogram. 16

17 In the second mode (this mode is active when the current instruction in the microcontrol in 15, in which case the value of the signal MY is 1). IN that case the output of the PICRAM is fed into the address line of the OUTRAM and the output of the OUTRAM is fed into the data line of the CUMRAM. The data now being stored in the CUMRAM is the final output image which is written at the falling edge so that the address at the address line is constant when data is written in the CUMRAM Computation part A small module was made out of the computation part. The module is Figure 7: The calculation module 17

18 Internals: This is the basic operation performed by the calculating module. The algorithm requires the following computation: G 1 T[ p] = H[ p] MN (for an image with grayscale 0 to G-1 and size M pixels x N pixels) For the present case, G = 256 and M=N=16. So we need to multiply a number by 255 and divide it by 256. Multiplying a number x with 255 is same as: x* 255 = x* 256 x This small manipulation makes it a lot easier in hardware to perform the computation. And then to divide by 256, the last 8 bits are dropped out. Figure 8: The calculation module block diagram 18

19 s Figure 9: The calculation module internals Transformation of the image The transform thus obtained is applied to the input image as shown below: 19

20 Figure 10a: Reading the new value for each pixel 20

21 Figure 10b: The cumulative RAM being reused to store the new image 21

22 5.2.5 Signals summary There are 2 status signals: j_not_255 k_not_zero There are 12 control signals: inc_k sel_2 hisgen ld_j outwr cumwr hiswr clr_j inc_j my ld_r1 sel_1 22

23 5.3 The CONTROL PART Micro-programmed control has been implemented. Inputs: 2 status bits Outputs: 12 control bits The microcontroller consists of microsequencer, a multiplexer to select the next address and a register to latch the current instruction. A combinational logic is used to calculate the select signals of the multiplexer. The instructions supported by the microsequencer are: INSTRUCTION ENCODING (i 1 i 0 ) Next address: 00 Conditional jump: 01 Unconditional jump: 10 The algorithm broadly involves steps that are doable within 16 instructions. Empty instructions have been included wherever necessary to incorporate appropriate delays. 23

24 μ Seq Control 18 R 11 ROM E G 2 1 Mux Data Part 2 Figure 11: The Microprogrammed control: Outline 24

25 The micro-sequencer: Figure 12: The Microsequencer Select Logic: S1 = i 0 i 1 r + i 1 c r S0 = r i 0 i 1 + i 0 i 1 r c (Where S1, S0 are bits of output, i 1 and i 0 are bits of instruction, c represents Condition, r represents Reset) 25

26 Figure 13: The micro-sequencer Next-Address select logic Figure 14: The micro-sequencer condition-select multiplexer 26

27 Figure 15: The micro-programmed control as in the schematic 27

28 According to the algorithm stated on page 5, the symbolic instructions are: (Default values for all signals: 0) 0: sel_2, hisgen, clr_j 1: sel_2, hisgen, hiswr 2: inc_k, sel_2, hisgen 3: sel_2, hisgen, c_sel=10, NA=2, mseq_inst=01, hiswr 4: clr_j, sel_1 5: ld_r1, sel_1 6: sel_1 7: cumwr 8: inc_j, ld_r1 9: c_sel=00, NA=8, mseq_inst=01, cumwr 10: ld_j 11: NOP 12: outwr 13: inc_j 14: c_sel=01, NA=13, mseq_inst=01, outwr 15: NA=15, mseq_inst=10, my So we finally have Bits for Next Instruction Address : n=4 Bits for Datapart Controls : m=12 Bits for mseq_inst select : k=2 Bits for condition select : s=2 Hence the instruction will be 20 bits wide. 28

29 The micro-instruction format: Figure 16: The micro-instruction format The microprogram was fed into the control ROM. The ROM contents have been listed below. 0000: ; 0001: ; 0010: ; 0011: ; 0100: ; 0101: ; 0110: ; 0111: ; 1000: ; 1001: ; 1010: ; 1011: ; 1100: ; 1101: ; 1110: ; 1111: ; 29

30 6. SIMULATION (a) Functional Simulation A screenshot of the simulation is shown below. The simulation extends till around 80 µs, so it is not possible to show the whole of it here. The waveform has been saved and will be shown during the demo. Figure 17: The functional simulation results 30

31 (a) Timing Simulation A screenshot of the simulation is shown below. The simulation extends till around 80 µs, so it is not possible to show the whole of it here. The waveform has been saved and will be shown during the demo. Figure 18: The timing simulation results 31

32 7. The.UCF file (pin mappings) ################################ # THE RW CIRCUIT (internal) # ################################ NET AD<0> LOC=P9; NET AD<1> LOC=P8; NET AD<2> LOC=P7; NET AD<3> LOC=P6; NET AD<4> LOC=P5; NET AD<5> LOC=P4; NET AD<6> LOC=P3; NET AD<7> LOC=P84; NET RD_L LOC=P83; NET WR_L LOC=P82; ############################## # CN 13 TO 1 # ############################## NET CURRADDROB3 LOC=P14; NET CURRADDROB2 LOC=P15; NET CURRADDROB1 LOC=P16; NET CURRADDROB0 LOC=P17; NET CNTROUTOB3 LOC=P18; NET CNTROUTOB2 LOC=P19; 32

33 NET CNTROUTOB1 LOC=P20; NET CNTROUTOB0 LOC=P23; NET RDADDROB3 LOC=P24; NET RDADDROB2 LOC=P25; NET RDADDROB1 LOC=P26; #NET RDADDROB0 LOC=P27; NET LSBOB LOC=P27; ############################### # CN 17 TO 11 # ############################### NET RESETRW LOC=P60; NET RESETIN LOC=P61; 33

34 8. Implementation results Design Summary: Number of errors: 0 Number of warnings: 35 Number of CLBs: 377 out of % CLB Flip Flops: 72 4 input LUTs: 196 (1 used as route-throughs) 3 input LUTs: 22 32X1 RAMs: X1 ROMs: 20 Number of bonded IOBs: 25 out of 61 40% IOB Flops: 0 IOB Latches: 0 Number of TBUFs: 280 out of % Number of RPM macros: 1 Number of OSC: 1 out of 1 100% Total equivalent gate count for design: Additional JTAG gate count for IOBs: 1200 Device utilization summary: Number of External IOBs 25 out of % Flops: 0 Latches: 0 34

35 Number of CLBs 377 out of % Total CLB Flops: 72 out of 800 9% 4 input LUTs: 728 out of % 3 input LUTs: 278 out of % Number of OSCILLATORs 1 out of 1 100% Number of TBUFs 280 out of % Timing summary: Timing errors: 0 Score: 0 Constraints cover paths, 582 nets, and 4862 connections (100.0% coverage) Design statistics: Minimum period: ns (Maximum frequency: 9.191MHz) Maximum net delay: ns PAR The Delay Summary Report The Score for this design is:

36 The Number of signals not completely routed for this design is: 0 The Average Connection Delay for this design is: ns The Maximum Pin Delay is: ns The Average Connection Delay on the 10 Worst Nets is: ns Listing Pin Delays by value: (ns) d < 7.00 < d < < d < < d < < d < d >= Section 4 - Removed Logic Summary block(s) removed 29 block(s) optimized away 37 signal(s) removed POST LAYOUT TIMING REPORT Data Sheet report: All values displayed in nanoseconds (ns) Setup/Hold to clock WR_LIB Setup to Hold to Source Pad clk (edge) clk (edge) AD<0> (R) (R) 36

37 AD<1> (R) (R) AD<2> (R) (R) AD<3> (R) (R) AD<4> (R) (R) AD<5> (R) (R) AD<6> (R) (R) AD<7> (R) (R) Clock RD_LIB to Pad clk (edge) Destination Pad to PAD AD<0> (R) AD<1> (R) AD<2> (R) AD<3> (R) AD<4> (R) AD<5> (R) AD<6> (R) AD<7> (R) RDADDROB (R) RDADDROB (R) RDADDROB (R) RDADDROB (R) Clock WR_LIB to Pad clk (edge) Destination Pad to PAD CNTROUTOB (R) CNTROUTOB (R) CNTROUTOB (R) CNTROUTOB (R) Clock to Setup on destination clock RD_LIB Src:Rise Src:Fall Src:Rise Src:Fall Source Clock Dest:Rise Dest:Rise Dest:Fall Dest:Fall

38 RD_LIB Clock to Setup on destination clock WR_LIB Src:Rise Src:Fall Src:Rise Src:Fall Source Clock Dest:Rise Dest:Rise Dest:Fall Dest:Fall WR_LIB Pad to Pad Source Pad Destination Pad Delay RESETIN CURRADDROB RESETIN CURRADDROB RESETIN CURRADDROB RESETIN CURRADDROB

39 9. Conclusions and Possible Refinements Various possible extensions to this project may be: (a) Some optimizations may be implemented like: 1. Reducing the no. of RAMs used by reusing the RAM storing the histogram for storing the cumulative histogram. 2. Reducing the size of the microinstruction by encoding various signals into various fields. 3. Splitting the last loop (in which the transform function is to be applied) into two clock cycles so that that maximum clock frequency is increased. (b) Increasing the size of the input image. But this will require a bigger FPGA because the maximum depth allowed in XC4010PC84 is 256 words. 39

Virtex-II Architecture

Virtex-II Architecture Block SelectRAM resource I/O Blocks (IOBs) edicated multipliers Programmable interconnect Configurable Logic Blocks (CLBs) Virtex -II architecture s core voltage operates at 1.5V