VHDL Coding Styles and Methodologies. Second Edition

Transcription

1 VHDL Coding Styles and Methodologies Second Edition

2 VHDL Coding Styles and Methodologies Second Edition Ben Cohen KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

3 CD-ROM only available in print edition. ebook ISBN: Print ISBN: Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow Print 1999 Kluwer Academic Publishers Dordrecht All rights reserved No part of this ebook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Kluwer Online at: and Kluwer's ebookstore at:

4 CONTENTS 1.0 VHDL OVERVIEW AND CONCEPTS WHAT IS VHDL LEVEL OF DESCRIPTIONS METHODOLOGY AND CODING STYLE REQUIREMENTS VHDL TYPES VHDL OBJECT CLASSES Constant Signal and Variable File 1.6 VHDL DESIGN UNITS ENTITY Style Comment Header Generics Indentation Line length Statements per line Declarations per line Alignment of declarations Entity Ports ARCHITECTURE Process 1.7 COMPILATION, ELABORATION, SIMULATION Compilation Example Simulation Example Synthesis Example 2.0 BASIC LANGUAGE ELEMENTS 2.1 LEXICAL ELEMENTS Identifiers Port Identifiers Identifier Naming Convension Accessing Identifiers Defined in Packages Capitalization 2.2 SYNTAX Delimiters Literals Decimal literals Based literals Character literals String literals Bit string literals Operators and Operator Precedence Logical operators Relational Operators Shift Operators The Concatenation "&" Operator

5 vi VHDL Coding Styles and Methodologies Remainder and Modulus 2.3 TYPES AND SUBTYPES Scalar Type Integer Type and Subtypes Composite Arrays Records Access Type FILE ATTRIBUTES ALIASES Enumeration Types User Defined Enumeration Types Predefined Enumeration Types Boolean Type Physical types Distinct Types and Type Conversion Real type One Dimensional Arrays Unconstrained Array Types Multi-dimensional Array types Anonymous Arrays Implicit Functions for Array Declarations Array Slices and Ranges 3.0 CONTROL STRUCTURES 3.1 EXPRESSION CLASSIFICATION 3.2 CONTROL STRUCTURES The"if" Statement The Case Statement Rules for the Case Statement Latch Inference Register Inference Loop Statement The Simple Loop The while loop The for loop for loop Rules 4.0 DRIVERS 4.1 RESOLUTION FUNCTION 4.2 DRIVERS Definition and Initialization Creation of Drivers Drivers and Resolved Signal Types Driving Data from multiple Processes onto a Non-Resolved Signal 4.3 PORTS 5.0 VHDL TIMING 5.1 SIGNAL ATTRIBUTES 5.2 THE "WAIT" STATEMENT Delta Time wait on sensitivity_list

6 Table of Contents vii wait until condition wait for time_expression SIMULATION ENGINE MODELING WITH DELTA TIME DELAYS Wait for 0 ns Method Concurrent Statements Method Use of Variables Method VITAL Tables 5.5 INERTIAL / TRANSPORT DELAY Simulation Engine Handling of Inertial Delay Simple View Updating Projected Waveforms per LRM ELEMENTS OF ENTITY/ARCHITECTURE VHDL ENTITY VHDL ARCHITECTURE Process Statement Concurrent Signal Assignment Statements Conditional Signal Assignment Selected Signal Assignment Component Instantiation Statement Port Association Rules Connection Type Conversion Concurrent Procedure Call Generate Statement Concurrent Assertion Statement Block Statement Guarded Signal Assignments SUBPROGRAMS SUBPROGRAM DEFINITION SUBPROGRAM RULES AND GUIDELINES Unconstrained Arrays in Subprograms Interface class declaration Subprogram Initialization Subprogram Implicit Signal Attributes Passing Subtypes Drivers in Subprograms Signal Characteristics in Procedure Calls Side Effects Separating High Level Tasks FromLow Level Protocols Positional and Named Notation SUBPROGRAM OVERLOADING FUNCTIONS RESOLUTION FUNCTION OPERATOR OVERLOADING CONCURRENT PROCEDURE PACKAGES PACKAGE Package Declaration

7 viii VHDL Coding Styles and Methodologies Package Body Deferred Constant The "use" Clause Signals in Packages Resolution Function in Packages Subprograms in Packages CONVERTING TYPED OBJECTS TO STRINGS PACKAGE TEXTIO Printing Objects from VHDL DESIGN OF A LINEAR FEEDBACK SHIFT REGISTER (LFSR) Random Number Generation COMPILATION ORDER Compilation Rules on Changes Automatic Analysis of Dependencies USER DEFINED ATTRIBUTES, SPECIFICATIONS, AND CONFIGURATIONS ATTRIBUTE DECLARATIONS USER-DEFINED ATTRIBUTES SPECIFICATIONS Attribute Specifications 9.4 CONFIGURATION SPECIFICATION Default Binding Indication Explicit Binding Indication in Configuration Specifications 9.5 CONFIGURATION DECLARATION Binding with configured components CONFIGURATION OF GENERATE STATEMENTS Deferring the Binding of an Instance of a Component 10.0 DESIGN FOR SYNTHESIS CONSTRUCTS FOR SYNTHESIS REGISTER INFERENCE Signals Assignments in Clocked Process Variable assignments in clocked process Asynchronous Reset or Set of Registers Synchronous Reset or Set of Registers 10.3 COMBINATIONAL LOGIC INFERENCE Latch Inference and Avoidance Variable STATE MACHINE RTL STATE MACHINE DESIGN STYLES State Machine Styles Safe FSM with No Lock up 10.6 ARITHMETIC OPERATIONS 11.0 FUNCTIONAL MODELS AND TESTBENCHES TESTBENCH MODELING Testbench Overview Testbench Design Methodology Validation Plan List of errors to be detected Architecture block diagram

8 Table of Contents ix Testbench design Testbench Architectures Typical Testbench Architecture FM/BFM Modeling Requirements SCENARIO GENERATION SCHEMES Scenario Generation Model: VHDL Code Waveform Generator Client/Server Scenario Generation Model: Text Command File Scenario Generation Model: Binary Command File Generation of Binary Files UART PROJECT UART ARCHITECTURE UART Transmitter General UART Concepts UART Transmitter design UART Receiver UART TESTBENCH UART Package Transmit Protocol Receive Protocol Component Transmission Line Component Monitor or Verifier Component Testbench Entity and Architecture Configuration VITAL 13.1 VITAL Overview VITAL FEATURES VITAL MODEL Pin-to-Pin Delay Modeling Style Distributed Delay Modeling Style APPENDIX A APPENDIX B APPENDIX C APPENDIX D APPENDIX E APPENDIX F APPENDIX G APPENDIX H VHDL'93 AND VHDL'81 SYNTAX SUMMARY PACKAGE STANDARD PACKAGE TEXTIO STD_LOGIC_TEXTIO PACKAGE STD_LOGIC_1164 NUMERIC_STD STD_LOGIC_UNSIGNED STD_LOGIC_SIGNED

9 x VHDL Coding Styles and Methodologies APPENDIX I APPENDIX J STD_LOGIC_ARITH STD_LOGIC_MISC APPENDIX K INDEX VHDL PREDEFINED ATTRIBUTES

10 PREFACE VHDL Coding Styles and Methodologies, Edition is a follow up book to the first edition of same book and to VHDL Answers to Frequently Asked Questions, first and second editions. This book was originally written as a teaching tool for a VHDL training course. The author began writing the book because he could not find a practical and easy to read book that gave in depth coverage of both, the language and coding methodologies. This edition provides practical information on reusable software methodologies for the design of bus functional models for testbenches. It also provides guidelines in the use of VHDL for synthesis. All VHDL code described in the book is on a companion CD. The CD also includes the GNU toolsuite with EMACS language sensitive editor (with VHDL, Verilog, and other language templates), and TSHELL tools that emulate a Unix shell. Model Technology graciously included a timed evaluation version of ModelSim, a recognized industry standard VHDL/Verilog compiler and simulator that supports easy viewing of the models under analysis, along with many debug features. In addition, Synplicity included a timed version of Synplify, a very efficient, user friendly and easy to use FPGA synthesis tool. Synplify provides a user both the RTL and gate level views of the synthesized model, and a performance report of the design. Optimization mechanisms are provided in the tool. This book is intended for: College students. It is organized in thirteen chapters, each covering a separate aspect of the language, with complete examples. Students can compile and simulate the examples to get a greater understanding of the language. Each chapter includes a series of exercises to reinforce the concepts. Engineers. It is written by an aerospace engineer who has many years of hardware, software, computer architecture and simulation experience. It covers practical applications of VHDL with coding styles and methodologies that represent what is current in the industry. VHDL synthesizable constructs are identified. Included are practical guidelines for the design of bus functional models used in testbenches, such as waveform generation, client/server control, text and binary file command methods, and binary file generation schemes. Also included is an elaboration of a project for the design of a synthesizable Universal Asynchronous Receiver Transmitter (UART), and a testbench to verify proper operation of the UART in a realistic environment, with CPU interfaces and transmission line jitter. An introduction to VHDL Initiative Toward ASIC Libraries (VITAL) is also provided. The book emphasizes VHDL 1987 standard but provides guidelines for features implemented in VHDL 1993.

11 xii VHDL Coding Styles and Methodologies This book differs from other VHDL books in the following respects: 1. Emphasizes VHDL core, Ada like sequential aspects and restrictions, along with the VHDL specific, concurrent aspects of the language. 2. Uses complete examples with good code, and code with common mistakes experienced by users to demonstrate the language restrictions and misunderstandings. 3. Provides a CD that includes all the book examples in addition to GNU EMACS language sensitive editor, other useful reference VHDL code material, and GNU TSHELL. 4. Uses an easy to remember symbology notation throughout the book to emphasize language rules, good and poor methodology and coding styles. 5. Identifies obsolete VHDL constructs to be avoided. 6. Identifies non-synthesizable structures. 7. Covers practical design of testbenches for modeling the environment and automatic verification of a unit under test. 8. Provides a complete design example that uses the guidelines presented in the book. 9. Provides an introduction to VITAL. 10. Provides guidelines for synthesis and identifies the VHDL constructs that are typically synthesizable. This book is organized in four basic VHDL aspects: 1. SEQUENTIAL LANGUAGE. This is similar to the sequential aspects of other programming languages like C or Ada. Chapter 1 provides sufficient knowledge to compile and simulate a simple counter. Chapter 2 covers the basic language elements including the lexical elements, the syntax, and the types. Chapter 3 discusses the control structures. 2. CONCURRENCY. This differentiates VHDL from other sequential languages. Chapter 4 discusses drivers, chapter 5 covers the timing and chapter 6 emphasizes the concurrent statements. 3. ADVANCED TOPICS. This includes subprograms in chapter 7, packages in chapter 8, and attributes, specifications and configurations in chapter 9, and design for synthesis in chapter APPLICATIONS. This emphasizes reusable software methods to generate functional models, bus functional models, and testbench designs in chapter 11; a UART project with synthesizable transmitter and receiver in a testbench environment in chapter 12; VITAL coding style optional methodology in chapter 13. The language rules, coding styles, and methodologies presented in this book support the structure necessary to create digital hardware designs and models that are readable, maintainable, predictable, and efficient.

12 About The CD Table 1 summarizes the contents of the enclosed CD.

13 NOTATION CONVENTIONS The following symbols and syntactic description are used to facilitate the learning of VHDL. SYMBOLS Methodology and guideline. Two thumbs up. Good methodology or approach. Two thumbs down. Poor methodology or approach. Disagreement in community on methodology or approach. Legal or OK code Coding Error Synthesizable Non-Synthesizable Ellipsis points in code: Source code not relevant to discussion. [1] Quotations reprinted from IEEE Std IEEE Standard VHDL Language Reference Manual (LRM). Quotations printed in "italic and in this font". Syntax reprinted from the LRM "in this font", but without the prefix [1]. Boldface Boldface in text: Emphasizes important points. Boldface in syntax and sample code: Emphasizes VHDL reserved words.

14 xvi VHDL Coding Styles and Methodologies SYNTACTIC DESCRIPTION left_hand_side ::= right_hand side left_hand_side is the syntactic category right_hand_side is a replacement rule ::= (read as "can be replaced by") Vertical bar separates alternative items Example: letter_or_digit ::= letter digit Square brackets [] enclose optional items Example: return_statement ::= return [expression] Braces {} enclose a repeated item (zero or more times). Example: index_constraint ::= (discrete_range, {discrete_rang}) Underlined identifies that the notation is applicable for VHDL 93 ONLY Example: end [configuration] [configuration_simple_name]

15 Acknowledgments VHDL Coding Styles and Methodologies, Edition evolved from the previous edition of this book, and from VHDL Answers to Frequently Asked Questions, first and second editions. It also evolved from several documents and discussions with several individuals, along with personal experiences and frustration of students in using VHDL. I thank Model Technology for allowing me access to ModelSim, an excellent and easy to use VHDL/Verilog compiler/simulator, and for their excellent product support. I thank Synplicity for allowing me access to Synplify, a very efficient, user friendly and easy to use FPGA synthesis tool. I also thank these two companies for providing evaluation copies of their tools in this book. I thank Peter Sinander from the European Space Agency for publishing on the Internet the document VHDL Modelling Guidelines 2. I thank Janick Bergeron from Qualis Design Corp for publishing on the Internet the document Guidelines for Writing VHDL Models in a Team Environment 3. Those documents contributed to many of the coding styles presented in this book. I thank Richard Hall from Cadence Design Systems, Inc. who reviewed the original version of this book and provided many suggestions. I thank Larry Saunders, Steve Schoessow, Johan Sandstrom, and John Coffin for various VHDL discussions we had over the years on the use of VHDL. I thank Synopsys, Inc. for the release of their VHDL packages. I thank Geoff Voelker, Andrew Innes and Reto Zimmermann for their effort in providing GNU Emacs for Windows NT and Windows 95/98. I thank James Fulcomer and Drew Davidoff for their inquisitive challenges in the use of the language, in addition to compiling the GNU software into an easy to install package. I also thank my publisher Carl Harris for supporting in these endeavors of publishing books. I acknowledge my daughter Lori Hillary, and my son Michael Lloyd for inspiring me to teach. I especially thank my wife, Gloria Jean, for her patience and support in these projects 2 The VHDL Modelling Guidelines document is available through anonymous ftp from ftp.estec.esa.nl in the "/pub/vhdl" directory. 3 The Guidelines for Writing VHDL Models in a Team Environment is available via ftp from vhdl.org as /pub/misc/guidelines.paper.ps.

16 xviii VHDL Coding Style and Methodologies About the Author Ben Cohen has an MSEE from USC and is a Scientist engineer at Raytheon Systems Company. He has technical experience in digital and analog hardware design, computer architecture, ASIC design, synthesis, and use of hardware description languages for modeling of statistical simulations, instruction set descriptions, and hardware models. He applied VHDL since 1990 to model various bus functional models of computer interfaces. He authored VHDL Coding Styles and Methodologies, 1st Edition, and VHDL Answers to Frequently Asked Questions, first and second editions. He was one of the pilot team members of the VHDL Synthesis Interoperability Working Group of the Design Automation Standards Committee who authored the IEEE P Standard For VHDL Register Transfer Level Synthesis. He has taught several VHDL training classes, and has provided VHDL consulting services on several tasks. Web page: VhdlCohen@aol.com