Advanced Software Writing Using AXI

Transcription

1 Lab Workbook Introduction This lab guides you through the process of adding timer and interrupt controller to an embedded system and writing a software application that utilizes these timer and interrupt controller. The SDK will be used to create and debug the software application. Objectives After completing this lab, you will be able to: Utilize the AXI timer with interrupt controller Assign an interrupt handler to the timer Develop an interrupt handler function Use SDK Debugger to set break points and view the content of variables and memory Procedure This lab is separated into steps that consist of general overview statements that provide information on the detailed instructions that follow. Follow these detailed instructions to progress through the lab. This lab comprises 5 primary steps: You will add a timer and interrupt controller, create a SDK software project, write an Interrupt Handler, add a Linker script, and, finally, verify and debug application operation in hardware using SDK. Design Description You will extend the hardware design created in lab 5 to include an AXI interrupt controller and AXI Timer (see Figure 1). You will develop an interrupt handler to count the interrupts generated from the timer. Figure 1. Design Updated from Previous Lab Nexys3 5-1

2 Lab Workbook General Flow for this Lab Step 1: Add a timer and interrupt controller Step 2: Create a SDK software project Step 3: Write an Interrupt Handler Step 4: Add a Linker script Step 5: Verify operation in hardware Add a Timer and Interrupt Controller Step Create a lab5 folder and copy the contents of the lab4 folder into the lab5 folder, or copy the content of the labsolution\lab4 folder into the lab5 folder. Launch Xilinx Platform Studio (XPS) and open the project file Create a lab5 folder in the C:\xup\embedded\labs directory and copy the contents from lab4 to lab5, or copy the content of the labsolution\lab4 folder into the lab5 folder Open XPS by selecting Start > All Programs >Xilinx Design Tools > ISE Design Suite 14.2 > EDK > Xilinx Platform Studio Browse to the lab5 directory and open the project system.xmp 1-2. Add the AXI timer and AXI Interrupt Controller peripherals to the design from the IP Catalog, and connect them to the system according to the following table. Intr Irq CaptureTrig0 Interrupt INTERRUPT AXI_intc_0 instance delay_interrupt axi_intc_0_interrupt delay instance net_gnd delay_interrupt microblaze_0 instance axi_intc_0_ INTERRUPT Add the AXI Timer/Counter peripheral from the DMA and Timer section of the IP Catalog, and click Yes Check Only One Timer is present option and change its instance name to delay Click OK twice to add it Add the AXI Interrupt Controller peripheral from the Clock, Reset, and Interrupt section of the IP Catalog with default settings. Nexys

3 Lab Workbook The two added peripherals are automatically connected to the AXI4-Lite interface. Figure 2. Added interrupt controller and timer peripherals instances Select the Addresses tab The generated addresses should look similar to that indicated in the figure below. Figure 3. Generated Addresses for the Interrupt Controller and Timer peripherals In the Ports tab, connect the interrupt controller and timer as follows. o Click in the intr field of axi_intc_0 field to open the Interrupt Connection Dialog. Click on delay on left side, and click on right-arrow sign to add to the Connected Interrupts field (right), and then click OK Figure 4. Connecting the timer and interrupt controller interrupt ports o Connect CaptureTrig0 port of delay instance to net_gnd to avoid erroneous interrupt request generated due to noise on the unconnected input port Nexys3 5-3

4 Lab Workbook In Bus Interfaces tab, connect INTERRUPT (external interrupt request) port of the microblaze_0 instance to axi_intc_0_interrupt as shown below. Figure 5. Connect the MicroBlaze Interrupt to axi_intc_0_interrupt Select Hardware > Generate Bitstream to generate new system.bit file. Create an SDK Software Project Step Launch SDK and create a new empty software application project named lab5. Associate it to the standalone_bsp_0 software platform project. Import the lab5.c source file into lab5 application project Open SDK by selecting Project > Export Hardware Design to SDK Check Include Bitstream and BMM File option and click on Export & Launch SDK button. This will implement the design if necessary and generate system.bit and system_bd.bmm Browse to c:\xup\embedded\labs\lab5\sdk\sdk_export as the Workspace and click OK Right-click on standalone_bsp_0 in the Project Explorer window and select Clean Project. This will recompile the board support package including drivers associated with the just added peripherals (timer, interrupt) Right-click on standalone_bsp_0 in the Project Explorer window and select New > Project Select Xilinx C Project and click Next Choose Empty Application in Select Project Template window, enter lab5 in the Project Name field, and click Next. Nexys

5 Lab Workbook Click Target an Existing Board Support Package, choose standalone_bsp_0 and click Finish Select lab5 in the project view, right-click, and select Import Expand the General folder and double-click on File System and browse to c:\xup\embedded\sources. Select lab5.c and click Finish Note that both the Problems and Console tabs on the bottom report several compilation errors Note also that the project outline on the right side is updated to reflect the libraries and routines used in the source file Correct the errors In the Problems tab, double-click on the first red x for the parse error. This will open the source file bring you around to the error place. Figure 6. First error Add the missing global variable declaration as unsigned int, initialize it to the value of 1, and save the file. The first error message should disappear Click the next error message to highlight the problem in the source code Figure 7. Second error Add the missing global variable declaration as int, initialize it to the value of 0, and save the file. The program will be compiled again. Nexys3 5-5

6 Lab Workbook Figure 8. Add global variable declarations Write an Interrupt Handler Step Create the interrupt handler for the AXI timer Go to where the interrupt handler function has already been stubbed out in the source file (a fast way to do this is to click on the function in the outline view) The first step in creating an AXI timer interrupt handler is to verify that the AXI timer caused the interrupt. This can be determined by looking at the AXI Timer Control Status Register or using an API function. Open the API documentation to determine how this can be done In SDK, open the timer API documentation by clicking Documentation link corresponding to the delay instance in the system.mss tab Go to the File List section and select xtmrctr.c. You will see several available functions including XTmrCtr_IsExpired. XTmrCtr_IsExpired(XTmrCtr * InstancePtr, u8, TmrCtrNumber) Checks if the specified timer counter of the device has expired. In capture mode, expired is defined as a capture occurred. In compare mode, expired is defined as the timer counter rolled over/under for up/down counting. When interrupts are enabled, the expiration causes an interrupt. This function is typically used to poll a timer counter to determine when it has expired. Add the XTmrCtr_isExpired function call to the code with the associated parameters. if (XTmrCtr_IsExpired(InstancePtr, TmrCtrNumber)); Complete the Interrupt handler according to the steps below. 1. Increment a counter if an interrupt was taken. 2. Display the count value by using the MYIP peripheral and print the value using xil_printf (same functionality as printf with the exception of floating-point handling). Nexys

7 Lab Workbook Hint: You may use the LED_IP_mWriteReg () function. The completed handler should look like as shown in the next figure (you can find code in source folder named lab5_soln.c). Figure 9. Completed Interrupt Handler Code Save all the files Compile the source successfully. Add Linker Script Step Generate the linker script by setting heap and stack to 0x400 each and in AXI_BRAM_Controlller Right-click lab5 in project view and select Generate Linker Script Set the heap and stack size to 1024 bytes each Assign heap and stack section to AXI_BRAM_Controller memory Figure 10. Generate linker script Nexys3 5-7

8 Lab Workbook Click Generate to generate the linker scrip. The program will be compiled again. Click Yes to overwrite file Look in the console to answer the following question. Question 1 What is the size of the compiled program?.text segment:.data segment:.bss segment: Total in decimal: Total in hexadecimal: Verify Operation in Hardware Step Program the FPGA using the bootloop program Connect and power up the board Select the tab. If it is not visible then select Window > Show view > Terminal Click on and select appropriate COM port (depends on your computer), and configure it with baud rate Select Xilinx Tools > Program FPGA Browse and select system.bit and system_bd.bmm files from the C:\xup\embedded\labs\lab5\SDK\SDK_Export\lab1_hw_platform, and select bootloop as the application Click Program. This will execute Data2Mem program to combine the bootloop executable with hardware bitstream, generate the download.bit file, and configure the FPGA Launch Debugger and debug Right-click on the Lab5 project in the Project Explorer view and select Debug As > Launch on Hardware. The lab5.elf will be downloaded and a dialog box will appear to switch to the Debug perspective Click Yes to change to the Debug perspective Right click in the Variables tab and select Add Global Variables All global variables will be displayed. Select count variable and click OK Nexys

9 Lab Workbook Double-click to set a breakpoint on the line in lab5.c where count is written to LED in the interrupt handler. Figure 11. Setting breakpoint Click on Resume button to continue executing the program up until the breakpoint is reached. As you do step over, you will notice that the count variable value is changing Click on the memory tab. If you do not see it, go to Window > Show View > Memory Click the sign to add a Memory Monitor Figure 12. Adding memory address Enter the address for the count variable as follows, and click OK. Figure 13. Monitoring a memory address Click the Resume button to continue execution of the program. Nexys3 5-9

10 Lab Workbook Notice that the count variables increment every time you click resume. Watch count value increment Figure 14. Viewing Memory Content of the count variable Terminate the session by clicking on the Terminate button. Figure 15. Terminating a Debug Session Close the SDK application and close the XPS project Conclusion This lab led you through adding an AXI timer and interrupt controller, and assigning an interrupt handler function to the interrupting device through function calls. You developed an interrupt handler function and tested it in hardware. Additionally, you used the SDK debugger to view the content of variables and memory. Answers 1. What is the size of the compiled program?.text segment: data segment: 340.bss segment: 2162 Total in decimal: Total in hexadecimal: 3af4 Nexys

11 Lab Workbook Completed MHS File # ############################################################################## # Created by Base System Builder Wizard for Xilinx EDK 14.2 Build EDK_P.28xd # Wed Sep 19 09:57: # Target Board: digilent nexys3 Rev B # Family: spartan6 # Device: xc6slx16 # Package: csg324 # Speed Grade: -3 # ############################################################################## PARAMETER VERSION = PORT RS232_Uart_1_sout = RS232_Uart_1_sout, DIR = O PORT RS232_Uart_1_sin = RS232_Uart_1_sin, DIR = I PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 1 PORT GCLK = GCLK, DIR = I, SIGIS = CLK, CLK_FREQ = PORT dip_gpio_io_i_pin = dip_gpio_io_i, DIR = I, VEC = [7:0] PORT push_gpio_io_i_pin = push_gpio_io_i, DIR = I, VEC = [3:0] PORT led_ip_0_led_pin = led_ip_0_led, DIR = O, VEC = [7:0] BEGIN proc_sys_reset PARAMETER INSTANCE = proc_sys_reset_0 PARAMETER HW_VER = 3.00.a PARAMETER C_EXT_RESET_HIGH = 1 PORT MB_Debug_Sys_Rst = proc_sys_reset_0_mb_debug_sys_rst PORT Dcm_locked = proc_sys_reset_0_dcm_locked PORT MB_Reset = proc_sys_reset_0_mb_reset PORT Slowest_sync_clk = clk_100_0000mhz PORT Interconnect_aresetn = proc_sys_reset_0_interconnect_aresetn PORT Ext_Reset_In = RESET PORT BUS_STRUCT_RESET = proc_sys_reset_0_bus_struct_reset BEGIN lmb_v10 PARAMETER INSTANCE = microblaze_0_ilmb PARAMETER HW_VER = 2.00.b PORT SYS_RST = proc_sys_reset_0_bus_struct_reset PORT LMB_CLK = clk_100_0000mhz BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = microblaze_0_i_bram_ctrl PARAMETER HW_VER = 3.10.a PARAMETER C_BASEADDR = 0x PARAMETER C_HIGHADDR = 0x00003fff BUS_INTERFACE SLMB = microblaze_0_ilmb BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block BEGIN lmb_v10 PARAMETER INSTANCE = microblaze_0_dlmb PARAMETER HW_VER = 2.00.b PORT SYS_RST = proc_sys_reset_0_bus_struct_reset Nexys3 5-11

12 Lab Workbook PORT LMB_CLK = clk_100_0000mhz BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = microblaze_0_d_bram_ctrl PARAMETER HW_VER = 3.10.a PARAMETER C_BASEADDR = 0x PARAMETER C_HIGHADDR = 0x00003fff BUS_INTERFACE SLMB = microblaze_0_dlmb BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block BEGIN bram_block PARAMETER INSTANCE = microblaze_0_bram_block PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block BEGIN microblaze PARAMETER INSTANCE = microblaze_0 PARAMETER HW_VER = 8.40.a PARAMETER C_INTERCONNECT = 2 PARAMETER C_USE_BARREL = 1 PARAMETER C_USE_FPU = 0 PARAMETER C_DEBUG_ENABLED = 1 PARAMETER C_ICACHE_BASEADDR = 0X PARAMETER C_ICACHE_HIGHADDR = 0X3FFFFFFF PARAMETER C_USE_ICACHE = 0 PARAMETER C_ICACHE_ALWAYS_USED = 0 PARAMETER C_DCACHE_BASEADDR = 0X PARAMETER C_DCACHE_HIGHADDR = 0X3FFFFFFF PARAMETER C_USE_DCACHE = 0 PARAMETER C_DCACHE_ALWAYS_USED = 0 BUS_INTERFACE ILMB = microblaze_0_ilmb BUS_INTERFACE DLMB = microblaze_0_dlmb BUS_INTERFACE M_AXI_DP = axi4lite_0 BUS_INTERFACE DEBUG = microblaze_0_debug BUS_INTERFACE INTERRUPT = axi_intc_0_interrupt PORT MB_RESET = proc_sys_reset_0_mb_reset PORT CLK = clk_100_0000mhz BEGIN mdm PARAMETER INSTANCE = debug_module PARAMETER HW_VER = 2.10.a PARAMETER C_INTERCONNECT = 2 PARAMETER C_USE_UART = 1 PARAMETER C_BASEADDR = 0x PARAMETER C_HIGHADDR = 0x4140ffff BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug PORT Debug_SYS_Rst = proc_sys_reset_0_mb_debug_sys_rst BEGIN clock_generator PARAMETER INSTANCE = clock_generator_0 Nexys

13 Lab Workbook PARAMETER HW_VER = 4.03.a PARAMETER C_CLKIN_FREQ = PARAMETER C_CLKOUT0_FREQ = PARAMETER C_CLKOUT0_GROUP = NONE PORT LOCKED = proc_sys_reset_0_dcm_locked PORT CLKOUT0 = clk_100_0000mhz PORT RST = RESET PORT CLKIN = GCLK BEGIN axi_interconnect PARAMETER INSTANCE = axi4lite_0 PARAMETER HW_VER = 1.06.a PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0 PORT interconnect_aclk = clk_100_0000mhz PORT INTERCONNECT_ARESETN = proc_sys_reset_0_interconnect_aresetn BEGIN axi_uartlite PARAMETER INSTANCE = RS232_Uart_1 PARAMETER HW_VER = 1.02.a PARAMETER C_BAUDRATE = PARAMETER C_DATA_BITS = 8 PARAMETER C_USE_PARITY = 0 PARAMETER C_ODD_PARITY = 1 PARAMETER C_BASEADDR = 0x PARAMETER C_HIGHADDR = 0x4060ffff PORT TX = RS232_Uart_1_sout PORT RX = RS232_Uart_1_sin BEGIN axi_gpio PARAMETER INSTANCE = dip PARAMETER HW_VER = 1.01.b PARAMETER C_GPIO_WIDTH = 8 PARAMETER C_ALL_INPUTS = 1 PARAMETER C_BASEADDR = 0x PARAMETER C_HIGHADDR = 0x4000ffff PORT GPIO_IO_I = dip_gpio_io_i BEGIN axi_gpio PARAMETER INSTANCE = push PARAMETER HW_VER = 1.01.b PARAMETER C_GPIO_WIDTH = 4 PARAMETER C_ALL_INPUTS = 1 PARAMETER C_BASEADDR = 0x PARAMETER C_HIGHADDR = 0x4004ffff PORT GPIO_IO_I = push_gpio_io_i BEGIN led_ip Nexys3 5-13

14 Lab Workbook PARAMETER INSTANCE = led_ip_0 PARAMETER HW_VER = 1.00.a PARAMETER C_BASEADDR = 0x7f PARAMETER C_HIGHADDR = 0x7f40ffff PORT LED = led_ip_0_led BEGIN axi_bram_ctrl PARAMETER INSTANCE = axi_bram_ctrl_0 PARAMETER HW_VER = 1.03.a PARAMETER C_S_AXI_PROTOCOL = AXI4LITE PARAMETER C_S_AXI_BASEADDR = 0x PARAMETER C_S_AXI_HIGHADDR = 0x40051fff BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_bram_porta BUS_INTERFACE BRAM_PORTB = axi_bram_ctrl_0_bram_portb BEGIN bram_block PARAMETER INSTANCE = axi_bram_ctrl_0_bram_block_1 PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = axi_bram_ctrl_0_bram_porta BUS_INTERFACE PORTB = axi_bram_ctrl_0_bram_portb BEGIN axi_timer PARAMETER INSTANCE = delay PARAMETER HW_VER = 1.03.a PARAMETER C_ONE_TIMER_ONLY = 1 PARAMETER C_BASEADDR = 0x41c00000 PARAMETER C_HIGHADDR = 0x41c0ffff PORT Interrupt = delay_interrupt PORT CaptureTrig0 = net_gnd BEGIN axi_intc PARAMETER INSTANCE = axi_intc_0 PARAMETER HW_VER = 1.02.a PARAMETER C_BASEADDR = 0x PARAMETER C_HIGHADDR = 0x4120ffff BUS_INTERFACE INTERRUPT = axi_intc_0_interrupt PORT Intr = delay_interrupt Nexys