Design of NaviEngine - a SoC with MPCore - Oct. 2 nd, 2007 NEC Electronics Corp. Automotive System Div.

Transcription

1 Design of NaviEngine - a SoC with MPCore - Oct. 2 nd, 2007 NEC Electronics Corp. Automotive System Div. masa.yoshida@necel.com 1

2 Agenda Background Automotive Multimedia Markets Multicore Technology Concept of NaviEngine System solution Hardware Platform Software and tools Future roadmap 2

3 Future Car system More Comfort Safety Environment -easy and fun to to drive -safety and relax -Earth friendly Comfort Entertainment (Video and Audio) ITS (VICS/DSRC/WAN/LAM) Easy user Interface Security Driver assist Camera and recognition Pre clash safety air bag control emergency alert Evolution in Car for better Society Safety Fuel cell car Hybrid car Traffic jam free Environment 3

4 1000 MIPS 100 MIPS Evolution of Car Infotainment Systems Navigation Entertainment Driver assistance Intelligent Car Brain of Car, face to driver and passenger MIPS Navigation 2D mapping Route detect Multiple application combined in single unit. Voice TV Phone Camera Browser Mail Image recognition Digital TV 3D Graphics Navigation JAVA Multimedia 3D mapping Entertainment Speech UI Speech Recognition Security Now=600MIPS Driver assist Pre-crash safety ITS Intelligent car Auto Drive ECU integration Body ECU, Engine ECU Future =20,000MIPS Next Gen=2,000MIPS

5 Requirement for 1 Low Power for In dashboard Embedded product power range 0.1W Mobile Embedded PC & Server 1W 10W 100W 2 High performance Over 1000MIPS UI Traffic info Digital TV Vision recog Navigation 80MIPS 100MIPS 200MIPS 400MIPS 400MIPS 3 Easy to use Real-time response for UI Beep! Car approaching Hey, where it is? 4 Many Products for Many country Minimize design cost and resouce Car Maker A Asia Europe US Car Maker B Asia Europe US 5

6 Merit of Muticore:High performance and low power Power Consumption High 1 Low core (NEC Electronics estimate) Parallel processing technology Relationship between processing speed and power consumption Single high frequency Speed up Parallel processing 2 core Low Power 3 core Multi Processor Performance (MIPS) Increase frequency Larger power consumption Parallel processing Improved power consumption 6

7 Merit of Multicore: Real Time Response The real-time response is improved by dispatch tasks to individual s. Total Task time Scheduling Real-time Single Task#A Task#B Task#C a1 a2 b1 Data dependency t Time slice of scheduling tasks is bottle neck of response. Multi a1 a2 b1 Overhead for inter-task communication t If there are free, task can be dispatched with minimum overhead. Or, dispatch task statically with specific to zero overhead. 7

8 Scalable Platforms Scalable architecture built on parallel processing technology and media processing technology Best balance for Power, performance and cost Scalable High Application SW for single designs can also be used for multiple designs Camera I/F Mem. Main bus LCD I/F MM Mem. Rich graphics Scalable Sharing of functions and loads Low Memory Camera I/F Main bus LCD I/F Standard graphics Select number of s based on balance between need for power consumption and performance Simple functions Complex functions 8

9 NEC s Multicore Technology NEC has over 10 year history and expertise in Multicore technology R&D for embedded market. 2000, MP98 announcement SMP technology Media Parallel IMAP 8SIMD Core Parallel S/W MPcore 16 Cores on Chip =128Processor (Sept. 2004) PE0 PE2 MP98 Technology: 1. High performance on-chip multicore design 2. Low power consumption with adaptive shutdown SPX K602 DSP PE0 Logic1 SRAM Logic 0 PE1 PE2 PE1 SCU PE3 (June 2005) NaviEngine1 MPCore 2D/3D IOs LCDC 3. Software technology to hide complexity of multicore. MP211 (Jan. 2005) 9

10 Strategic Collaboration In 2003, ARM and NEC Electronics established a strategic collaboration for next generation core development. ARM ARM ARM11 TM core Widely-deployed ARM family with rich line-up of software and development environments NEC NEC Electronics Multiprocessing technology High performance and low power LSI design technology Collaboration 1. Next generation parallel core co-development and co-marketing 2. Fundamental software development Next-Generation Multiprocessor 0 1 FPU SCU st result: MPCore TM 10

11 Product definition: Concept of NaviEngine 1 st product to use NaviEngine Architecture ARM SMP: Multicore for scalability AXI and MBus: High performance bus interconnect SGX: Embedded 2D/3D Graphics capability On-chip multiple IOs (LCDC, SATA, etc.) Establish NaviEngine platform Multicore ICE and OS will be prepared Software (Middleware and application) development bench 11

12 Application System block diagram NTSC Hands free mic AMP SW AMP USB2.0 Tuner/DSP Acoustic Tuner Calibration System controller Micro controller Audio router USB Audio CAN/LIN Flexray Audio Processor Ripping CD compressed DRAM NaviEngine Speech recognition Vision recognition Video capture Navigation Digital TV DRAM connectivity Sensor GPS Enter -tainment 2D/3D mapping LCD output WiFi,CDMA ATA SATA RGB Key(GPIO) VICS GPS SDcard DVD HDD 12

13 Internal Block Diagram HDD CD/DVD MPCore TM 400MHz x 4 64 AXI 64b@133MHz SGX 535 Local Memory 1KB DMAC64 Video 133MHz Display 133MHz AXI-I/F 64/128b@133MHz MBUS 128b@133Mz DDR port I/F with DLL 32 to DRAM SATA AXI64AHB IOBRG DMAC32 DMAC32 DMAC32 ATA6 AHB32PCI DMAC32 EXBUS x4 128 AHB 32b@133Mz TS I/F 133MHz USBH 2 port 32 from OFDM AHB32APB SD PWM WDT Timer x 6 GPIO APB 32b@66Mz 32 CF I2C SPDIF i SPDIF o I2S x 4 UART x 8 CSI NAND SYSCTRL 13

14 NaviEngine Specification overview power supply(vdd) 1.0V 1.8V 3.3V power consumption (PD) 5W (T.B.D.) storage temperature (TST) - 65~125 operative temperature (Tc) - 40~105 ( )The measurement point of Tc is the center of lid. 720pin( 0.8mm )FCBGA Function contents MPCore(ARM11 4) 400MHz, with VFP11 i-cache/d-cache Local Memory 32kbyte/32kbyte 1kbyte Others MMU JAVA accelerator memory Memory controller DDR2(533 32bit) Graphics 2D/3D SGX535 (8Mline/s,15Mpoly/s, 800M pix/sec) Display Controller W-SVGA 7 layer(max) Peripherals Video Capture ITU-R BT.601/ITU-R BT.656 RGB565/RGB888 Others USBH2.0, SATA/ATA, UART. CSI. SPDIF. I2S, etc. 14

15 Software development platform General purpose software development platform for NaviEngine Not for Hardware evaluation Design for typical use-case only Low cost, easy to use Small foot print for desk top work Software Dev Platform Compliant for T-Engine design Plug in board and peripherals will be available. 15

16 System Performance Improvement Three bottlenecks in multiprocessing Sequential Part Load imbalance Communication overhead Example: System activity consists of 4 tasks (or 4 threads) Time Sequential Processing Parallel Processing on Small gain by low utilization Sequential Part Load Imbalance Communication overhead 16

17 System Performance Improvement (cont d) Performance Analysis and Tuning Existing application set Run existing application set on SMP OS (If the sequential part is small or load is well balanced we will get enough performance.) Relax the synchronization point of sequential part by modifying algorithm, etc. - Tune the communication code. 1a 1b 1d 1c 1e Find the key components (e.g. 1) and restructure it with multithreading. Profiling tool is useful for the tuning. 17

18 Summary Car Navigation will evolve to Brain in the car with performance improvement. Multicore is Key factor to realize such high performance as in-car system Prepare to support Multicore will take advantage for coming business in embedded electronics NEC will provide semiconductor platform to open the door for this. Thank you! 18

19 [Note] NaviEngine is a registered trademark of NEC Electronics Corporation in Japan. All other trademarks are the properties of their respective owners. 19