CS8416 Delivers Performance Gains Over CS8413/14

Transcription

1 N339 CS8416 Delives Pefomance Gains Ove CS8413/14 1. INTRODUCTION by Jonathan Schwatz The CS8413/14 S/PDIF eceives have long hel a position of espect as the inusty-favoe eceives fo ecovee clock quality. s of ealy 2009, an upcoming en-of-life of these poucts has many system esignes woneing what thei next move will be, an whee they ll go to get the level of pefomance they ve become accustome to. Othes simply nee 192 k suppot, which the CS8413/14 oes not povie. Satisfying both of these equiements, Cius Logic offes the CS8416 S/PDIF eceive with new featues an lowe ecovee clock jitte than the CS8413/14. When the CS8416 was fist elease in 2002, it use a phase etecto scheme that esulte in highe ecovee clock jitte compae to the CS8413/14. To impove on its pefomance an follow in the taition of the CS8413/14, a new phase etecto option was ae to the CS8416 in This new option offes even lowe ecovee clock jitte than the CS8413/14 an esults in measuably impove auio pefomance as shown in Figue 1. This application note etails how the CS8416 impoves upon the pefomance of the CS8413/14. summay of impotant functional iffeences an etaile jitte an auio pefomance measuements ae inclue to clealy emonstate the impovements that can be expecte when tansitioning to the CS SUMMRY OF IMPROVEMENTS CS8416 Figue 1. DC THD+N Many impovements wee mae in the geneational leap fom the CS8413/14 to the CS8416. Fo efeence, some of the high-level impovements ae summaize in the table below. Fo moe infomation, please efe to each evice s atasheet. Paamete CS8413/14 CS8416 Unit Maximum Sample Rate k aseban Jitte (Note 1) (Note 2) ps Logic Supply Voltage Range V Powe Supply Consumption mw ack-up System Clock Duing Receive Eo None OMCK pin - Receive Input Pins 1 8 in SW Moe, 4 in HW Moe - Deicate Reset Pin None Yes - Contol Pot Potocol Paallel Pot, CS8413 Only I²C an SPI - Table 1. Summay of CS8416 Impovements Notes: 1. Values liste ae fom expeiment esults. See Section 5 2. PDUR=1. See Section 3 Copyight Cius Logic, Inc (ll Rights Reseve) JUL '09 N339REV1

2 N339REV1 N339 eyon those liste in the table, seveal othe notable enhancements ae available in the CS8416: Geneal Enhancements Optional automatic enable of e-emphasis filte base on channel status bits. Deicate S/PDIF eceive pass-though pin. Selectable ecovee maste clock fequency of 256 x Fs o 128 x Fs. SOIC, TSSOP, an QFN package options. vailable in automotive gae. Softwae Moe Enhancements Thee configuable GPO pins. Data output muting capability. Data fomat etection an epoting. Channel status egiste upate inhibit function. Use ata Q-channel subcoe ecoing into egistes. IEC61937 Pc/P bust peamble egistes. Thee ae a numbe of othe iffeences between the CS8413/14 an the CS8416 that a esigne consieing a tansition fom the CS8413/14 to the CS8416 shoul be awae of. Fo efeence, a list of some of the moe significant iffeences is inclue in Section9.1 on page SICS OF CLOCK RECOVERY The pupose of a S/PDIF eceive is to convet a 1-wie S/PDIF input signal containing both clock an ata infomation into iscete seial auio clock an ata signals. phase-locke loop (PLL) is use to eive a system clock signal synchonous to the S/PDIF steam, an igital logic is use to ecoe the ata. In some limite applications, a S/PDIF eceive is use to souce ata into a puely igital system whee clock jitte nees to be only goo enough to opeate the intenal igital components. Howeve, the vast majoity of systems with a S/PDIF eceive also contain a D/ convete, an /D convete, o a combination of the two, all being clocke by the PLL ecovee system clock geneate by the S/PDIF eceive. In these systems, the jitte pefomance of the S/PDIF ecovee clock is of exteme impotance because it has a iect impact on the system s analog auio pefomance. Input Phase Compaato LPF VCO Recovee Maste Clock s a esult, an impotant qualifying facto fo a S/PDIF eceive is the pefomance of its ecovee clock. If the S/PDIF eceive oes not povie a low-jitte ecovee clock, then any convetes that use the clock fo sampling can be expecte to exhibit euce pefomance as a esult. The basic block iagam of the PLL is shown in Figue 2. The PLL uses a negative feeback loop N to compae the phase of the input clock to that of the output clock. The esulting eo voltage signal is low pass filtee an sent to an intenal volt- Figue 2. PLL lock Diagam age-contolle oscillato (VCO). The VCO output clock fequency is ajuste by the eo signal voltage until the output clock fequency matches the input. The feeback loop contains a fequency ivie so that the output clock fequency can be a multiple of the input fequency. The amount of jitte pesent on the ecovee clock is epenent on the chaacteistics of the PLL that geneates the clock. Since the CS8413/14 an CS8416 have iffeent PLLs, the jitte on thei ecovee clocks is expecte to be iffeent as iscusse in the following section. 2 N339REV1

3 N339REV1 N CS8413/14 ND CS8416 CLOCK RECOVERY COMPRED The pimay iffeence between the CS8413/14 an CS8416 PLLs is foun in the input souce to each PLL s phase etecto block. In each of these evices, igital logic analyzes the incoming biphase encoe S/PDIF steam to geneate pulses that seve as the input to the phase compaato. The fequency of these pulses is efee to as the phase etecto upate ate. The moe often the phase etecto is upate, the moe often the VCO output fequency is coecte to match the fequency of the input S/PDIF signal. slowe upate ate allows the VCO fequency a geate egee of wane, leaing to incease low fequency (auio-ban) ecovee clock jitte. See Figue 3 an Figue 4. VCO Fequency (M) VCO Jitte Ieal VCO Fequency In pactice, the CS8413/14 etecto is upate once pe bit of the input S/PDIF signal; thus the upate ate is ata epenent 64 times the input sample ate. With an upate ate of this fequency, the CS8413/14 has goo auio-ban output jitte. Phase Detecto Upate Rate Time (secons) Figue 3. Slow Phase Detecto Upate Rate When the CS8416 was fist elease in 2002, its igital logic was esigne to upate its phase etecto only once pe subfame of the S/PDIF input signal, o at 2 times the input sample ate. This was one as a measue esigne to suppot 192 k sample ates an to euce ata epenency. The unfotunate esult of this slowe upate ate was highe auio-ban jitte pesent on the ecovee maste clock. To aess this issue an impove upon the CS8416 an CS8413/14, in 2004 a new phase etecto upate ate option was ae to the CS8416. When enable, the newe upate ate option causes the phase etecto to be upate on evey ege of the biphase S/PDIF input signal; thus the upate ate is ata epenent fom 64 to 128 times the input sample ate. This new etecto lowes the auio-ban ecovee clock jitte an esults in impove convete pefomance. It s impotant to note that the maximum sample ate is Figue 4. Fast Phase Detecto Upate Rate limite to 108 k in this newe moe. The iffeent etecto moes in the CS8416 ae selecte by the Phase Detecto Upate Rate (PDUR) contol. PDUR set low ( 0 ) selects the oiginal an slowe upate ate, while PDUR set high ( 1 ) selects the new fast upate ate. The PDUR setting can be accesse at stat-up though the TX pin in hawae moe, o in egiste 00h in softwae moe. Since the CS8416 with PDUR = 1 has the same upate ate o faste than the CS8413/14, the CS8416 is expecte to have lowe auio-ban ecovee clock jitte. Section 5 below etails the esults of jitte measuement tests that empiically suppot this conclusion. 5. MESURED JITTER COMPRISON VCO Fequency (M) Phase Detecto Upate Rate Time (secons) Ieal VCO Fequency lthough thee ae seveal iffeent jitte specifications use to quantify the jitte pesent on a clock signal (peio, cycle-to-cycle, etc.), they ae not all useful fo coelating measue jitte to the THD+N pefomance of an auio convete that uses the measue clock signal to ive its sampling cicuits. The best jitte specification fo this coelation is baseban jitte as efine in section of ES-12i06. baseban jitte measuement ban-passes the measue jitte signal, calculating the jitte amplitue ove a fequency ban fom 100 to 40 k. Jitte outsie of this fequency ban is sai to have no effect on the THD+N pefomance of an auio convete because the esulting moulation tones will eithe be psycho-acoustically maske (jitte less than 100 ) o highe than the uppe limit of the 20 k auio ban (jitte geate than 40 k). VCO Jitte N339REV1 3

4 N339REV1 N339 Each eceive, incluing both of the CS8416 phase etecto upate moes, was teste with input S/PDIF sample ates at common values of 48 k an 96 k. itionally, the CS8416 was teste at 192 k with PDUR = 0. The esulting baseban jitte measuement ata is pesente in Table 2. Phase noise plots showing the measue jitte signal on the eceives ecovee clocks ae isplaye in Figues 5 though 11. Refe to Section 9.2 fo etaile test set-up infomation an iagams. Sample Rate - 48 k (Figue 5) 96 k (Figue 6) CS8416 PDUR= (Figue 7) (Figue 8) CS8416 PDUR= (Figue 9) (Figue 10) 192 k (Figue 11) Table 2. aseban Jitte - Summay Unit ps ps ps The highlighte potions of each plot enote the 100 to 40 k banwith specifie by the ES-12i06 baseban jitte efinition. s the efinition suggests, the magnitue of the highlighte potion of the plots coelate to auio-ban convete THD+N pefomance. Thus, the lowe the magnitue, the bette the convete pefomance. Figue 5. MCK Phase Noise Fs = 48 k Figue 6. MCK Phase Noise Fs = 96 k Figue 7. CS8416 RMCK Phase Noise Fs = 48 k, PDUR = 1 Figue 8. CS8416 RMCK Phase Noise Fs = 96 k, PDUR = 1 Figue 9. CS8416 RMCK Phase Noise Fs = 48 k, PDUR = 0 Figue 10. CS8416 RMCK Phase Noise Fs = 96 k, PDUR = 0 4 N339REV1

5 N339REV1 N339 Figue 11. CS8416 RMCK Phase Noise Fs = 192 k, PDUR = 0 upate ate esults in euce low fequency VCO noise on the ecovee clock. The measuements show the CS8416 has less baseban jitte than the when PDUR = 1. While the plots also inicate that the CS8416 has moe jitte at highe fequencies, as suggeste by ES-12i06 an confime by the measuements to be shown in Section 6, this high fequency jitte oes not affect auio convete THD+N pefomance. It can also be seen that the CS8416 has highe baseban jitte when PDUR = 0; this is ue to its slowe phase etecto upate ate in this moe. s an altenate illustation of this point, notice that the baseban jitte is euce fo all thee eceive cases when the sample ate is incease. This is an inication that a faste phase etecto 6. MESURED CONVERTER PERFORMNCE COMPRISON n altenate, an aguably moe tangible way to evaluate the impact of the ecovee clock jitte impovement povie by the CS8416 woul be to simply measue the analog pefomance of a D/ convete clocke by the eceive s ecovee clock. The esults fom a few of these tests have been inclue to povie an example of how the impovements mae in the CS8416 will benefit a eal-wol auio application. Fom a high-level, it s easy to see that the impove jitte pefomance esults in bette THD+N pefomance of the convete; see Table 3. Detaile plots an summay ata can be foun in the next few sections. These epesent the most common an citical analog pefomance metics that can be expecte to be affecte by clock jitte. The CS4398 high-pefomance D/ convete was use as the auio souce fo each measuement. Thee common sample ates wee teste fo each measuement: 48 k, 96 k, an 192 k. Since the cannot accept a sample ate of 192 k, pefomance ata fo the opeation at 48 k is use as a compaison baseline fo the plots emonstating the CS8416 opeation at 192 k. Refe to Section 9.2 fo etaile test set-up infomation an iagams. 6.1 THD+N Measuements Table 3 summaizes the pefomance iffeences, which ae clealy most notable at 18 k. The plots that follow show that the THD+N pefomance egaes as the signal amplitue an fequency ae incease. s peicte by the baseban jitte values in Section 5, the convete s pefomance impoves as the sample ate is incease fom 48 k to 96 k when souce by eithe eceive. It s also notewothy that the pefomance with the CS8416 an PDUR = 0 at a sample ate of 192 k is compaable to the pefomance with the at a sample ate of 48 k. This shows that using the extene sample ate ange of the CS8416 oesn t come at the expense of pefomance elative to the benchmak set by the. Funamental Fequency Sample Rate THD+N - CS8416 THD+N PDUR=1 CS8416 THD+N PDUR=0 Unit Figue k k k k 48 k k 96 k k 192 k Table 3. THD+N Summay N339REV1 5

6 N339REV1 N Figue 12. THD+N vs Fequency - 0 FS Fs = 48 k FS Figue 13. THD+N vs mplitue - 18 k Fs = 48 k Figue 14. THD+N vs Fequency - 0 FS Fs = 96 k FS Figue 15. THD+N vs mplitue -18 k Fs = 96 k -65 (48 k) -65 (48 k) Figue 16. THD+N vs Fequency - 0 FS Fs = 192 k FS Figue 17. THD+N vs mplitue - 18 k Fs = 192 k 6 N339REV1

7 N339REV1 N Full-Scale FFTs FFTs of the 997 an 18 k test cases ae povie below. These show the iffeences in the tonal an noise signatues of the convetes when clocke fom the CS8413/14 an the CS8416 in each PDUR moe. Figue 18. FFT - 0 FS, 997 Fs = 48 k Figue 19. FFT - 0 FS, 18 k Fs = 48 k Figue 20. FFT - 0 FS, 997 Fs = 96 k Figue 21. FFT - 0 FS, 18 k Fs = 96 k (48 k) (48 k) Figue 22. FFT - 0 FS, 997 Fs = 192 k Figue 23. FFT - 0 FS, 18 k Fs = 192 k N339REV1 7

8 N339REV1 N Dynamic Range Measuements s iscusse in section 5.2 of ES-12i06, jitte outsie of the baseban fequency ange can inteact with the shape quantization noise of an auio convete an esult in ecease ynamic ange egaless of the level o fequency of the auio input signal. The level of ynamic ange euction is epenent upon the out of ban enegy of the convete an the out of ban jitte signal on its sample clock. Since the peominant multi-bit convete achitectues of toay pouce less out of ban enegy than ealie convetes using a single-bit achitectue, they can be expecte to be less sensitive to out of ban jitte. The measuements eveal that thee is little iffeence between the convete s ynamic ange when souce by each ecovee clock souce. Thee is a small euction in ynamic ange fo the CS8416 an PDUR = 1 case that can be attibute to the RMCK jitte in the ~100 k ange as shown in Figue 7. Table 4 summaizes the measuement esults. The plots that follow show the convete s output spectum fo each sample ate, both acoss the auio ban with a input stimulus, an out of the auio ban with no input stimulus. Sample Rate - CS8416 PDUR=1 CS8416 PDUR=0 Unit Figue 48 k k k Table 4. -Weighte Dynamic Range Summay Figue 24. FFT - FS, 997 Fs = 48 k 20k 40k 60k 80k 100k Figue 25. FFT - No Input (w/ Dithe) Out of an, Fs = 48 k 120k Figue 26. FFT - FS, 997 Fs = 96 k 20k 40k 60k 80k 100k Figue 27. FFT - No Input (w/ Dithe) Out of an, Fs = 96 k 120k 8 N339REV1

9 N339REV1 N339 (48 k) (48 k) Figue 28. FFT - FS, 997 Fs = 192 k 20k 40k 60k 80k 100k Figue 29. FFT - No Input (w/ Dithe) Out of an, Fs = 192 k 120k 7. JITTER MESUREMENT TO DC THD+N CORRELTION The esults pesente in Section 5 show that the amount of baseban jitte pesent on the ecovee maste clock of each eceive is euce as the sample ate of the input S/PDIF signal is incease. This elationship is a iect esult of the incease phase etecto upate ate, which is popotional to the incoming sample ate. lso, the esults of Section 6 show that baseban jitte pesent on the ecovee maste clock has the most significant affect on the convete s THD+N pefomance when its auio input signal level an fequency ae both high. Using this infomation, a simple test was evise to help coelate the level of baseban jitte to the DC s THD+N. To o this, a S/PDIF signal with a fixe 0 FS, 18 k auio tone was tansmitte into both eceives. The sample ate of the S/PDIF signal was then vaie, an both the ecovee clock baseban jitte an the THD+N of the CS4398 wee measue at each sample ate step. The esults ae shown in Figue 30 an Figue 31 below aseban Jitte (ps) k THD+N () Fs (k) Fs (k) Figue 30. aseban Jitte vs Sample Rate Figue 31. THD+N vs Sample Rate The plots confim the elationship between ecovee clock baseban jitte an DC THD+N. It can again be seen that the baseban jitte an THD+N fo the CS8416 when PDUR = 1 is bette than that with the. Fo sample ates geate than 96 k (up to 192 k), the jitte an THD+N fo the CS8416 with PDUR = 0 is compaable to the pefomance of the with a sample ate of 48 k. N339REV1 9

10 N339REV1 N CONCLUSION The CS8416 offes many impovements an featues beyon those of the CS8413/14. One of the CS8416 s pimay impovements is the euction of baseban jitte on its ecovee maste clock. s shown though expeiment, this jitte euction impoves the THD+N pefomance of a convete souce by the CS8416 when compae to the same convete souce by the CS8413/14. This emonstation suppots the CS8416 as a pefomance-enhance eplacement fo existing CS8413/14 esigns. 9. PPENDIX 9.1 Othe Diffeences etween CS8413/14 an CS8416 sie fom those liste in Section 2 on page 1, thee ae a numbe of othe iffeences between the CS8413/14 an the CS8416 that a esigne consieing a tansition fom the CS8413/14 to the CS8416 shoul be awae of. Fo efeence, a list of some of the moe significant iffeences is inclue below. Fo complete etails on any of these, please efe to each evice s atasheet. The CS8416 is not pin compatible with the CS8413/14. The CS8416 eceive input pins ae not RS-422 compliant; the eceive input absolute maximum voltage ange is ±12 V fo the CS8413/14 an -0.3 V to VL V fo the CS8416. The typical V an VD supply voltages ae 5 V fo the CS8413/14 an 3.3 V fo the CS8416. The extenal PLL filte component values ae iffeent between the CS8416 an CS8413/14. The ecovee clock fequency povie when the PLL is unlocke is appoximately 3 M fo the CS8413/14 an appoximately 375 k o 750 k fo the CS8416, epening upon the selecte RMCK atio. The CS8416 ecovee clock output pin is not active uing eset. Thee ae vaious iffeences between the evices C an U ata faming implementations. The evices inicate thei input sample ate iffeently. lthough typical I²S, Left-Justifie, an Right- Justifie fomats ae suppote by the evices, thee ae vaious iffeences in othe suppote seial auio output fomats. The available contols ove the state of the seial ata output uing a eceive eo conition ae iffeent. Thee ae vaious iffeences in the opeation of the evices eo inication pins. Cetain pins eicate to the epoting of the C ata bits on the ae not available in the CS8416 s hawae moe. The CS8413 is not iectly egiste-compatible with the CS8416 in softwae moe. The fist five bytes of both channels C ata ae egiste accessible in the CS8416 s softwae moe, while the CS8413 allows sequential 1- byte access to all 24-bits of a single channel s C ata. Thee ae vaious iffeences in the behavio of the CS8413 an CS8416 s inteupt functions. 9.2 System Set-Up The ata pesente in this ocument is eive fom measuements collecte using one anomly selecte sample of each evice. Measuements wee taken at each evice s nominal voltage an at oom tempeatue. Specifically, the Revision an the CS8416 Revision E wee use. To collect the auio pefomance ata, the CS4398 high-pefomance DC was chosen to emonstate the effect of each eceive s output jitte. single CD4398 custome evaluation boa was use to conuct each test. The CS4398 FILT+ capacito on the CD4398 was incease fom 100 µf to 1000 µf to ensue a flat low-fequency THD+N esponse. The locate on the CD4398 was use fo all measuements souce by the, an a CD8416 custome evaluation boa was use to ive the CS N339REV1

11 N339REV1 N339 on the CD4398 fo all measuements souce by the CS8416. Refe to the CD4398 an CD8416 ata sheets fo moe infomation on each evaluation boa. lock iagams of each test set-up ae shown in Figue 32 an Figue 33. n uio Pecision (P) SYS-2722 high-pefomance auio analyze was use to geneate the igital input signals fo the eceives an to measue the analog output signals fom the CS4398. gilent E3631 powe supplies wee use to powe the evaluation boas. Tektonix DPO7054 oscilloscope with JIT3 softwae was use to measue the jitte signal of the an CS8416 s ecovee maste clocks. The softwae was configue to geneate phase noise plots with no aveaging applie to pouce the figues shown in Section 5. The phase noise integation function was use to calculate the baseban jitte values shown in Table 2. Fo each plot shown, the blue taces epesent ata taken using the as the clock an ata souce, the geen taces with the CS8416 an PDUR=1 as the clock an ata souce, an the e taces with the CS8416 an PDUR=0 as the clock an ata souce. Fo claity, only OUT is shown in the plots; no notable iffeences wee seen between the CS4398 output channels. gilent E3631 Powe Supply +5V GND +18V -18V P SYS-2722 S/PDIF OUTPUT J17 S/PDIF INPUT J6 U2 J8 J10 J9 U9 CS4398 J18 OUT OUT P SYS-2722 LNCED NLOG INPUT CD4398 J27 Tektonix Oscilloscope Figue 32. Test Setup gilent E3631 Powe Supplies +5V GND +5V GND +18V -18V P SYS-2722 S/PDIF OUTPUT J9 S/PDIF INPUT J3 J4 U19 CS8416 J18 PCM OUTPUT J6 J12 PCM INPUT J8 J10 J9 U9 CS4398 J18 OUT OUT P SYS-2722 LNCED NLOG INPUT J27 CD8416 CD4398 Tektonix Oscilloscope Figue 33. CS8416 Test Setup N339REV1 11

12 N339REV1 N Test Conitions Fo all tests, unless othewise state: CS4398 V = VREF = VD = VLS = VLC = 5 V; PCM ata is 24 bit I 2 S fomat; 22 to 20 k measuement banwith fo THD+N an ynamic ange values. The unit is efeence to the measue 997 full scale output voltage of the CD4398, which was measue at 2.41 V RMS. The S/PDIF input signal amplitue is 0.5 Vpp with 24-bit esolution. V = VD = 5 V. CS8416 V = VD = 3.3 V; VL = 5 V. The bin with is 2 fo all of the FFT plots, with the exception of Figues 25, 27 an 29, which have a bin with of REFERENCES 1. uio Engineeing Society ES-12i06: ES Infomation Document fo igital auio measuements - Jitte pefomance specifications, May REVISION HISTORY Revision Date Changes REV1 JUL 2009 Initial Release Contacting Cius Logic Suppot Fo all pouct questions an inquiies contact a Cius Logic Sales Repesentative. To fin one neaest you go to IMPORTNT NOTICE Cius Logic, Inc. an its subsiiaies ( Cius ) believe that the infomation containe in this ocument is accuate an eliable. Howeve, the infomation is subject to change without notice an is povie S IS without waanty of any kin (expess o implie). Customes ae avise to obtain the latest vesion of elevant infomation to veify, befoe placing oes, that infomation being elie on is cuent an complete. ll poucts ae sol subject to the tems an conitions of sale supplie at the time of oe acknowlegment, incluing those petaining to waanty, inemnification, an limitation of liability. No esponsibility is assume by Cius fo the use of this infomation, incluing use of this infomation as the basis fo manufactue o sale of any items, o fo infingement of patents o othe ights of thi paties. This ocument is the popety of Cius an by funishing this infomation, Cius gants no license, expess o implie une any patents, mask wok ights, copyights, taemaks, tae secets o othe intellectual popety ights. Cius owns the copyights associate with the infomation containe heein an gives consent fo copies to be mae of the infomation only fo use within you oganization with espect to Cius integate cicuits o othe poucts of Cius. This consent oes not exten to othe copying such as copying fo geneal istibution, avetising o pomotional puposes, o fo ceating any wok fo esale. CERTIN PPLICTIONS USING SEMICONDUCTOR PRODUCTS MY INVOLVE POTENTIL RISKS OF DETH, PERSONL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTL DMGE ( CRITICL PPLICTIONS ). CIRRUS PRODUCTS RE NOT DESIGNED, UTHORIZED OR WRRNTED FOR USE IN PRODUCTS SURGICLLY IMPLNTED INTO THE ODY, UTOMOTIVE SFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICL PPLICTIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH PPLICTIONS IS UNDERSTOOD TO E FULLY T THE CUSTOMER'S RISK ND CIRRUS DISCLIMS ND MKES NO WRRNTY, EXPRESS, STTUTORY OR IMPLIED, INCLUDING THE IMPLIED WRRNTIES OF MERCHNT- ILITY ND FITNESS FOR PRTICULR PURPOSE, WITH REGRD TO NY CIRRUS PRODUCT THT IS USED IN SUCH MNNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICL PPLICTIONS, CUSTOMER GREES, Y SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIUTORS ND OTHER GENTS FROM NY ND LL LIILITY, IN- CLUDING TTORNEYS' FEES ND COSTS, THT MY RESULT FROM OR RISE IN CONNECTION WITH THESE USES. Cius Logic, Cius, an the Cius Logic logo esigns ae taemaks of Cius Logic, Inc. ll othe ban an pouct names in this ocument may be taemaks o sevice maks of thei espective ownes. gilent is a egistee taemak of gilent Technologies, Inc. Tektonix is a egistee taemak of Tektonix, Inc. uio Pecision an the P logo esign ae egistee taemaks of uio Pecision, Inc. 12 N339REV1