CDB4385. Evaluation Board for CS4385. Description. Features. Hardware or Software Board Control. Inputs for PCM Clocks and Data

Transcription

1 CD4385 Evaluation oa fo CS4385 Featues Desciption Demonstates ecommene layout an gouning aangements CS8416 eceives S/PDIF, & EIJ-340 compatible igital auio Heaes fo extenal auio input fo eithe PCM o DSD Requies only a igital signal souce an powe supplies fo a complete igital-to-analog convete system The CD4385 evaluation boa is an excellent means fo quickly evaluating the CS bit, 48-pin, 8- channel D/ convete. Evaluation equies an analog signal analyze, a igital signal souce, a PC fo contolling the CS4385 (only equie fo contol pot moe), an a powe supply. nalog line-level outputs ae povie via RC phono jacks. The CS8416 igital auio eceive IC povies the system timing necessay to opeate the igital-to-analog convete an will accept S/PDIF an EIJ-340-compatible auio ata. The evaluation boa may also be configue to accept extenal timing an ata signals fo opeation in a use application uing system evelopment. ORDERING INFORMTION CD4385 Evaluation oa Inputs fo PCM Clocks an Data Hawae o Softwae oa Contol CS8416 Digital uio Inteface CS4385 nalog Outputs an Filteing Inputs fo DSD Clocks an Data Copyight Cius Logic, Inc (ll Rights Reseve) MY '08 DS671D4

2 TLE OF CONTENTS CD CS4385 DIGITL-TO-NLOG CONVERTER CS8416 DIGITL UDIO RECEIVER INPUT FOR CLOCKS ND DT INPUT FOR CONTROL DT POWER SUPPLY CIRCUITRY GROUNDING ND POWER SUPPLY DECOUPLING NLOG OUTPUT FILTERING PERFORMNCE PLOTS SCHEMTICS ERRT REVISION HISTORY LIST OF FIGURES Figue 1.FFT (48 k, 0 )... 7 Figue 2.FFT (48 k, )... 7 Figue 3.FFT (48 k, No Input)... 7 Figue 4.FFT (48 k Out-of-an, No Input)... 7 Figue 5.FFT (48 k, Wieban)... 8 Figue 6.FFT (IMD 48 k)... 8 Figue 7.48 k, THD+N vs. Input Feq... 8 Figue 8.48 k, THD+N vs. Level... 8 Figue 9.48 k, Fae-to-Noise Lineaity... 8 Figue k, Fequency Response... 8 Figue k, Cosstalk... 9 Figue k, Impulse Response... 9 Figue k, Impulse Pefilte... 9 Figue 14.Dynamic Range 48 k Figue 15.FFT (96 k, 0 ) Figue 16.FFT (96 k, ) Figue 17.FFT (96 k, No Input) Figue 18.FFT (96 k Out-of-an, No Input) Figue 19.FFT (96 k, Wieban) Figue 20.FFT (IMD 96 k) Figue k, THD+N vs. Input Feq Figue k, THD+N vs. Level Figue k, Fae-to-Noise Lineaity Figue k, Fequency Response Figue k, Cosstalk Figue k, Impulse Response Figue k, Impulse Pefilte Figue 28.Dynamic Range 96 k Figue 29.FFT (192 k, 0 ) Figue 30.FFT (192 k, ) Figue 31.FFT (192 k, No Input) Figue 32.FFT (192 k Out-of-an, No Input) Figue 33.FFT (192 k, Wieban) Figue 34.FFT (IMD 192 k) Figue k, THD+N vs. Input Feq Figue k, THD+N vs. Level Figue k, Fae-to-Noise Lineaity Figue k, Fequency Response DS671D4

3 CD4385 Figue k, Cosstalk Figue k, Impulse Response Figue k, Impulse Pefilte Figue 42.Dynamic Range 192 k Figue 43.System lock Diagam an Signal Flow Figue 44.CS Figue 45.nalog Outputs Figue 46.nalog Outputs Figue 47.nalog Outputs Figue 48.nalog Outputs Figue 49.CS8416 S/PDIF Input Figue 50.PCM Input Heae an Muxing Figue 51.DSD Input Heae Figue 52.Contol Input Figue 53.Powe Inputs Figue 54.Silksceen Top Figue 55.Top Sie Figue 56.ottom Sie LIST OF TLES Table 1. System Connections... 5 Table 2. CD4385 Jumpe Settings... 6 DS671D4 3

4 CD4385 SYSTEM OVERVIEW CD4385 The CD4385 evaluation boa is an excellent means of quickly evaluating the CS4385. The CS8416 igital auio inteface eceive povies an easy inteface to igital auio signal souces incluing the majoity of igital auio test equipment. The evaluation boa also allows the use to supply extenal PCM o DSD clocks an ata though PC heaes fo system evelopment. The CD4385 schematic has been patitione into 10 schematics shown in Figues 44 though 53. Each patitione schematic is epesente in the system iagam shown in Figue 43. Notice that the system iagam also inclues the inteconnections between the patitione schematics. 1. CS4385 DIGITL-TO-NLOG CONVERTER esciption of the CS4385 is inclue in the CS4385 atasheet. 2. CS8416 DIGITL UDIO RECEIVER The system eceives an ecoes the stana S/PDIF ata fomat using a CS8416 igital auio eceive (Figue 49). The outputs of the CS8416 inclue a seial bit clock, seial ata, left-ight clock, an a 128/256 Fs maste clock. The CS8416 ata fomat is fixe to I 2 S. The opeation of the CS8416 an a iscussion of the igital auio inteface ae inclue in the CS8416 atasheet. The evaluation boa has been esigne such that the input can be eithe optical o coaxial, see Figue 49. Howeve, both inputs cannot be iven simultaneously. Switch position 7 of S1 sets the output MCLK-to-LRCK atio of the CS8416. This switch shoul be set to 256 (close) fo inputs Fs 96 k an 128 (open) fo Fs 64 k. The 8416 must be manually eset using HW RST (S2) o though the softwae when this switch is change. 3. INPUT FOR CLOCKS ND DT The evaluation boa has been esigne to allow intefacing to extenal systems via heaes J11 an J7. Heae J11 allows the evaluation boa to accept extenally geneate PCM clocks an ata. The schematic fo the clock/ata input is shown in Figue 50. Switch position 6 of S1 selects the souce as eithe CS8416 (open) o heae J11 (close). Heae J7 allows the evaluation boa to accept extenally geneate DSD ata an clocks. The schematic fo the clock/ata input is shown in Figue 50. synchonous MCLK must still be povie via Heae J11. Switch position 8 of S1 selects eithe PCM (open) o DSD (close). Please see the CS4385 atasheet fo moe infomation. 4. INPUT FOR CONTROL DT The evaluation boa can be un in eithe a stan-alone moe o with a PC. Stan-alone moe uses the CS4385 in hawae moe an the moe pins ae configue using switch positions 1 though 5 of S1. PC moe uses softwae to setup the CS4385 though I²C using the PC s seial o US pots. PC moe is automatically selecte when the seial o US pot is attache an the CD4385 softwae is unning. Heae J15 offes the option fo extenal input of RST an SPI /I²C clocks an ata. The boa is setup fom the factoy to use the on-boa micocontolle in conjunction with the supplie softwae. To use an extenal contol souce, emove the shunts on J15 an place a ibbon cable so the signal lines ae on the cente ow an the gouns ae on the ight sie. R116 an R119 shoul be populate with 2-kΩ esistos when using an extenal I 2 C souce which oes not aleay povie pull-ups. 4 DS671D4

5 CD POWER SUPPLY CIRCUITRY Powe is supplie to the evaluation boa by fou bining posts (GND, +5V, +12V, an -12V), see Figue 53. The +5V teminal supplies V an the est of the +5-V cicuity on the boa. The +3.3-V cicuity is powee fom a egulato. The +2.5 volts equie fo VD is also povie fom an on-boa egulato. The +5-V supply shoul be set within the ecommene values fo V state in the CS4385 atasheet. WRNING: Refe to the CS4385 atasheet fo maximum allowable voltage levels. Opeation outsie of this ange can cause pemanent amage to the evice. 6. GROUNDING ND POWER SUPPLY DECOUPLING s with any high-pefomance convete, the CS4385 equies caeful attention to powe supply an gouning aangements to optimize pefomance. Figue 44 etails the connections to the CS4385 an Figues 54, 55, an 56 show the component placement an top an bottom layout. The ecoupling capacitos ae locate as close to the CS4385 as possible. Extensive use of goun plane fill in the evaluation boa yiels lage euctions in aiate noise. 7. NLOG OUTPUT FILTERING The analog output on the CD4385 has been esigne accoing to the CS4385 atasheet. This output cicuit inclues an active 2-pole, 50-k filte which utilizes the multiple-feeback topology. CONNECTOR INPUT/OUTPUT SIGNL PRESENT +5V Input + 5 V powe GND Input Goun connection fom powe supply +12V Input +12 V positive supply fo the on-boa filteing -12V Input -12 V negative supply fo the on-boa filteing S/PDIF IN - J9 Input Digital auio inteface input via coax S/PDIF IN - OPT1 Input Digital auio inteface input via optical PCM INPUT - J11 Input Input fo maste, seial, left/ight clocks an seial ata DSD INPUT - J7 Input Input fo DSD seial clock an DSD ata OUT1-4 Output RC line level analog outputs Table 1. System Connections DS671D4 5

6 CD4385 JUMPER / SWITCH PURPOSE POSITION FUNCTION SELECTED J15 Selects souce of contol ata *shunts on Left shunts emove Table 2. CD4385 Jumpe Settings *Contol fom PC an on-boa micocontolle Extenal contol input using cente an ight columns J16 JTG mico pogamming - Reseve fo factoy use only S2 Resets CS8416 an CS4385 The CS8416 must be eset if switch S1 is change S1 CS4385 moe settings M0-M4 1-5 Sets clock souce 6 Default: M0, M4 open (HI) M1, M2, M3 close (LO) Sets clock souce fo CS4385 *open = RX(CS8416), close = EXT(J11) Sets MCLK atio of CS Selects 128x (open) o 256x (*close) MCLK/LRCK atio output fo CS8416 Selects PCM o DSD moe 8 Fo PCM input set to *Open, fo DSD set to Close *Default Factoy Settings 6 DS671D4

7 8. PERFORMNCE PLOTS CD4385 The plots in the following section wee acheive using an uio Pecision System 2700 an a anomly chosen pouction CD4385. In some cases the pefomance may be limite by the CD4385. ll measuements wee taken at oom temp using the stana P filte options (20 to 22 k) with efault boa settings an nominal atasheet voltages applie unless othewise note. The impulse esponse plots wee taken both pe-an post filteing as the off-chip filte was egaing the pefomance at highe sample ates. The pe-filte impulse esponse plots wee taken iectly at the output pins of the DC (with the analog filte still connecte) to show the effect of the CD s analog filteing on the impulse esponse (as the analog filteing as its own signatue to the impulse esponse of the DC, an in the case of the highe sampling ates it was ban-limiting it). 0 0 Figue 1. FFT (48 k, 0 ) Figue 2. FFT (48 k, ) 0 0 Figue 3. FFT (48 k, No Input) 20k 40k 60k 80k 100k 120k Figue 4. FFT (48 k Out-of-an, No Input) DS671D4 7

8 CD Figue 5. FFT (48 k, Wieban) 2k 4k 6k 8k 10k 12k 14k 16k 18k Figue 6. FFT (IMD 48 k) 20k 0 0 Figue k, THD+N vs. Input Feq 0 FS Figue k, THD+N vs. Level FS Figue k, Fae-to-Noise Lineaity -5 Figue k, Fequency Response 8 DS671D4

9 CD V 500m 0 0m Figue k, Cosstalk u 1m 1.5m 2m 2.5m 3m sec Figue k, Impulse Response m V 0 0m u 1m 1.5m 2m 2.5m 3m sec Figue k, Impulse Pefilte DS671D4 9

10 CD4385 Figue 14. Dynamic Range 48 k 0 0 Figue 15. FFT (96 k, 0 ) Figue 16. FFT (96 k, ) 10 DS671D4

11 CD Figue 17. FFT (96 k, No Input) 20k 40k 60k 80k 100k 120k Figue 18. FFT (96 k Out-of-an, No Input) k 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k Figue 19. FFT (96 k, Wieban) Figue 20. FFT (IMD 96 k) 0 0 Figue k, THD+N vs. Input Feq 0 FS Figue k, THD+N vs. Level DS671D4 11

12 CD FS Figue k, Fae-to-Noise Lineaity -5 Figue k, Fequency Response m V 0 0m Figue k, Cosstalk u 500u 750u 1m 1.25m 1.5m sec Figue k, Impulse Response m V 0 0m u 500u 750u 1m 1.25m 1.5m sec Figue k, Impulse Pefilte 12 DS671D4

13 CD4385 Figue 28. Dynamic Range 96 k 0 0 Figue 29. FFT (192 k, 0 ) Figue 30. FFT (192 k, ) DS671D4 13

14 CD Figue 31. FFT (192 k, No Input) 20k 40k 60k 80k 100k 120k Figue 32. FFT (192 k Out-of-an, No Input) k 90k 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k Figue 33. FFT (192 k, Wieban) Figue 34. FFT (IMD 192 k) 0 0 Figue k, THD+N vs. Input Feq 0 FS Figue k, THD+N vs. Level 14 DS671D4

15 CD FS Figue k, Fae-to-Noise Lineaity -5 Figue k, Fequency Response m V 0 0m Figue k, Cosstalk u 400u 600u sec Figue k, Impulse Response m V 0 0m u 400u 600u sec Figue k, Impulse Pefilte DS671D4 15

16 CD4385 Figue 42. Dynamic Range 192 k 16 DS671D4

17 DS671D SCHEMTICS PCM HEDER CS8416 S/PDIF Input PCM Clocks/Data PCM Clocks/Data CS8416 clock setting PCM mux PCM souce select M0 - M4 switches (fo stan-alone moe) Hawae Contol Switches PCM Clocks/Data DSD input enable Seial Contol Pot I 2 C/SPI Heae CS4385 DSD clk_enable DSD Clocks/ Data DSD HEDER Figue 43. System lock Diagam an Signal Flow Powe Diffeential to Single-Ene nalog Outputs 1, 1 2, 2 3, 3 4, 4 CD4385

18 CD4385 Figue 44. CS DS671D4

19 CD4385 Figue 45. nalog Outputs 1-1 DS671D4 19

20 20 DS671D4 Figue 46. nalog Outputs 2-2 CD4385

21 DS671D4 21 Figue 47. nalog Outputs 3-3 CD4385

22 22 DS671D4 Figue 48. nalog Outputs 4-4 CD4385

23 CD4385 Figue 49. CS8416 S/PDIF Input DS671D4 23

24 24 DS671D4 Figue 50. PCM Input Heae an Muxing CD4385

25 CD4385 Figue 51. DSD Input Heae DS671D4 25

26 CD4385 Figue 52. Contol Input 26 DS671D4

27 CD4385 Figue 53. Powe Inputs DS671D4 27

28 CD4385 Figue 54. Silksceen Top 28 DS671D4

29 CD4385 Figue 55. Top Sie DS671D4 29

30 CD4385 Figue 56. ottom Sie 30 DS671D4

31 10.ERRT CD4385 Fo the CD4385 evision, the silksceen fo S1 enotes efault switch settings. This efes only to M0 - M4. See Table 2 on page 6 fo efault settings fo the othe switch positions. DS671D4 31

32 11.REVISION HISTORY Release Changes D1 Initial Release D2 Upate fo evision C of CD D3 e Pefomance Plots D4 e US suppot to Section 4. Input fo Contol Data CD4385 Contacting Cius Logic Suppot Fo all pouct questions an inquiies, contact a Cius Logic Sales Repesentative. To fin the one neaest to you, go to IMPORTNT NOTICE Cius Logic, Inc. an its subsiiaies ("Cius") believe that the infomation containe in this ocument is accuate an eliable. Howeve, the infomation is subject to change without notice an is povie "S IS" without waanty of any kin (expess o implie). Customes ae avise to obtain the latest vesion of elevant infomation to veify, befoe placing oes, that infomation being elie on is cuent an complete. ll poucts ae sol subject to the tems an conitions of sale supplie at the time of oe acknowlegment, incluing those petaining to waanty, inemnification, an limitation of liability. No esponsibility is assume by Cius fo the use of this infomation, incluing use of this infomation as the basis fo manufactue o sale of any items, o fo infingement of patents o othe ights of thi paties. This ocument is the popety of Cius an by funishing this infomation, Cius gants no license, expess o implie une any patents, mask wok ights, copyights, taemaks, tae secets o othe intellectual popety ights. Cius owns the copyights associate with the infomation containe heein an gives consent fo copies to be mae of the infomation only fo use within you oganization with espect to Cius integate cicuits o othe poucts of Cius. This consent oes not exten to othe copying such as copying fo geneal istibution, avetising o pomotional puposes, o fo ceating any wok fo esale. CERTIN PPLICTIONS USING SEMICONDUCTOR PRODUCTS MY INVOLVE POTENTIL RISKS OF DETH, PERSONL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTL DMGE ( CRITICL PPLICTIONS ). CIRRUS PRODUCTS RE NOT DESIGNED, UTHORIZED OR WRRNTED FOR USE IN PRODUCTS SURGICLLY IMPLNTED INTO THE ODY, UTOMOTIVE SFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT- ICL PPLICTIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH PPLICTIONS IS UNDERSTOOD TO E FULLY T THE CUSTOMER S RISK ND CIRRUS DISCLIMS ND MKES NO WRRNTY, EXPRESS, STTUTORY OR IMPLIED, INCLUDING THE IMPLIED WRRNTIES OF MERCHNTILITY ND FITNESS FOR PRTICULR PURPOSE, WITH REGRD TO NY CIRRUS PRODUCT THT IS USED IN SUCH MNNER. IF THE CUSTOMER OR CUSTOMER S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICL PPLICTIONS, CUSTOMER GREES, Y SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIUTORS ND OTHER GENTS FROM NY ND LL LIILITY, INCLUD- ING TTORNEYS FEES ND COSTS, THT MY RESULT FROM OR RISE IN CONNECTION WITH THESE USES. Cius Logic, Cius, an the Cius Logic logo esigns ae taemaks of Cius Logic, Inc. ll othe ban an pouct names in this ocument may be taemaks o sevice maks of thei espective ownes. DSD is a egistee taemak of Sony Kabushiki Kaisha T Sony Company. I²C is a egistee taemak of Philips Semiconucto. SPI is a taemak of Motoola, Inc. 32 DS671D4