Evaluation Board for CS4270. Description. Serial/USB Control Port. I 2 C/SPI Header CS4270. S/PDIF Output. HW Setup Switches

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1 CD4270 Evaluation oa fo CS4270 Featues Desciption Single-Ene nalog uio Inputs an Outputs CS8416 S/PDIF Digital uio Receive Heae fo Extenal Configuation of CS4270 Heae fo Extenal DSP Seial uio I/O 3.3V Logic Intefaces Pe-Define Softwae Scipts Demonstates Recommene Layout Winows -Compatible GUI Inteface fo oa Configuation an Contol Using the CD4270 is an excellent way to evaluate the CS4270 CODEC. Othe equipment equie inclues analog/igital auio souces/analyze, a 5V powe supply an a Winows-compatible PC fo the GUI. System timing fo the I²S, Left-Justifie o Right-Justifie auio ata fomats can be povie by the CS4270, by the CS8416, o by a evice connecte to the onboa DSP I/O heae. The evaluation boa may also be configue to accept extenal timing an ata signals fo opeation in a use application uing system evelopment. RC jacks ae povie fo the analog auio inputs an outputs. Digital S/PDIF tansmit o eceive ata I/O is available via eithe RC jacks o optical connectos. The Winows GUI softwae povie allows fo easy configuation of the CD4270. The GUI softwae communicates with the boa via US o seial pot connections to configue the CS4270 egistes. ORDERING INFORMTION CD4270 Evaluation oa Hawae Setup Seial/US Contol Pot CS8406 S/PDIF Output I 2 C/SPI Heae NLOG INPUT Clocks/Data Single-Ene Input MCLK US CS4270 CS8416 S/PDIF Input Hawae Setup Clocks /Data FPG DC/DC Clocks/ Data Hawae Setup NLOG OUTPUT Single-Ene Output HW Setup Switches Osc. DC/DC Clocks & Data DSP HEDER Copyight Cius Logic, Inc (ll Rights Reseve) SEPTEMER '06 DS686D3

2 TLE OF CONTENTS CD SYSTEM OVERVIEW Powe Gouning an Powe Supply Decoupling FPG CS4270 uio CODEC CS8406 Digital uio Tansmitte CS8416 Digital uio Receive Canne Oscillato Extenal Contol Heaes nalog Input nalog Outputs Contol Pot Hawae Moe Switches FPG OVERVIEW FPG chitectue Intenal Sub-Clock Routing Intenal Data Routing Intenal Dives Extenal MCLK Contol SOFTWRE MODE CD4270 Contol Scipts S/PDIF In, nalog Out nalog In, S/PDIF Out nalog In, nalog Out (Digital Loop-ack) DSP In, nalog Out CD4270 GUI Registe Maps Contol Tabs HRDWRE MODE FPG GUI REGISTER DESCRIPTION FPG REGISTER QUICK REFERENCE Revision Numbe its (its 7:0) SDOUT Routing to Heae (its 7:6) MCLK Souce (it 4) SDOUT Routing to DUT (its 3:2) Subclock Routing (its 1:0) CS8406 OMCLK Divie Contol (its 7:6) CS8406 Maste/Slave Select (it 4) CS8406 SDIN Fomat Select (it 3) CS8406 SDIN Souce (its 1:0) CS8416 RMCLK Divie Contol (it 6) CS8416 Maste/Slave Select (it 4) CS8416 SDOUT Fomat Select (it 3) CD4270 HRDWRE MODE SETTINGS CD CONNECTORS, SWITCHES, INDICTORS ND JUMPERS DC PERFORMNCE PLOTS DC PERFORMNCE PLOTS CD LOCK DIGRM CD SCHEMTICS CD LYOUT CHNGES MDE TO REV. ORD Moifications (Done by Cius Logic) REVISION HISTORY DS686D3

3 LIST OF FIGURES CD4270 Figue 1.DC THD+N... 7 Figue 2.DC Dynamic Range... 7 Figue 3.Intenal Sub-Clock Routing... 9 Figue 4.Intenal Data Routing Figue 5.Intenal Dives Figue 6.Extenal MCLK Contol Figue 7.CD4270 Contols Tab Figue 8.Registe Maps Tab - CS Figue 9.Registe Maps Tab - oa Configuation Figue 10.Registe Maps Tab - GPIO Figue 11.FFT (-1 48 k) Figue 12.FFT (, 48 k) Figue 13.FFT (48 k, No Input) Figue k, THD+N vs. Input Feq Figue k, THD+N vs. Level Figue k, Fae-to-Noise Lineaity Figue k, Fequency Response Figue k, Cosstalk Figue 19.FFT (-1 96 k) Figue 20.FFT (, 96 k) Figue 21.FFT (96 k, No Input) Figue k, THD+N vs. Input Feq Figue k, THD+N vs. Level Figue k, Fae-to-Noise Lineaity Figue k, Fequency Response Figue k, Cosstalk Figue 27.FFT ( k) Figue 28.FFT (192 k, ) Figue 29.FFT (192 k, No Input) Figue k, THD+N vs. Input Feq Figue k, THD+N vs. Level Figue k, Fae-to-Noise Lineaity Figue k, Fequency Response Figue k, Cosstalk Figue 35.FFT (48 k, 0 ) Figue 36.FFT (48 k, ) Figue 37.FFT (48 k, No Input) Figue 38.FFT (48 k Out-of-an, No Input) Figue k, THD+N vs. Input Feq Figue k, THD+N vs. Level Figue k, Fae-to-Noise Lineaity Figue k, Fequency Response Figue k, Cosstalk Figue k, Impulse Response Figue 45.FFT (96 k, 0 ) Figue 46.FFT (96 k, ) Figue 47.FFT (96 k, No Input) Figue 48.FFT (96 k Out-of-an, No Input) Figue k, THD+N vs. Input Feq Figue k, THD+N vs. Level Figue k, Fae-to-Noise Lineaity Figue k, Fequency Response DS686D3 3

4 CD4270 Figue k, Cosstalk Figue k, Impulse Response Figue 55.FFT (192 k, 0 ) Figue 56.FFT (192 k, ) Figue 57.FFT (192 k, No Input) Figue 58.FFT (192 k Out-of-an, No Input) Figue k, THD+N vs. Input Feq Figue k, THD+N vs. Level Figue k, Fae-to-Noise Lineaity Figue k, Fequency Response Figue k, Cosstalk Figue k, Impulse Response Figue 65.lock Diagam Figue 66.CS Figue 67.nalog Input Figue 68.nalog Output Figue 69.CS8406 S/PDIF Tansmitte Figue 70.CS8416 S/PDIF Receive Figue 71.uffes - Clock/Data Routing Figue 72.FPG Figue 73.US/RS232 Micopocesso Figue 74.Powe Figue 75.Silk Sceen Figue 76.Top-Sie Laye Figue 77.ottom-Sie Laye LIST OF TLES Table 1. Revision Numbe Table 2. SDOUT Routing to Heae Table 3. MCLK Souce Table 4. SDOUT Routing to DUT Table 5. Sub-Clock Routing Table 6. CS8406 OMCLK Fequency Table 7. CS8406 Maste/Slave Table 8. CS8406 SDIN Fomat Table 9. CS8406 SDIN Souce Table 10. CS8416 RMCLK Fequency Table 11. CS8416 Maste/Slave Table 12. CS8416 SDOUT Fomat Table 13. CD4270 Hawae Moe - Functional Desciption Table 14. Connectos an Switches Table 15. Jumpes an Inicatos DS686D3

5 1. SYSTEM OVERVIEW CD4270 The CD4270 evaluation boa is an excellent tool fo evaluating the CS4270 CODEC. The boa featues both analog an igital auio intefaces along with an FPG fo ata/clk outing an an on-boa micopocesso fo configuation contol. The boa is easily configue in Softwae Moe using the supplie PC-to-DUT US cable along with the Winows-base GUI configuation softwae o in Hawae Moe using the on-boa ip switches. The CD4270 schematic set has been patitione into nine pages an is shown in Figues 66 though Powe Powe must be supplie to the evaluation boa though the +5.0 V bining posts. The +5 V inputs must be efeence to the single black bining post goun connecto (Figue 74 on page 45). WRNING: Please efe to the CS4270 ata sheet fo allowable voltage levels. 1.2 Gouning an Powe Supply Decoupling To optimize pefomance, PC boa esigns fo the CS4270 equie caeful attention to powe supply, gouning an signal outing aangements. Figue 65 on page 36 shows the basic component/signal inteconnect fo the CD4270. Figue 75 on page 46 shows the component placement. Figue 76 on page 47 shows the top layout. Figue 77 on page 48 shows the bottom layout. The ecoupling capacitos ae locate as close to the CS4270 as possible. Extensive use of goun plane fill in the evaluation boa yiels lage euctions in aiate noise. 1.3 FPG See FPG Oveview on page 9 fo a complete esciption of the FPG (Figue 72 on page 43) that is use on the CD CS4270 uio CODEC complete esciption of the CS4270 (Figue 66 on page 37) is inclue in the CS4270 pouct ata sheet. The CS4270 coec pefoms steeo 24-bit /D an D/ convesion at sample ates of up to 216 K. The pat accommoates I²S, Left-Justifie an Right-Justifie seial auio fomats. 1.5 CS8406 Digital uio Tansmitte complete esciption of the CS8406 tansmitte (Figue 69 on page 40) an a iscussion of the igital auio inteface ae inclue in the CS8406 ata sheet. The CS8406 convets the PCM ata fom eithe the CS4270, the DSP Heae, o the CS8416 to a stana S/PDIF ata steam. The CS8406 opeates in eithe maste o slave sub-clock moe an will accept eithe a 128 Fs, 256 Fs, o 512 Fs maste clock on the OMCK input pin. The evice will opeate in eithe the Left- Justifie o I²S inteface ata moes. 1.6 CS8416 Digital uio Receive complete esciption of the CS8416 eceive (Figue 70 on page 41) an a iscussion of the igital auio inteface ae inclue in the CS8416 ata sheet. The CS8416 convets the input S/PDIF ata steam into PCM ata that can be use by the CS4270 an CS8406. The evice opeates in eithe Maste o Slave sub-clock moes an geneates eithe a 128 Fs o 256 Fs maste clock fo output on the RMCK pin. Eithe Left-Justifie o I²S inteface output ata fomats can be selecte DS686D3 5

6 CD Canne Oscillato Oscillato Y1 povies a system maste clock. This clock is oute though the CS8416 an out of the RMCK pin when the S/PDIF input is isconnecte (efe to the CS8416 ata sheet fo etails on OMCK opeation). To use the canne oscillato as the souce of the MCLK signal, emove the S/PDIF input to the CS8416 an configue the CS8416 appopiately. The oscillato is mounte in pin sockets, allowing easy emoval o eplacement. The boa is shippe with a M cystal oscillato populate at Y Extenal Contol Heaes The evaluation boa has been esigne to allow intefacing with extenal systems via the J10 an J9 heaes. The 10-pin, 2-ow heae, J9, allows access to the seial auio signals equie to inteface with a DSP (see Figue 71 on page 42). The 18-pin, 3-ow heae, J10, allows the use biiectional access to the SPI TM /I²C contol signals by simply emoving all of the shunt jumpes fom the NORML position. The use may then choose to connect a ibbon cable to the EXTERNL position. single GND ow fo the ibbon cable s goun connection is povie to maintain signal integity. Two unpopulate pull-up esistos ae also available shoul the use choose to use the CD fo the I²C powe ail. 1.9 nalog Input RC connectos supply the CS4270 analog inputs though passive, C-couple, single-ene cicuits. 2 Vms single-ene signal into the RC connectos will ive the CS4270 inputs to full scale (1 Vms). The input netwok on the CD4270 was esigne to emonstate that the CS4270 will povie supeio pefomance with up to 2.5 kω iving impeances (looking back fom the CS4270 inputs) while allowing fo 2 Vms inputs. DC pefomance vaies epening upon the input impeance of the input netwok. Figues 1 an 2 show typical THD+N an Dynamic Range pefomance fo the DC as a function of input impeance. 6 DS686D3

7 CD4270 Figue 1. DC THD+N Figue 2. DC Dynamic Range DS686D3 7

8 CD nalog Outputs The CS4270 analog outputs ae C-couple an oute though a single-pole RC Low-Pass filte Contol Pot gaphical use inteface is inclue with the CD4270 to allow easy manipulation of the egistes in the CS4270 (see the CS4270 ata sheet fo egiste esciptions an the FPG GUI Registe Desciption on page 18). The GUI will un on a stana Winows-base PC. Connecting a US cable fom a PC to J15 o an RS-232 cable to J16 an launching the Cius Logic FlexGUI softwae enables contol an configuation of the boa. Refe to Softwae Moe on page 13 fo a esciption of the Gaphical Use Inteface (GUI) Hawae Moe Switches The HW Moe Config an Clk/Data Config switches contol all Hawae Moe options. Hawae Moe on page 18 povies a esciption of each topology. 8 DS686D3

9 CD FPG OVERVIEW The FPG (U11) contols all igital signal outing between the CS4270, CS8406, CS8416 an the DSP I/O Heae. The evice also geneates all of the clock/ata ive output enables an S/PDIF evice moe contols. The FPG intenal egistes can be configue eithe via the I²C (Softwae Moe) o via extenal ip switches (Hawae Moe). When using the CS4270 in Hawae Moe, the FPG ecoes some of these ip-switch settings an geneates the CS4270 contol signals. In aition, the FPG istibutes esets fom the mico fo all of the evices on the boa. 2.1 FPG chitectue Figues 3 though 5 show the intenal achitectue of the FPG. Figue 6 shows the MCLK outing to/fom the FPG an the othe evices on the boa. The FPG has an I²C inteface an intenal egistes fo softwae contol an can also ea extenal ip-switch settings fo hawae contol. Refe to the FPG GUI Registe Desciption section of this ocument fo a esciption of the FPG egistes. 2.2 Intenal Sub-Clock Routing. Figue 3 shows the intenal sub-clock (SCLK, LRCK) outing topology between the CS4270, CS8416, CS8406 an DSP Heae. Refe to the FPG GUI Registe Desciption section of this ocument fo a esciption of the sub-clock outing egiste settings. FPG SU_CK[1:0] SU_CK[1:0] CS4270 CS8416-FPG-LRCK HDR-LRCK FPG-CS8406-LRCK CS8416-FPG-SCLK HDR-SCLK FPG-CS8406-SCLK LRCK SCLK FPG- DUT-LRCK FPG-DUT-SCLK SU_CK[1:0] CS8416-FPG-LRCK HDR-LRCK FPG-DUT-LRCK SU_CK[1:0] CS8416-FPG-SCLK HDR-SCLK FPG-DUT-SCLK LRCK SCLK CS8406 FPG-CS8406- LRCK FPG-CS8406-SCLK CS8416 SU_CK[1:0] SU_CK[1:0] LRCK FPG-DUT-SCLK FPG-DUT-LRCK SCLK HDR-SCLK HDR-LRCK FPG-CS8406-SCLK FPG-CS8406-LRCK CS8416-FPG- LRCK CS8416-FPG-SCLK DSP Heae SUCLK.FROM.HDR SUCLK.TO.HDR SU_CK[1:0] SU_CK[1:0] LRCK CS8416-FPG-SCLK CS8416-FPG-LRCK SCLK FPG-DUT-SCLK FPG-DUT-LRCK SUCLK.TO.HDR FPG-CS8406-SCLK FPG-CS8406-LRCK SUCLK.FROM.HDR HDR-LRCK HDR-SCLK Figue 3. Intenal Sub-Clock Routing DS686D3 9

10 CD Intenal Data Routing. Figue 4 shows the intenal ata outing topology between the CS4270, CS8416, CS8406 an the DSP Heae. Refe to the FPG GUI Registe Desciption section of this ocument fo a esciption of the auio ata outing egiste settings. CS8416 FPG TXSDIO[1:0] CS8406 SDOUT CS8416-FPG-SDOUT CS8406-SDIN SDIN DSP Heae SDIO[1:0] SDIN SDOUT FPG-SDIN FPG-HDR-SDOUT CS4270 DUT_SDIO[1:0] SDOUT SDIN CS4270-FPG-SDOUT CS4270-SDIN Figue 4. Intenal Data Routing 10 DS686D3

11 2.4 Intenal Dives CD4270 Figue 5 shows the intenal ives an logic fo boa level selects/enables an so foth. Refe to the FPG GUI Registe Desciption section of this ocument fo a esciption of the boa level contol egiste settings.. FPG MICRO-SD/CCLK FPG-SPI M1 HDR-SD/CDOUT MICRO-SCL/MISO FPG-SPI M0 HDR-SCL/CCLK FPG-CS FPG-SPI MDIV1 HDR-D1/CDIN FPG-D0 FPG-I2C MDIV2 HDR-D2 FPG-MOSI FPG-SPI DIF HDR-D0/CS FPG-D1 FPG-I2C FPG-SW/HW FPG-D2 FPG-I2C FPG-I2C I2C Figue 5. Intenal Dives DS686D3 11

12 CD Extenal MCLK Contol Seveal souces fo MCLK exist on the CD4270. The cystal oscillato, Y1, will maste the MCLK bus when no S/PDIF signal is input to the CS8416 (efe to the CS8416 ata sheet fo etails on OMCK opeation). When S/PDIF ata is pesent at the CS8416 input, the CS8416 geneates a maste clock wheneve its intenal PLL is locke to the incoming S/PDIF steam. The DSP Heae can maste the MCLK bus o be an obsevation point fo MCLK epening upon the state of the ive contol signals fom the FPG.. Refe to the Registe Desciption section of this ocument fo a esciption of the MCLK outing contol egistes. CS8416 RMCK MCLK CS4270 OSC OMCK FPG MCLK.FROM.8416 CS8406 OMCK MCLK MCLK.FROM.HDR DSP Heae MCLK.TO.HDR MCLK Figue 6. Extenal MCLK Contol 12 DS686D3

13 3. SOFTWRE MODE CD4270 The CD4270 uses a Micosoft Winows-base GUI (ownloa fom Cius web site), which allows contol of the CS4270 an FPG egistes. Inteface to the GUI is povie via US o RS-232 seial connection. Once the appopiate cable is connecte between the CD4270 an the host PC, un FlexLoae.exe. The softwae shoul automatically etect the boa. If a boa selection ialog is isplaye, select CD4270 fom the list. Once loae, all egistes ae set to thei efault state. Note: The boa is automatically set to Softwae Contol Moe once the seial o US cable is installe an the GUI is up an unning. The GUI s File menu povies the ability to save an loa scipt files containing all of the egiste settings. Sample scipt files fo basic moe opeation can be ownloae fom the achive at CD4270 Contol Scipts ief esciptions of the supplie scipts ae given below S/PDIF In, nalog Out When the SPDIF_IN_OUT.FGS scipt is un, the CS8416 is the sub-clock (SCLK an LRCK) maste an all othe evices incluing the DSP Heae ae slaves. The CS8416 povies MCLK ecovee fom the S/PDIF ata an SDOUT to the CS4270 DC, DSP Heae an CS nalog In, S/PDIF Out When the IN_SPDIF_OUT.FGS scipt is un, the cystal oscillato is the MCLK maste. The CS8416 passes the clock fom the cystal oscillato, Y1, though to the RMCK output (Note: the S/PDIF input must be isconnecte) to the CS4270, the CS8406 an the DSP Heae. The CS4270 povies SDOUT to the CS8406 an the DSP Heae. The CS8406 geneates sub-clocks eive fom the CS4270 ata an is the sub-clock maste. ll othe evices incluing the DSP Heae ae sub-clock slave evices nalog In, nalog Out (Digital Loop-ack) When the IN_OUT.FGS scipt is un, the cystal oscillato is the MCLK maste. The CS8416 passes the clock fom the cystal oscillato, Y1, though to the RMCK output (Note: the S/PDIF input must be isconnecte) to the CS4270, the CS8406 an the DSP Heae. The CS8416 geneates sub-clocks eive fom the cystal oscillato an is the sub-clock maste. ll othe evices an the DSP Heae ae subclock slave evices. SDOUT fom the CS4270 DC is oute though the FPG to the CS4270 DC, to the DSP Heae an to the CS DSP In, nalog Out When the DSP_IN_OUT.FGS scipt is un, the DSP Heae is the MCLK, sub-clock an ata maste an all othe evices ae slaves. SDOUT at the heae is the CS4270 SDOUT. DS686D3 13

14 CD CD4270 GUI ief esciptions of the GUI tab views ae povie below. The CD4270 Contols tab povies high-level contol of the CS4270, FPG (oa Contols) an S/PDIF Tx an Rx evices. The CS4270 Contols goup affects that evice s egiste settings. The oa Contols goup allows the use to select MCLK an sub-clock souce/outing as well as CS4270 an CS8406 SDIN souces. The S/PDIF Receive an S/PDIF Tansmitte contol goups allow the use to select ata fomats, MCLK fequency an maste o slave fo each evice. Reset push-buttons ae also available along with a Comm Moe select op box fo CS4270 communication moe fomat selection. Figue 7. CD4270 Contols Tab 14 DS686D3

15 3.3 Registe Maps Contol Tabs CD4270 Une this tab ae the CS4270, oa Configuation (FPG) an GPIO tabs. On each tab, egiste values can be moifie bit-wise o byte-wise. Fo bit-wise moification, click the appopiate push-button fo the esie bit. Fo byte-wise moification, the esie hex value can be type iectly into the egiste aess box in the egiste map. Refe to the CS4270 evice ata sheet egiste settings section an the FPG egiste infomation in this ocument fo egiste efinitions. Figue 8. Registe Maps Tab - CS4270 DS686D3 15

16 CD4270 Figue 9. Registe Maps Tab - oa Configuation 16 DS686D3

17 CD4270 Figue 10. Registe Maps Tab - GPIO DS686D3 17

18 CD HRDWRE MODE When the Flex GUI is not unning on a PC o when the US o seial pot cables ae not connecte to the CD4270 fom the PC, the boa is automatically in Hawae Contol Moe. When in this contol moe, ip switches S1 an S2 contol the boa s functionality. Note: Hawae Moe contols ae a subset of Softwae Moe contols, an some FPG o CS4270 egiste bits cannot be change in Hawae Moe. See CD4270 Hawae Moe Settings on page 24 of this ocument fo a complete esciption of the Hawae Moe settings. 5. FPG GUI REGISTER DESCRIPTION s mentione peviously, the CS4270 an FPG egistes ae iectly accessible in Softwae Moe within the Flex GUI. In Hawae Moe, the FPG egistes contol all boa functions. The FPG egiste esciptions fo both moes ae escibe below. Fo a esciption of the CS4270 egistes, see the CS4270 ata sheet. 5.1 FPG REGISTER QUICK REFERENCE The table below shows the egiste names an thei associate efault values. Function h Coe Rev. ID REV.7 REV.6 REV.5 REV.4 REV.3 REV.2 REV.1 REV.0 01h 02h SDIO/CLK/SW/HW Contol CS8406 Contol SDIO.1 SDIO.0 Reseve MCLK DUT_SDIO.1 DUT_SDIO.0 SU_CK.1 SU_CK TXCLK.1 TXCLK.0 Reseve TX_M/S TX_FMT Reseve TXSDIO.1 TXSDIO h CS8416 Contol Reseve RXCLK Reseve RX_M/S RX_FMT Reseve Reseve Reseve Note: Default powe on bit states ae shown. 18 DS686D3

19 5.2 FPG CODE REVISION ID - DDRESS 00H CD REV.7 REV.6 REV.5 REV.4 REV.3 REV.2 REV.1 REV Revision Numbe its (its 7:0) Function: Ientifies FPG coe evision numbe. REV.7 - REV.4 inicate evision whole numbe, an REV.3 - REV.0 inicate evision ecimal numbe. These egiste bits ae Rea-Only. See Table 1. REV.7 REV.6 REV.5 REV.4 REV.3 REV.2 REV.1 REV.0 Revision Numbe Not Use Revision Revision Revision Revision Revision Revision Revision Revision Revision Revision Revision Revision Revision Revision Revision Table 1. Revision Numbe DS686D3 19

20 CD CS4270 CONTROL - DDRESS 01H SDIO.1 SDIO.0 Reseve MCLK DUT_SDIO.1 DUT_SDIO.0 SU_CK.1 SU_CK SDOUT Routing to Heae (its 7:6) Default = 00 Function: These bits contol the outing of SDOUT fom the CS8416, CS4270 an the Heae SDIN to the Heae SDOUT. Table 2 shows the available settings. SDIO.1 SDIO.0 SDIN/SDOUT Routing MCLK Souce (it 4) Default = 1 Function: This bit selects the souce of the CS4270 MCLK signal. Table 3 shows the available settings. MCLK MCLK Souce 0 MCLK fom DSP Heae 1 MCLK fom Oscillato (though CS8416), MCLK to DSP Heae SDOUT Routing to DUT (its 3:2) Default = 00 Function: 0 0 CS4270 SDOUT souce to DSP Heae SDOUT 0 1 CS8416 SDOUT souce to DSP Heae SDOUT 1 0 SDIN fom DSP Heae to DSP Heae SDOUT 1 1 Connect GND to DSP Heae SDOUT Table 2. SDOUT Routing to Heae Table 3. MCLK Souce These bits contol the outing of SDOUT fom the CS8416, CS4270 an the Heae SDIN to the CS4270. Table 4 shows the available settings. DUT_SDIO.1 DUT_SDIO.0 SDIN/SDOUT Routing 0 0 CS4270 SDOUT souce to CS4270 SDIN 0 1 CS8416 SDOUT souce to CS4270 SDIN 1 0 SDIN fom DSP Heae to CS4270 SDIN 1 1 Connect GND to CS4270 SDIN Table 4. SDOUT Routing to DUT 20 DS686D3

21 CD Subclock Routing (its 1:0) Default = 00 Function: These bits select SCLK an LRCK outing to/fom the CS4270, CS8416, CS8406 an the Heae. Table 5 shows the available settings. SU_CK.1 SU_CK.0 Sub-Clock Routing CS4270 is Maste - CS8416 an CS8406 ae Slaves to CS DSP Heae Sub-clocks ae Outputs fom CS CS4270 an CS8406 ae Slaves to CS CS8416 is Maste - DSP Heae Sub-clocks ae Outputs fom CS CS4270 is Slave to DSP Heae - CS8416 an CS8406 ae Slaves to DSP Heae - DSP Heae sub clocks ae Inputs - CS4270 an CS8416 ae Slave to CS CS8406 is Maste - DSP Heae Sub-clocks ae Outputs fom CS8406 Table 5. Sub-Clock Routing 5.4 CS8406 TX CONTROL - DDRESS 02H TXCLK.1 TXCLK.0 Reseve TX_M/S TX_FMT Reseve TXSDIO.1 TXSDIO CS8406 OMCLK Divie Contol (its 7:6) Default = 00 Function: These bits select the CS8406 OMCLK ivie atio. Table 6 shows the available settings. TXCLK.1 TXCLK.0 CS8406 OMCLK Fequency x Fs x Fs x Fs x Fs Table 6. CS8406 OMCLK Fequency DS686D3 21

22 CD CS8406 Maste/Slave Select (it 4) Default = 0 Function: This bit selects CS8406 Maste Moe (SCLK, LRCK ae outputs) o Slave Moe (SCLK, LRCK ae inputs). See Table 7. TX_M/S CS8406 SDIN Fomat Select (it 3) Default = 0 Function: This bit selects the CS8406 SDIN fomat. See Table 8. TX_FMT CS8406 SDIN Fomat 0 24-bit Left-Justifie 1 24-bit I²S CS8406 SDIN Souce (its 1:0) Default = 01 Function: CS8406 Maste/Slave 0 CS8406 Slave Moe 1 CS8406 Maste Moe Table 7. CS8406 Maste/Slave Table 8. CS8406 SDIN Fomat These bits select the souce of the CS8406 SDIN Signal. Table 9 shows the available settings. TXSDIO.1 TXSDIO.0 CS8406 SDIN Souce 0 0 CS4270 SDOUT 0 1 CS8416 SDOUT 1 0 SDIN fom Heae 1 1 GND Table 9. CS8406 SDIN Souce 22 DS686D3

23 CD CS8416 RX CONTROL - DDRESS 03H Reseve RXCLK Reseve RX_M/S RX_FMT Reseve Reseve Reseve CS8416 RMCLK Divie Contol (it 6) Default = 0 Function: This bit selects the CS8416 RMCLK ivie atio. Table 10. RXCLK CS8416 RMCLK Fequency x Fs x Fs CS8416 Maste/Slave Select (it 4) Default = 0 Function: This bit selects CS8416 Maste Moe (SCLK, LRCK ae outputs) o Slave Moe (SCLK, LRCK ae inputs). See Table 11 RX_M/S CS8416 Maste/Slave 0 CS8416 Slave Moe 1 CS8416 Maste Moe CS8416 SDOUT Fomat Select (it 3) Default = 0 Function: Table 10. CS8416 RMCLK Fequency Table 11. CS8416 Maste/Slave This bit selects the CS8416 SDOUT fomat. See.Table 12 RX_FMT CS8416 SDOUT Fomat 0 24-bit Left-Justifie 1 24-bit I²S Table 12. CS8416 SDOUT Fomat DS686D3 23

24 CD CD4270 HRDWRE MODE SETTINGS Schematic-Level Functional Desciption: When the Flex GUI is not use an thee is no seial pot communication to the boa, all evices ae in HW Moe. FPG SW contol is isable in this conition, an DIP switches S1 an S2 on the CD4270 set the FPG Registes to contol boa functionality. Note that the CS8406 an CS8416 ae eset when SW/HW fom the micopocesso goes low (going fom SW to HW Moe). See the schematic fo switch name labels, an see Table 13. Dip Switch Logic State b1, b0 nets S1 0,0 S1 0,1 S1 1,0 S1 1,1 Dip Switch Logic State b3, b2 nets S1 0,0 S1 0,1 S1 1,0 S1 1,1 Dip Switch Logic State b4 nets S1 0 S1 1 Functional Desciption s pe Table 5. - CS4270 is Maste - CS8416 an CS8406 ae Slaves to CS DSP Heae Sub-clocks ae Outputs fom CS4270 s pe Table 5. - CS8416 is Maste - CS4270 an CS8406 ae Slaves to CS DSP Heae Sub-clocks ae Outputs fom CS8416 s pe Table 5. -DSP Heae is Maste - CS4270, CS8416 an CS8406 ae Slaves to DSP Heae - DSP Heae Sub-clocks ae Inputs s pe Table 5. - CS8406 is Maste - CS4270 an CS8416 ae Slave to CS DSP Heae Sub-clocks ae Outputs fom CS8406 Functional Desciption s pe Table 2, Table 4, Table 9. CS4270 SDOUT to DSP Heae SDOUT CS4270 SDOUT to CS4270 SDIN CS4270 SDOUT to CS8406 SDIN s pe Table 2, Table 4, Table 9. CS8416 SDOUT to DSP Heae SDOUT CS8416 SDOUT to CS4270 SDIN CS8416 SDOUT to CS8406 SDIN s pe Table 2, Table 4, Table 9. DSP Heae SDIN to DSP Heae SDOUT DSP Heae SDIN to CS4270 SDIN DSP Heae SDIN to CS8406 SDIN s pe Table 2, Table 4, Table 9. DSP Heae SDIN to DSP Heae SDOUT DSP Heae SDIN to CS4270 SDIN DSP Heae SDIN to CS8406 SDIN FPG Functional Desciption s pe Table 3. MCLK fom DSP Heae s pe Table 3. MCLK fom Oscillato (though CS8416), MCLK to DSP Heae Table 13. CD4270 Hawae Moe - Functional Desciption 24 DS686D3

25 Dip Switch (1) Logic State M1, M0, MDIV2, MDIV1 S2 0,0,0,0 S2 0,1,0,0 S2 1,0,0,0 S2 1,0,1,0 S2 1,1,10 S2 1,1,1,1 Dip Switch Logic State DIF net S2 0 S2 1 CS4270 Functional CD4270 Sets CS4270 Single Spee MCLK ivie by 1 Moe, no e-emphasis, CS8406 OMCLK=256xFs an CS8416 RMCLK=256xFs Sets CS4270 Single Spee MCLK ivie by 1 Moe, w/e-emphasis, CS8406 OMCLK=256xFs an CS8416 RMCLK=256xFs Sets CS4270 Double Spee MCLK ivie by 1 Moe, no e-emphasis, CS8406 OMCLK=128xFs an CS8416 RMCLK=128xFs Sets CS4270 Double Spee MCLK ivie by 2 Moe, no e-emphasis, CS8406 OMCLK=256xFs an CS8416 RMCLK=256xFs Sets CS4270 Qua Spee MCLK ivie by 2 Moe, no e-emphasis, CS8406 OMCLK=128xFs an CS8416 RMCLK=128xFs Sets CS4270 Qua Spee MCLK ivie by 4 Moe, no e-emphasis, CS8406 OMCLK=256xFs an CS8416 RMCLK=256xFs CS4270 Functional Desciption Sets CS bit LJ Moe fo SDIN an SDOUT. CS8406 set to LJ Moe fo SDIN an CS8416 set to LJ Moe fo seial ata Sets CS bit I²S Moe fo SDIN an SDOUT. CS8406 set to I²S Moe fo SDIN an CS8416 set to I²S Moe fo seial ata Table 13. CD4270 Hawae Moe - Functional Desciption 1. Fo othe M1, M0, MDIV2, MDIV1 states, CS8406 OMCLK=256xFs an CS8416 RMCLK=256xFs. Note: Wheneve changes ae mae to the S/PDIF Receive (CS8416), the FPG (fo CS4270 HW o SW Moes) geneates a CS8416.RESET (CS8416 RESET) afte the paamete is change. Reg 03h (FPG) shows the paametes that apply. lso, wheneve CS4270-M/S (CS4270 maste/slave) changes state, the FPG geneates a HDR-RESET (CS4270 RESET). DS686D3 25

26 CD CD CONNECTORS, SWITCHES, INDICTORS ND JUMPERS CONNECTOR, SWITCH Refeence Designato INPUT/OUTPUT SIGNL PRESENT +5V J1 Input +5.0 V Powe Supply CLK/DT CON- TROL S1 Input HW Moe Clock/Data Routing Contol Dip Switch HW MODE CONFIG S2 Input HW Moe CS4270 Moe Contol Switch GND J2 Input Goun Refeence SPDIF OPTICL OUT OPT2 Output CS8406 igital auio output via optical cable SPDIF COX OUT J7 Output CS8406 igital auio output via coaxial cable SPDIF OPTICL IN OPT1 Input CS8416 igital auio input via optical cable SPDIF COX IN J5 Input CS8416 igital auio input via coaxial cable RS232 J16 Input/Output Seial connection to PC fo SPI / I²C Contol Pot signals US J15 Input/Output US connection to PC fo SPI / I²C Contol Pot signals DSP HEDER J9 Input/Output I/O fo Clocks & Data SERIL CONTROL J10 Input/Output I/O fo extenal SPI / I²C Contol Pot signals MICRO C2 HEDER J14 Input/Output I/O fo pogamming the mico contolle (U21) FPG JTG J12 Input/Output I/O fo pogamming the FPG (U11) MICRO RESET S4 Input Reset fo the mico contolle (U21) IN IN OUT OUT J13 J11 J6 J4 Input Output RC phono jacks fo analog inputs RC phono jacks fo analog outputs Table 14. Connectos an Switches JUMPER/ INDICTOR CONTROL JUMPERS MUTE JUMPERS MUTE JUMPERS MUTE LED MUTE LED PURPOSE SPI/I²C contol Intenal o extenal select Selects between MUTE Enable an MUTE LED Inicato Enable Selects between MUTE Enable an MUTE LED Inicato Enable Inicates that CS4270 MUTE signal is pesent Inicates that CS4270 MUTE signal is pesent POSITION/ REF DES *J10, pins 1-2 J10, none *J8, pins 1-2 J8, pins 2-3 *J3, pins 1-2 J3, pins 2-3 D3 D1 FUNCTION SELECTED/INDICTION *Nomal I²C/SPI Opeation Connect to pins 2 (contol) an 3 (gn) fo extenal contol * MUTE Enable MUTE LED Enable * MUTE Enable MUTE LED Enable MUTE fom CS4270 is pesent when LED is on MUTE fom CS4270 is pesent when LED is on INIT INDICTOR Inicates FPG pogam INIT D5 FPG is being pogamme when on DONE Inicates FPG pogam complete D4 FPG has been pogamme when on RCVR ERROR Inicates CS8416 Data Receive Eo D2 Inicates Data Receive Eo when on US PRESENT Inicates US Connection D7 Inicates US connection when on Table 15. Jumpes an Inicatos *Default factoy settings 26 DS686D3

27 8. DC PERFORMNCE PLOTS CD4270 F S F S 0 0 Figue 11. FFT (-1 48 k) Figue 12. FFT (, 48 k) F S 0 F S 0 Figue 13. FFT (48 k, No Input) Figue k, THD+N vs. Input Feq +40 T TT TT F S F S Figue k, THD+N vs. Level Figue k, Fae-to-Noise Lineaity DS686D3 27

28 CD F S +1-1 F S Figue k, Fequency Response Figue k, Cosstalk F S F S 0 0 Figue 19. FFT (-1 96 k) Figue 20. FFT (, 96 k) F S 0 F S 0 Figue 21. FFT (96 k, No Input) Figue k, THD+N vs. Input Feq 28 DS686D3

29 CD TT T F S F S Figue k, THD+N vs. Level Figue k, Fae-to-Noise Lineaity F S +1-1 F S Figue k, Fequency Response Figue k, Cosstalk F S F S 0 0 Figue 27. FFT ( k) Figue 28. FFT (192 k, ) DS686D3 29

30 CD4270 F S 0 F S 0 Figue 29. FFT (192 k, No Input) Figue k, THD+N vs. Input Feq +40 T TT F S F S Figue k, THD+N vs. Level Figue k, Fae-to-Noise Lineaity F S +1-1 F S Figue k, Fequency Response Figue k, Cosstalk 30 DS686D3

31 9. DC PERFORMNCE PLOTS CD Figue 35. FFT (48 k, 0 ) Figue 36. FFT (48 k, ) 0 0 Figue 37. FFT (48 k, No Input) 20k 40k 60k 80k 100k 120k Figue 38. FFT (48 k Out-of-an, No Input) 0 0 Figue k, THD+N vs. Input Feq 0 FS Figue k, THD+N vs. Level DS686D3 31

32 CD FS -5 Figue k, Fae-to-Noise Lineaity Figue k, Fequency Response TTTTTTTTTT TT TT TTT TT TT V 1 750m 500m 250m 0-250m 0m 0-750m u 1m 1.5m 2m 2.5m 3m sec Figue k, Cosstalk Figue k, Impulse Response 0 0 Figue 45. FFT (96 k, 0 ) Figue 46. FFT (96 k, ) 32 DS686D3

33 CD k 40k 60k 80k 100k 120k Figue 47. FFT (96 k, No Input) Figue 48. FFT (96 k Out-of-an, No Input) FS Figue k, THD+N vs. Input Feq Figue k, THD+N vs. Level FS -5 Figue k, Fae-to-Noise Lineaity Figue k, Fequency Response DS686D3 33

34 CD4270 TTTTTT T TTTT T TTTTTTT TT TTT T V m 500m 250m 0-250m 0m 0-750m u 500u 750u 1m 1.25m 1.5m sec Figue k, Cosstalk Figue k, Impulse Response 0 0 Figue 55. FFT (192 k, 0 ) Figue 56. FFT (192 k, ) k 40k 60k 80k 100k 120k Figue 57. FFT (192 k, No Input) Figue 58. FFT (192 k Out-of-an, No Input) 34 DS686D3

35 CD FS Figue k, THD+N vs. Input Feq Figue k, THD+N vs. Level FS -5 Figue k, Fae-to-Noise Lineaity Figue k, Fequency Response TTTTTTTTTTTTTTTT T T T TTTTTT T V m 500m 250m 0-250m 0m 0-750m u 400u 600u sec Figue k, Cosstalk Figue k, Impulse Response DS686D3 35

36 36 DS686D3 10.CD LOCK DIGRM CS8406 S/PDIF Output Figue 19 CS8416 S/PDIF Input Figue 20 Osc. Figue 21 Clocks/Data Hawae Setup Clocks /Data Hawae Setup DSP HEDER Figue 21 MCLK US FPG Figue 22 DC/DC Clocks & Data Figue 23 DC/DC Clocks/ Data Hawae Setup US/Seial Contol Pot CS4270 HW Setup Switches Figue 22 Figue 16 Figue 65. lock Diagam I 2 C/SPI Heae Figue 23 Powe Figue 24 NLOG INPUT Single-Ene Input Figue 17 NLOG OUTPUT Single-Ene Output Figue 18 CD4270

37 DS686D CD SCHEMTICS Figue 66. CS4270 CD4270

38 CD4270 Figue 67. nalog Input 38 DS686D3

39 CD4270 Figue 68. nalog Output DS686D3 39

40 40 DS686D3 Figue 69. CS8406 S/PDIF Tansmitte CD4270

41 DS686D3 41 Figue 70. CS8416 S/PDIF Receive CD4270

42 42 DS686D3 Figue 71. uffes - Clock/Data Routing CD4270

43 CD4270 Figue 72. FPG DS686D3 43

44 44 DS686D3 Figue 73. US/RS232 Micopocesso CD4270

45 CD4270 Figue 74. Powe DS686D3 45

46 46 DS686D3 12.CD LYOUT Figue 75. Silk Sceen CD4270

47 CD4270 Figue 76. Top-Sie Laye DS686D3 47

48 CD4270 Figue 77. ottom-sie Laye 48 DS686D3

49 13.CHNGES MDE TO REV. ORD CD Moifications (Done by Cius Logic) Note: Thee is no ewok necessay when CS4270 C0 pats ae installe on the Rev. boa. See CD Data Sheet DS686D2 when 0 pats ae installe on the Rev. boa o DS686D1 when 0 pats ae installe on the Rev. boa. lso efeence the Rev. 0, 0, an C0 chip Eata at Select Eata fom the pouct infomation categoies shown. DS686D3 49

50 CD REVISION HISTORY Revision D1 D2 D3 Initial Release: pplies to ssy. (2 PL). Changes This Revision is fo the ssy. (2 PL). Upates fo US pot use, new GUI gaphics, new schematics, new ewok infomation, new layout gaphics an ae pefomance plots. Remove Rev. /1 (PL) efeences, schematics, layout gaphics an ewok. e Pefomance Plots Replace Figue 67 on page 38 Delete Figue 28, oa Moifications Contacting Cius Logic Suppot Fo all pouct questions an inquiies, contact a Cius Logic Sales Repesentative. To fin the one neaest you, go to IMPORTNT NOTICE Cius Logic, Inc. an its subsiiaies ("Cius") believe that the infomation containe in this ocument is accuate an eliable. Howeve, the infomation is subject to change without notice an is povie "S IS" without waanty of any kin (expess o implie). Customes ae avise to obtain the latest vesion of elevant infomation to veify, befoe placing oes, that infomation being elie on is cuent an complete. ll poucts ae sol subject to the tems an conitions of sale supplie at the time of oe acknowlegment, incluing those petaining to waanty, inemnification, an limitation of liability. No esponsibility is assume by Cius fo the use of this infomation, incluing use of this infomation as the basis fo manufactue o sale of any items, o fo infingement of patents o othe ights of thi paties. This ocument is the popety of Cius an by funishing this infomation, Cius gants no license, expess o implie une any patents, mask wok ights, copyights, taemaks, tae secets o othe intellectual popety ights. Cius owns the copyights associate with the infomation containe heein an gives consent fo copies to be mae of the infomation only fo use within you oganization with espect to Cius integate cicuits o othe poucts of Cius. This consent oes not exten to othe copying such as copying fo geneal istibution, avetising o pomotional puposes, o fo ceating any wok fo esale. CERTIN PPLICTIONS USING SEMICONDUCTOR PRODUCTS MY INVOLVE POTENTIL RISKS OF DETH, PERSONL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTL DMGE ( CRITICL PPLICTIONS ). CIRRUS PRODUCTS RE NOT DESIGNED, UTHORIZED OR WRRNTED FOR USE IN IRCRFT SYSTEMS, MILITRY PPLICTIONS, PRODUCTS SURGICLLY IMPLNTED INTO THE ODY, UTOMOTIVE SFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICL PPLICTIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH PPLICTIONS IS UNDER- STOOD TO E FULLY T THE CUSTOMER S RISK ND CIRRUS DISCLIMS ND MKES NO WRRNTY, EXPRESS, STTUTORY OR IMPLIED, INCLUDING THE IMPLIED WRRNTIES OF MERCHNTILITY ND FITNESS FOR PRTICULR PURPOSE, WITH REGRD TO NY CIRRUS PRODUCT THT IS USED IN SUCH MNNER. IF THE CUSTOMER OR CUSTOMER S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICL PPLICTIONS, CUSTOMER GREES, Y SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIUTORS ND OTHER GENTS FROM NY ND LL LIILITY, INCLUDING TTORNEYS FEES ND COSTS, THT MY RESULT FROM OR RISE IN CONNECTION WITH THESE USES. Cius Logic, Cius, an the Cius Logic logo esigns, an Popgua ae taemaks of Cius Logic, Inc. ll othe ban an pouct names in this ocument may be taemaks o sevice maks of thei espective ownes. I²C is a egistee taemak of Philips Semiconucto. SPI is a taemak of Motoola, Inc. Winows is a egistee taemak of Micosoft Copoation. 50 DS686D3