Qucs-S a maturing GPL software package for circuit simulation and compact modelling of current and emerging technology devices
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1 Qucs-S a maturing GPL software package for circuit simulation and compact modelling of current and emerging technology devices Mike Brinson 1, mbrin72043@yahoo.co.uk. Vadim Kuznetsov 2, ra3xdh@gmail.com 1 Centre for Communications Technology, London Metropolitan University, UK 2 Bauman Moscow Technical University, Russia Presented at the 14th MOS-AK Workshop, ESSDERC/ESSCIRC, Lausanne, September 12, / 33
2 Qucs-S a maturing GPL software package: Introduction to presentation Background and release dates for Qucs-S/RC7 Qucs-S documentation and circuit simulation capabilities Qus-S Help documentation: User manual and reference material, Qucs-S SPICE style components and model libraries, Qucs-S extended circuit simulation features. Qucs-S Equation-Defined Device (EDD) and Verilog-A compact device modelling case studies The Efficient Power Corporation (EPC) GaN EPC2001 power transistor model, The MIT virtual source GaN-RF HEMT model. Qucs-S modelling tool extensions and new features XSPICE Code Model support, Qucs-S model parameter extraction controlled by Qctave script files. Qucs-S future developments - the way forward in / 33
3 Qucs-S a maturing GPL software package: Background and release details Development Time Line Original branch New branch Qucs (October 2014) spice4qucs-rc1 + SPICE spice4qucs-rc6 Qucs (September 2016) Qucs-S (September 2016) Qucs is the next release in the Qucs series of software packages. This release is primarily GUI and quasator improvements plus general bug fixes. Snapshot at qucs/files/qucs-binary/ snapshots/qucs rc1-win64.exe/ download New test suite for Qucs-S introduced. A set netlist and simulation tests available. Sources are here: Extended Qucs circuit simulator package, including 1. Improved Qucs GUI, 2. Access to qucsator, Ngspice, Xyce and SPICE OPUS 3. Increased number of circuit simulation types, including pole-zero analysis, distortion analysis, Harmonic Balance, steady state shooting method and Monte-Carlo statistical analysis, 4. Full range of SPICE 3f5, Ngspice, Xyce and SPICE OPUS device models, 5. SPICE style component libraries, 6. Equation-defined device modelling, 7. Verilog-A model synthesis and "Turn Key" C++ code compiler, 8. XSPICE Code model "Turn Key" compiler, 9 XSPICE analogue component library, 10. Nutmeg and Xyce script device modelling, 11. Qucs and Octave post-simulation data processing, 12. Qucs-S device parameter extraction with linked Octave packages. New "Qucs-S Help" Documentation: This is a "live" document which is updated by Qucs-S Developes as the package is improved. Users can find it at - Qucs-S can be found at: 3 / 33
4 Qucs-S a maturing GPL software package: Latest release impact 4 / 33
5 Qucs-S a maturing GPL software package: Functional block diagram 5 / 33
6 Qucs-S a maturing GPL software package: Qucs-S Help documentation 6 / 33
7 Qucs-S a maturing GPL software package: Ngspice, Xyce and SPICEOPUS built in components 7 / 33
8 Qucs-S a maturing GPL software package: Available semiconductor device models 8 / 33
9 Qucs-S a maturing GPL software package: Simulation control icons 9 / 33
10 Qucs-S a maturing GPL software package: XSPICE analogue component models 10 / 33
11 Qucs-S a maturing GPL software package: Qucs-S extended circuit simulation Part 1. SPICE.OP to visual DC by pressing key F8 11 / 33
12 Qucs-S a maturing GPL software package: Qucs-S extended circuit simulation Part 2. Noise spectral response 12 / 33
13 Qucs-S a maturing GPL software package: Qucs-S extended circuit simulation Part 3. Multi-tone Harmonic balance analysis 13 / 33
14 Qucs-S a maturing GPL software package: Qucs-S extended circuit simulation Part 4. Direct support for SPICE libraries 14 / 33
15 Qucs-S a maturing GPL software package: Compact device modelling tools Part 1. Equation-Defined behvioural modelling and Verilog-A model code synthesis 15 / 33
16 Qucs-S a maturing GPL software package: Compact device modelling Part 2. Qucs-S EDD model of the Efficient Power Corporation (EPC) GaN EPC2001 power transistor 16 / 33
17 Qucs-S a maturing GPL software package: Compact device modelling Part 3. Qucs-S EDD model of the Efficient Power Corporation (EPC) GaN EPC2001 power transistor; DC test bench and typical output simulation curves 17 / 33
18 Qucs-S a maturing GPL software package: Compact device modelling Part 4. Synthesis of Verilog-A code for the Efficient Power Corporation (EPC) GaN EPC2001 power transistor 18 / 33
19 Qucs-S a maturing GPL software package: Compact device modelling Part 5. AC gate matching network, test bench and typical simulation results 19 / 33
20 Qucs-S a maturing GPL software package: Compact device modelling Part 6. Switching response test bench and typical simulation results 20 / 33
21 Qucs-S a maturing GPL software package: Verilog-A modeling of the MIT virtual source GaN-RF HEMT 1.0.0: Problems simulating with ADMS; workarounds and typical simulationddata - Part 1. Introduction The Analogue Device Model Synthesizer (ADMS) version is used by Qucs/Qucs-S, Ngspice, Xyce and Gnucap GPL circuit simulators. ADMS is based on a subset of Verilog-A HDL selected for compact device modelling. Although the Verilog-A HDL is standardised there is no guarantee that individual simulator implementations allow the same dialect of Verilog-A for modelling purposes, for example Qucs/Qucs-S Verilog-A models can include component noise while Ngspice does not implement thermal, shot or flicker noise. Normally emerging technology Verilog-A compact models have to be modified, often by hand, to compile without error: specific areas which can cause problems are Internal node collapsing, Voltage limiting, Setting initial conditions, Model equations that include complex combinations of analogue functions, Thermal effects due to power dissipation. 21 / 33
22 Qucs-S a maturing GPL software package: Verilog-A Modeling of the MIT Virtual Source GaN-RF HEMT 1.0.0: Problems simulating with ADMS; workarounds and typical simulation data - Part 2. Model parameter statement error workarounds ADMS parameter statements DO NOT ALLOW reference to previously defined model parameters. 22 / 33
23 Qucs-S a maturing GPL software package: Verilog-A Modeling of the MIT Virtual Source GaN-RF HEMT 1.0.0: Problems simulating with ADMS; workarounds and typical simulation data - Part 3. Removing V (n) < +statements ADMS DOES NOT ALLOW voltage contributions of the form V (n) < +I (n)r, where R is a resistance in Ω, OR statements of the form V (n) < +0.0, Resistors, for example 0.001, are used to short nodes (node collapsing), with I (n) < +V (N)/ / 33
24 Qucs-S a maturing GPL software package: Verilog-A Modeling of the MIT Virtual Source GaN-RF HEMT 1.0.0: Problems simulating with ADMS; workarounds and typical simulation data - Part 4. DC characteristics 24 / 33
25 Qucs-S a maturing GPL software package: Verilog-A Modeling of the MIT Virtual Source GaN-RF HEMT 1.0.0: Problems simulating with ADMS; workarounds and typical simulation data - Part 5. Simulating thermal self-heating effects induced by internal power dissipation The ADMS dialect of Verilog-A does not implement the pwr(dt) statement, Device self-heating is often modelled with a parallel RC network where the volt drop across the RC combination represents the change in device temperature due to internal power dissipation, Tth = RthPd + Temp(Pd = 0), where Tth is the device temperature at power dissipation Pd(W ). 25 / 33
26 Qucs-S a maturing GPL software package: Verilog-A Modeling of the MIT Virtual Source GaN-RF HEMT 1.0.0: Problems simulating with ADMS; workarounds and typical simulation data - Part 6. Variation of thermal resistance Rth and its effect on DC characteristics 26 / 33
27 Qucs-S a maturing GPL software package: Modelling tool additions and new features Qucs-S includes for the first time a turn-key XSPICE code level modelling package for use with the Ngspice and SPICE OPUS circuit simulators, Qucs-S has also been extended to include a new Qucs/Octave integrated tool set for compact device model and circuit macromodel parameter extraction. The technique employed is based on data fitting and optimization using measured, or manufacturers published device data, compared against simulated circuit data. 27 / 33
28 Qucs-S a maturing GPL software package: XSPICE Code Model support subsystem The XSPICE generic device component is the foundation for Precompiled XSPICE device (*.cm) library support, and Dynamic XSPICE Code Model compilation system which allows Code Model sources to be attached to a schematic and compiled automatically at simulation time. Schematic Precompiled CodeModel library XSPICE Generic device spice_netlist().model Component spice_netlist() SPICE Netlist.spinit file Qucs GUI Data visualization Ngspice simulator 28 / 33
29 Qucs-S a maturing GPL software package: XSPICE Generic Device component The XSPICE generic device component is a building block for the construction of user-defined A-devices. It is defined by a comma separated port list, plus XSPICE port designators. These are attached to a SPICE.MODEL statement v0 XSPICE v1 A1 PortList=v,v Model=Amp1.MODEL SpiceModel1 Line_1 =.MODEL Amp1 ggain(gain=10 out_offset=0.01) XSPICE CodeModel XSP_CMod1 File=/home/vvk/projects/xspice_icm/cfunc.mod File=/home/vvk/projects/xspice_icm/ifspec.ifs Source code: cfunc.mod file void cm_ggain(args) { Mif_Complex_t ac_gain; if(analysis!= MIF_AC) { OUTPUT(out) = PARAM(out_offset)+PARAM(gain)* (INPUT(in)+PARAM(in_offset)); PARTIAL(out,in) = PARAM(gain); } else { ac_gain.real = PARAM(gain); ac_gain.imag= 0.0; AC_GAIN(out,in) = ac_gain; } } 29 / 33
30 Qucs-S a maturing GPL software package: XSPICE Turn-Key Model Generation; compiler system dataflow diagram cfunc.mod ifspec.ifs Schematic XSPICE CodeModel XSPICE Generic device spice_netlist().model Component spice_netlist() Extract CodeModels *.mod and *.ifs CodeModels library source tree $WORKDIR/qucs_cmlib/ Makefile XSP_CMod1 cfunc.mod ifspec.ifs XSP_CMod2 cfunc.mod ifspec.ifs dlmain.c modpath.lst udnpath.lst Compilation Make rules file *.mk qucs_xspice.cm Qucs GUI SPICE Netlist.spinit file Data visualization Ngspice simulator 30 / 33
31 Qucs-S a maturing GPL software package: Ngspice/Xyce/SPICEOPUS device parameter extraction from maufacturers data, or measurements, controlled by Octave Script Files; structure diagram 31 / 33
32 Qucs-S a maturing GPL software package: Future developments - the way forward in Qucs-S is a relatively stable circuit simulator and compact modelling tool, incorporating the best features of Qucs, Ngspice. Xyce and SPICE OPUS. The next development phase will concentrate on the following: Testing the package and improving the feature coverage by the Qucs-S test suit, Adding the missing sections to the Qucs-S Help documentation, Introduction of XSPICE and Xyce digital models as the first step towards making Qucs-S a true mixed-mode electronic system and circuit simulation and modelling package, Improvements to XSPICE CodeModel development system, including new XXX.mod and XXX.ifs templates generated from model schematics, Continue development of the Qucs-S built-in libraries. It is expected that the next development phase will last around one year with a series of release candidates published at regular intervals. 32 / 33
33 Qucs-S a maturing GPL software package: Endnote - A brief look into the future Qucs-S True mixed-mode simulation and modelling ANALOGUE and DIGITAL device and IC models Ngspice and SPICE OPUS XSPICE digital IC models Xyce behavioural digital IC models In the next development phase Transistor level digital models Qucsator Ngspice SPICE OPUS Xyce X1 Device=BUF VCC=5 1 1 X3 Device=LOGIC1 X4 Device=LOGIC0 0 X13 Device=XOR = 1 X2 Device=INV VCC=5 X19 Device=NXOR = 1 1 X6 Device=AND4 VCC=5 & En G D0 D1 X5 Device=AND2 VCC=5 & X8 Device=NAND4 VCC=5 MUX Z & X23 Device=MUX2TO1 VCC=5 X7 Device=NAND2 VCC=5 & X10 Device=OR4 VCC=5 En G1 D0 D2 1 MUX G0 D1 D3 Z X22 Device=MUX4TO1 VCC=5 X9 Device=OR2 VCC=5 1 X12 Device=NOR4 VCC=5 1 X11 Device=NOR2 VCC=5 1 A -> D X16 Device=DPr VCC=5 X18 Device=PG D0=0 D1=0 PG D2=0 0 D3=0 1 D4=0 D5=0 2 D6=0 D7=0 3 VCC= X20 Device=FADDER VCC=5 in1 in2 carryin sumout carryout X24 Device=PG0123 D0=0 D1=0 PG D2=0 0 D3=0 VCC=5 1 & & & & X21 Device=ANDOR4X2 VCC= / 33
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