SMASH: a Verilog-A simulator for analog designers
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1 SMASH: a Verilog-A simulator for analog designers Gilles DEPEYROT, Frédéric POULLET & Benoît DUMAS DOLPHIN Integration
2 Outline Context & Goals Coding Guidelines Benchmark of Verilog-A vs. SPICE Progress during the last year Verilog-A limitations in the current implementations Verilog-A vs. SPICE Conclusion Status, Perspectives & Outlook 2
3 Context & Goals What needs to be done so that Verilog-A can become the standard for CM coding? Comparing the general purpose Verilog-A compilers with the integrated SPICE devices Detailed technical investigation of Verilog-A compilation aspects, not only for Compact Models Benchmarking performed to understand current status and SMASH progress Some results previously presented at MOS-AK in Frankfurt and Athens Guidelines put together for CM coding What is at stake? Fully taking into account SPICE-like integration of Verilog Compact Models in the ecosystem Providing a viable and open alternative to controlled initiatives (such as TMI)
4 Coding Guidelines Writing compact models Geoffrey J. Coram, HOWTO (AND HOWNOT TO) WRITE A COMPACT MODEL IN VERILOG-A, BMAS L. Lemaitre, C. Mc Andrew and W. Grabinski, Standardization of Compact Device Modeling in High Level Description Language, Nanotech 2003 Vol. 2 Optimizing compact models Guidelines for Verilog-A Compact Model Coding, Nanotech 2010 Vol. 2 Verilog-A Compact Model Coding Whitepaper
5 Benchmark of Verilog-A vs. SPICE Conditions VIN Test bench: Configurable CMOS delay (400, 4k or 40k MOS) Use default values for the parameters of the MOS models Use two models, one PMOS and one NMOS Computed iterations 2550±5 Use TRAP method for integration
6 Progress in SMASH Loading Time s VA: SMASH 5.14 VA: SMASH 5.15 VA: SMASH 5.16 SPICE: SMASH 5.16 Loading Time: x13 => x5.5 times slower 10.00s 1.00s 0.10s 2.38s 1.94s 0.25s psp-delay100 x9.5=>x s 0.87s 0.23s ekv3-delay100 x3.5=>x s 3.08s 0.40s psp-delay1k x31=>x s 1.65s 0.44s ekv3-delay1k x15=>x s 13.97s 2.60s psp-delay10k x9.7=>x s 10.78s 2.34s ekv3-delay10k x9.1=>x4.6
7 Progress in SMASH Operating Point Time 10,000.00s 1,000.00s Operating Point Time: x73 => x3.1 times slower VA: SMASH 5.14 VA: SMASH 5.15 VA: SMASH 5.16 SPICE: SMASH s 10.00s 1.00s 0.10s 2.50s 0.18s 0.23s psp-delay100 x10.9=>x s 0.15s 0.17s ekv3-delay100 x13.4=>x s 2.32s 2.17s psp-delay1k x25=>x s 2.36s 1.22s ekv3-delay1k x93.7=>x1.9 6,382.00s s 28.90s psp-delay10k x220.8=>x s 26.30s ekv3-delay10k inf=>x2.8
8 Progress in SMASH Transient Speed 10,000.00s 1,000.00s VA: SMASH 5.14 VA: SMASH 5.15 VA: SMASH 5.16 SPICE: SMASH 5.16 Transient Time: x23 => x5.6 time slower s 10.00s 1.00s 33.90s 9.49s 1.10s psp-delay100 x30.8=>x s 11.09s 2.43s ekv3-delay100 x21.4=>x s s 17.20s psp-delay1k x21.4=>x s s 31.30s ekv3-delay1k x22.9=>x4.4 3,384.00s 1,148.25s s psp-delay10k x16.4=>x5.5 1,437.20s s ekv3-delay10k inf=>x3.9
9 Progress in SMASH Memory Consumption 1,000Mb Memory Consumption: x4.3 => x1.2 times more VA: SMASH 5.14 VA: SMASH 5.15 VA: SMASH 5.16 SPICE: SMASH Mb 10Mb 76Mb 45Mb 40Mb psp-delay100 x1.9=>x1.1 71Mb 42Mb 39Mb ekv3-delay100 x1.8=>x Mb 68Mb 57Mb psp-delay1k x7.5=>x Mb 61Mb 51Mb ekv3-delay1k x7.2=>x Mb 294Mb 216Mb psp-delay10k x2.9=>x Mb 246Mb 170Mb ekv3-delay10k x4.7=>x1.4
10 Benchmark of Verilog-A vs. SPICE Summary Loading Time SPICE remains 5.5 times faster Goal: catch up with SPICE in the two years to come Operating-point Time SPICE remains 3.1 times faster Goal: catch up with SPICE in the year to come Transient Speed SPICE remains 5.6 times faster Goal: catch up with SPICE in the six months to come Memory Consumption SPICE consumes 20 % less memory Goal: catch up with SPICE in the year to come General purpose compiler vs. integrated devices
11 Verilog-A Limitations Implementation dependent Simulation Speed Bypass/Linearization Iteration specific code vs. specific code (initialization, noise) Extra nodes added for correlated noise due to ADMS XML limitation Flow/Potential branches Derivation/Integration Hidden states Language (or coding) standard dependent Iteration specific code vs. specific code (output variables) Conditional nodes (collapsible nodes)
12 Verilog-A vs. SPICE Both start from Verilog-A description XML scripts Verilog-A ADMS XML Verilog-A Compiler Model Instance size Instance Local variables Instantiate for each model Instantiate for each instance with the same size Instantiate for each instance Local variable use when the instance is evaluated Model Module Variables
13 Benchmark of Verilog-A vs. SPICE Loading Time s 10.00s VA: SMASH 5.16 SPICE: SMASH 5.16 VA: SimB SPICE: SimB Loading Time SMASH: x5.5 times slower SimB: x6.3 times slower 1.00s 0.10s 0.01s 1.94s 0.25s 0.75s 0.09s psp-delay100 SMASH: x7.8 SimB: x s 0.23s 0.20s ekv3-delay100 SMASH: x s 0.40s 1.75s 0.27s psp-delay1k SMASH: x7.7 SimB: x s 0.44s 0.74s ekv3-delay1k SMASH: x s 2.60s 10.75s 2.71s psp-delay10k SMASH: x5.4 SimB: x s 2.34s 11.87s ekv3-delay10k SMASH: x4.6
14 Benchmark of Verilog-A vs. SPICE Operating-Point 1,000.00s s VA: SMASH 5.15 SPICE: SMASH 5.16 VA: SimB SPICE: SimB Operating Point Time SMASH: x3.1 times slower SimB: x11.3 times slower 10.00s 1.00s 0.10s 0.01s 0.18s 0.23s 0.20s 0.02s psp-delay100 SMASH: x0.8 SimB: x s 0.17s 0.48s ekv3-delay100 SMASH: x s 2.17s 2.30s 0.19s psp-delay1k SMASH: x1.1 SimB: x s 1.22s 5.53s ekv3-delay1k SMASH: x s 28.90s 21.17s 1.80s psp-delay10k SMASH: x10.9 SimB: x s 26.30s 73.06s ekv3-delay10k SMASH: x2.8
15 Benchmark of Verilog-A vs. SPICE Transient Speed 100,000.00s 10,000.00s VA: SMASH 5.16 SPICE: SMASH 5.16 VA: SimB SPICE: SimB Transient Time SMASH: x5.6 times slower SimB: x19.3 times slower 1,000.00s s 10.00s 1.00s 9.49s 1.10s 30.06s 2.64s psp-delay100 SMASH: x8.6 SimB: x s 2.43s 31.77s ekv3-delay100 SMASH: x s 17.20s s 26.66s psp-delay1k SMASH: x6.3 SimB: x s 31.30s s ekv3-delay1k SMASH: x4.4 1,148.25s s 8,822.56s s psp-delay10k SMASH: x5.5 SimB: x31 1,437.20s s 10,197.66s ekv3-delay10k SMASH: x3.9
16 Benchmark of Verilog-A vs. SPICE Memory 1,000Mb VA: SMASH 5.16 SPICE: SMASH 5.16 VA: SimB SPICE: SimB Memory Consumption SMASH: x1.2 times more SimB: x2.1 times more 100Mb 10Mb 45Mb 40Mb 19Mb 13Mb psp-delay100 SMASH: x1.1 SimB: x1.5 42Mb 39Mb 15Mb ekv3-delay100 SMASH: x1.1 68Mb 57Mb 95Mb 42Mb psp-delay1k SMASH: x1.2 SimB: x2.3 61Mb 51Mb 68Mb ekv3-delay1k SMASH: x Mb 216Mb 853Mb 330Mb psp-delay10k SMASH: x1.4 SimB: x Mb 170Mb 540Mb ekv3-delay10k SMASH: x1.4
17 Conclusion Status For the moment, SPICE simulators remain faster than their Verilog-A counterparts Compact models in Verilog-A should continue to target SPICE simulators and respect the inherent constraints to facilitate their integration into different SPICE simulators. What we have today Verilog-A effectively adopted by Compact Model developers Very efficient integration of CM into SPICE simulators using dedicated (ADMS-XML) or optimized Verilog-A compilers A comprehensible approach for behavioral modeling of analog designs (same concepts in Verilog-A as in SPICE) Very flexible mixing of SPICE with Verilog-A (as per LRM Annex E) allowing progressive behavioral modeling
18 Conclusion Perspectives EDA vendors are filling the gap between SPICE and Verilog-A simulators Progress during the past year in SMASH gives good perspectives for the future EDA vendors must now make Verilog-A more attractive than SPICE for semiconductor foundries as well as for final users Future work Integrate coding checks into general purpose Verilog-A compiler Provide analog behavioral model developer with on-line feedback to help debug and optimize models Integrate compact model optimization mode into general purpose Verilog-A compiler Enable direct use in SPICE simulator of fully optimized compact model described in Verilog-A (no EDA vendor integration phase needed)
19 Conclusion Outlook Verilog-A is in competition with non-public API approaches To address the problems of deep submicron processes such as dynamic degradation, power consumption, system-level complexity Semiconductor foundry models currently developed as wrappers around compact models instead of extensions (in Verilog-A) SPICE sub-circuit wrappers, TMI approach Verilog-A has the potential to revolutionize the paradigm of analog design of integrated circuits and totally replace SPICE Depends on the adoption of Verilog-A by all concerned actors: EDA vendors, compact model developers, semiconductor foundries as well as final users HOWEVER, the compact model optimization mode is declared in the Verilog-A LRM but not defined
20 Please go ahead, download and use the free SMASH Discovery option from the DOLPHIN web site Thanks! Please send feedback about the Verilog Compact Model Coding Guidelines to DOLPHIN
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