A COMPLETE DESIGN OF A RISC PROCESSOR FOR PEDAGOGICAL PURPOSES *

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1 A COMPLETE DESIGN OF A RISC PROCESSOR FOR PEDAGOGICAL PURPOSES * Hala ElAarag Department of Mathematics and Computer Science Stetson University 421 N. Woodland Blvd. DeLand, Fl helaarag@stetson.edu ABSTRACT In this paper we present the design of an instruction set architecture to address the need of providing a simple but realistic hands-on experience to computer organization and architecture students. To illustrate the goals of (Reduced Instruction Set Computer) RISC processors, we start with DLX architecture and show how we can apply the RISC philosophy and further reduce the DLX instruction set. At the end, students can build a complete pipelined processor in the lab with minimum cost using TTL chips. In this paper we give a recommendation to the chips needed to build this processor hoping that it would be useful for other Computer organization and architecture professors who want to provide their students with a deep insight on processor design. 1. INTRODUCTION At our University, as is the case for many other universities, we offer one course in computer organization and architecture. This course covers logic design, assembly language programming and computer organization. To give the students a hands-on experience in processor design, we used a kit from Yunten Labs [1]. However, this system is a very simple 4-bit architecture with a handful of instructions. Although students enjoyed building their own processor, this was not sufficient for the instructor. * Copyright 2009 by the Consortium for Computing Sciences in Colleges. Permission to copy without fee all or part of this material is granted provided that the copies are not made or distributed for direct commercial advantage, the CCSC copyright notice and the title of the publication and its date appear, and notice is given that copying is by permission of the Consortium for Computing Sciences in Colleges. To copy otherwise, or to republish, requires a fee and/or specific permission. 205

2 JCSC 25, 2 (December 2009) The Essentials of Computer Organization and Architecture by Null [2] introduces assembly language through MARIE. MARIE has a very simplistic instruction set and datapath. Hennessy and Patterson s Computer Organization and design [3], while widely used, is more adequate at a university where a series of courses on computer organization are offered. It is best if the students are familiar with logic design and assembly language as it focuses on the design of processors. Hennessey and Patterson [3] use MIPS as the example for assembly language programming. While MIPS is a simple assembly language, it is too complicated to digest in one course that covers a board aspect of computer organization. That was the motivation to create HRISC. Our goal was to design an instruction set architecture that is not too simple like MARIE and not as complex as MIPS. HRISC is realistic, yet could be easily build in a lab. In this way, we combine theory and practice and clarify concepts by having students build their own processors from scratch. DLX is a simplified RISC architecture that is designed mainly for pedagogical purposes. We take DLX one step further, and start to reduce its instruction set based on the SPEC benchmarks to reach HRISC instruction set. 2. RELATED WORK There are many simplified architectures designed for pedagogical purposes. Some are designed with the goal of prototyping using FPGAs [4] while others are based on Hardware description Languages (HDL) [5]. Though, most of them are designed as simulators, some examples are Ant32 [6] and MARS [7]. Unlike related work, we had the following goals for our processor design:! Simple enough so students can build it physically using hardware.! Realistic enough so it gives insight on how real processors work.! Based on MIPS (or DLX) architecture. So we can make use of the myriad of simulators that have been developed over the years. To name a few MIPS simulators, SPIM [8] is the most famous and WebMIPS [9] illustrates some of MIPS architectural features like pipelining. 3. HRISC OVERVIEW HRISC is a 32-bit processor that is based on the DLX architecture. It has the following features:! Achieves RISC goals! Has a Simple instruction set! Other desired complex instructions are implemented in software.! Load/store architecture! Has a single addressing mode! Has two fixed length instruction formats.! Opcode and register designators are in the same bit fields within each instruction's encoding for simple decoding. 206

3 CCSC: Southeastern Conference! Pipelined design! Executes one instruction in one clock cycle.! Hardwired control unit. 4. HRISC INSTRUCTION SET In this section, we reduce the instruction set of the DLX machine. Benchmarks provided by the Standard Performance Evaluation Corporation (SPEC) are used [3]. The four benchmarks represent compilers, floating point, general integer and business data processing. From the instruction mixes of the four benchmarks, we noticed that only a small number of instructions (conditional branch, add, load and store) dominate across all four programs. If floating point instructions are not taken into account then it can be noticed that only 22 instructions are considered. Those instructions are the ones which are responsible for more than 2% of the execution in at least one of the benchmarks. Thus, as the other instructions constitute a very small percentage of the instruction execution then, they could be eliminated. This was done as a first step. We also noticed that some instructions have blank spaces. Those are the ones which are not responsible for more than 1.5% of the execution, and the average may appear at 1% or less because the instruction is not used by all benchmarks. These instructions were eliminated as a second step of the reduction. Although not shown here for space limitation, we show how the eliminated instructions could be implemented in software using non-eliminated instructions. From the 53 DLX instructions only 17 are left and 34 are eliminated. Hence the HRISC instruction set has 17 instructions shown in Table 1. HRISC has two instruction formats. Table 1: HRISC Instruction Set Control Branch BEQZ, BNEZ Jump JR, JALR Arithmetic/logical Add ADD,ADDI Subtract SUB And Logical AND Exclusive Or XOR Shift Right Logical SRL Shift Left Logical Load High Immediate Set Data Transfer Load Store SLL LHI SEQ, SLT, SGT LW SW 207

4 JCSC 25, 2 (December 2009) 5. THE TABLE OF EVENTS Table 2 shows the table of events of HRISC. This table of events is considered a documentation that shows the steps of execution of the different instructions in the pipeline. The table shows the pipeline stages on the vertical axis, while the six instruction groups on the horizontal axis. The Register Transfer Language (RTL) is used to describe the operations performed in the pipeline. The arrow used in the RTL means that destinations are loaded on the edge of the clock at the end of the stage. The intersection between a column and a row shows the operations performed in the execution of that instruction in that pipeline stage. All of these operations are done in parallel. Since in a pipelined system all the stages operate at the same time, therefore care was taken not to cause conflicts between operations in different stages of different instructions. Figure 1 shows a complete block diagram of HRISC. The block diagram is also divided vertically into the five stages. In the IF stage, the PC can be loaded with 3 possibilities BTA, RS1 or PC + 1 in case of a taken branch, a jump instruction or noncontrol transfer instructions, respectively. F1 and F2 are used to select an input to the multiplexer. They are functions of b1 and b2 (2 control bits from PROM ID) and the Z line (result of comparing RS1 with 0, if RS1 = 0 then Z = 0). Then f1 = bl.b2'.z' + b1.b2.z f2 = bl'.b2 In the ID stage, a comparator is used to compare RS1 with 0 and outputs the Z line. Also an adder is used to compute the target address of the branch instruction (BTA) early in the pipeline. Registers IR2 and LINK1 take the values of IR1 and PC, respectively. The two source registers are read into registers A and B. In the EX stage, OUT1 stores the result of the ALU instructions while OUT3 stores the result of the SET instructions. 208

5 CCSC: Southeastern Conference Since both OUT1 and OUT3 registers are connected to OUT2, then they should be chosen to be 3-state output registers. OUT1 is enabled by the control line (- (OUT2 <- OUT1)), while OUT3 is enabled by the control line (- (OUT2 <- OUT3)). Registers IR3 and LINK2 take the values of IR2 and LINK1, respectively. MAR is loaded with the ALU output, while MDR1 is loaded with the contents of register B. In the MEM stage registers IR4, OUT2, LINK3, MDR2 and the data memory[mar] are loaded with the contents of IR3, OUT1 or OUT3, LINK2, data memory[mar] or MDR1, respectively. The WB stage writes the register file with the contents of OUT2, LINK3 or MDR2. Only one of these registers is enabled by the corresponding control line and the write operation is performed. 6. DESIGN OF HRISC In this section we show how to build HRISC in a lab using off the shelf chips. Choosing chips for this design is fairly simple. This is because the design consists mainly of registers, PROMs, the register file and the ALU. Texas Instrument s TTL family offers a wide array of functions. The 7400 series is the most widespread family of Integrated circuits (ICs). A List of the chips that could be used is shown in Table 3. Other components could be substituted if they provide the same functionality. Most recent 7400 series parts are fabricated in CMOS. For example, 74HCT258 for High-speed CMOS with TTL-compatible input thresholds are functionally similar to the TTL part 74S258. The CMOS chips have significant power reduction when compared to TTL ones. Also instead of the 8-bit 374 registers there are 16-bit registers like 74FCT16374 and 32- bit registers like 74LVTH32374, which could greatly reduce the number of chips used. If 8-bit registers like the ones suggested in Table 3 are used to design 32-bit processor then the total number of chips used is 159. To build this processor in the lab, we suggest two options. Either build an 8-bit version of HRISC or use the equivalent 32-bit registers. 7. MICROPROGRAM AND HARDWIRED CONTROL UNIT We then design the microinstruction format of each PROM, and the possible entries for each field. For space limitation we show the simplest PROM; PROM ID PROM ID b1,b2 10 BEQZ 11 BNEQZ 01 JR, JALR 00 otherwise Since the PROMS are found to have most of its entries as don t cares, also they have very few control lines, therefore it is better to hardwire the control unit. This would lead to less cost and better speed. We now illustrate how the HRISC control unit could be hardwired. Each instruction has a 6-bit opcode, they are named a,b,c,d,e and f. To facilitate the job, the instruction's opcode can be assigned values such that each bit of the opcode 209

6 JCSC 25, 2 (December 2009) decides which group the instruction belongs to. That is, bit "a" decides whether the instruction is R-type or I-type, "b" decides whether it is a memory or a control instruction, bits "c and "d differentiate between different memory/control instructions, "e" decides whether it is a shift instruction from the ALU R-type instructions, while "f" differentiates between ALU and SET instructions. Table 4 shows the opcode bit configuration of the instructions. PROM ID has two control lines b1 and b2, they can be hardwired as follows: We similarly show the hardwiring for the other PROM EX, PROM MEM and PROM WB. CONCLUSION Implementing processors as part of a computer organization course contributes positively to the learning process. Students obtain an insight that they can t get through theory or simulation. Many students commented on how building their own processor using actual hardware gives them an invaluable experience and reveals many intricacies that otherwise would have remained ambiguous. In this paper, we presented a hardware implementation of a pipelined processor that could be used in the scope of one computer organization course. REFERENCES 1. Computer System Architecture Lab, 2. Linda Null, The Essentials of Computer Organization And Architecture, Jones and Bartlett publishing, Patterson and Hennessy, Computer Organization and Design: The Hardware/Software Interface, Morgan Kauffman, M. Holland, J. Harris, and S. Hauck, "Harnessing FPGAs for Computer Architecture Education", Int. Conf. on Microelectronic Systems Education, June Nestor J., Teaching Computer Organization with HDLs: An Incremental Approach, Proceedings of the 2005 IEEE Int. Conf. on Microelectronic Systems Education. 6. Ellard et al. On the design of a new CPU architecture for pedagogical purposes, Proceedings of the 2002 workshop on Computer architecture 210

7 CCSC: Southeastern Conference education: Held in conjunction with the 29th International Symposium on Computer Architecture, May Vollmar K., MARS: an education-oriented assembly language simulator, Proceedings of the 37th SIGCSE technical symposium on Computer science education, March Larus, J., SPIM: A MIPS32 simulator, 9. Branovic, I., Giorgi, R. and Martinelli, E., WebMIPS: A New Web-Based MIPS Simulation Environment for Computer Architecture Education, Workshop on Computer Architecture Education, 31st International Symposium on Computer Architecture, Munich, Germany, Table 3: Suggested Chips for HRISC Name Type Description Instruction Registers (IR1-IR4) 74AS374 Octal Register with three-state outputs Program Counter 74AS575 Octal D-Type Flip-Flop with Synchronous Clear, Three-state outputs 4:1 Multiplexer 74AS253 Dual 4-line to 1-line Data Selector/Multiplexer with three-state outputs 2:1 Multiplexer 74S258 Quad 2-line to 1-line Data Selector/Multiplexer with Inverted three-state outputs Adder 74S283 4-bit Binary Full adder Register File 74ASC3l03 16 x 8 edge-triggered 3-port register file ALU 74AS181 4-bit Arithmetic Logic Unit and Function Generator Carry Lookahead 74AS bit Lookahead Carry Generator Buffer 74AS244 Octal Buffer with Noninverted three-state outputs PROMs Registers A,B,OUT, LINK, MDR, MAR TBP18S S bits (32 words by 8 bits) Programmable Readonly memories Octal Register with three-state outputs 211

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