ROM (4K X 8) ROM (4K X 8) FOLD BACK FOR RAM0 RWM - RAM (2K X 8) RWM - RAM (2K X 8) FOLD BACK FOR RAM1 INPUT DEVICE 1

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Erica Jennings
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1 Lecture-43 In previous lectures, we have interfaced memory chips, input and output devices separately with the processor. We shall now take up a problem which involves all i.e, ROM, RWM, input devices and output devices. Design an 05A microprocessor based system for a process control application which comprises the following, 1) 05A CPU with 212 latch. 2) k byte ROM consisting of 2732 ROMs (4k x ). 3) 4k RWM consisting of 6116 (2k x ) 4) Two input devices connected through input ports. 5) Two output devices connected through two output ports. 6) A minimum of 32k byte memory space must be available for further expansion. Use memory mapped I/O structure to design interfacing circuitry. Use Fold back principles to simplify device circuitry. Intel 2732 is a 4k x ROM. Therefore, two numbers of chips are required for k x ROM. Similarly, Intel 6116 is 2k x RWM, therefore, two numbers of chips are required for 4k x RWM. Since two input devices are to be interfaced with the processor using memory mapped I/O, therefore, we may reserve a total of k memory locations for input devices 4k for input device 1 and another 4k for input device 2. Similarly, two output devices are to be interfaced using memory mapped I.O, and, therefore, another k memory locations may be

2 reserved for output devices 4k each for output device 1 and output device 2. It is for the user to reserve the memory locations for different devices. In any case, ROM must occupy the initial memory space starting from 0000H. The memory map for this problem is shown in fig H 1FFF H 200 H 2FFF H 300 H 3FFF H 5000 H 5FFF H 7000 H 7FFF H ROM (4K X ) ROM (4K X ) FOLD BACK FOR RAM0 RWM - RAM (2K X ) RWM - RAM (2K X ) FOLD BACK FOR RAM1 INPUT DEVI 1 INPUT DEVI 2 OUTPUT DEVI 1 OUTPUT DEVI 2 32 k Memory Space Not Used Fig.7.12 Memory Map 0000 H 0FFF H 2000 H 27FF H 3000 H 37FF H 4000 H 4FFF H 6000 H 6FFF H 000 H FFFF H After ROMs, next k memory space may be used for RWMs. Although only 4k space is required for RWMs but another 4k may also be reserved for RWMs as FOLD BACK address space. It simplifies the interfacing circuit. Since I/O devices are interfaced as memory mapped I/O, therefore, next 16k may be used for I/O devices k each for input devices and output devices. The remaining 32k is left for future expansion. Accordingly, the devices are connected to

3 system bus comprising address bus, data bus and control bus. The schematic diagram showing these connections is shown in figure. The only thing to be decided now is how to generate the chip select signals for different devices. To generate the chip select signals, the addresses assigned to each chip are tabulated as given in table below: A 15 A 14 A 13 A 12 A A 0 Control Signals Address CSROM H to 0FFFH CSROM1 CSRAM0 CSRAM1 IDSP1 IDSP2 ODSP1 ODSP H to 1FFFH 2000 H to 2FFFH 3000 H to 3FFFH 4000 H to 4FFFH 5000 H to 5FFFH 6000 H to 6FFFH 7000 H to 7FFFH From above table we see that depending on the address many control signals are to be generated device selection. The signals to be generated are also mentioned in the table. It is obvious from the table that the MSB address digit consisting of 4 bit A 15 A 14 A 13 A 12 decides which of the control signal should become ACTIVE LOW. For example, CSRAM0 should become ACTIVE whenever A 15 A 14 A 13 A 12 is

4 0000H. It should be HIGH otherwise. The table gives address bit information for the corresponding control signal to become ACTIVE LOW. The following points also become clear from this table: 1) For all these control signals, A 15 bit should be a zero. 2) Since it is memory mapped, IO/M control signal should be LOW to refer all these devices. 3) The control signals depend open the 3 bits A 14 A 13 A 12. (000) 2 for CSROM0 to (001) 2 for CSROM1 etc. This suggests a 3-line to - line decoder to be used for the decoding circuitry. INTEL 205 or 74LS13may be used as a decoder. The complete interfacing circuitry using 3-line to -line decoder is shown in fig C 10k 10 F 10pF RESET IN X1 X2 Intel 05A AD15- AD ALE AD7- AD0 G 74LS373 Latch A7- A0 16 A15-A0 Unidirectional Address Bus Bidirectional Data Bus,, IO/M, READY, TRAP, RST7.5, RST6.5, RST5.5 D7- D0 INTR, INTA, SID, SOD, S1, S0, HOLD, HLDA, RESETOUT, CLK(OUT) Bidirectional Control Bus

5 AB 12 A11-A0 12 A11-A0 11 A10-A0 11 A10-A0 ROM0 ROM1 RAM0 RAM1 CSROM0 CSROM1 CSRAM0 CSRAM1 WE WE AB INPUT PORT 1 INPUT PORT 2 OUTPUT PORT 1 OUTPUT PORT 2 IDSP1 Input Device 1 IDSP2 Input Device 2 ODSP1 Output Device 1 ODSP2 Output Device 2 AB A15 A12 A13 A14 A0 A1 A2 E3 E1 E Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 CSROM0 CSROM1 CSRAM0 CSRAM1 IDSP 1 IDSP 2 ODSP 1 ODSP 2 IO/M Fig.7.13 Schematic Diagram of Design Problem

History and Basic Processor Architecture

History and Basic Processor Architecture History of Computers Module 1 Section 1 What Is a Computer? An electronic machine, operating under the control of instructions stored in its own memory, that can