Review of Basic. Computer Architecture. Theory Goals Specification

Transcription

1 Computer Archtecture What s Computer Archtecture of Basc Computer Archtecture From Wkpeda, the free encyclopeda In computer scence and engneerng, computer archtecture refers to specfcaton of the relatonshp between dfferent hardware components of a computer system. It may also refer to the practcal art of defnng the structure and relatonshp of the subcomponents of a computer. Ths artcle needs attenton from an expert n computer scence. 2 Computer Archtecture What s Computer Archtecture Defnton 2.0 In computer scence and engneerng, computer archtecture refers to the study of performance n computer systems. It also refers to the practcal scence of applyng performance theory to specfyng the structure and relatonshp of the subcomponents of a computer. From an expert n computer scence. Theory Goals Specfcaton Theory Computaton components CPU: ALU + memory + control s Performance run-tme speed Run-tme of what? Compared to what? Requrements Word processng Number crunchng Gamng Web server Real tme von Neumann Archtecture nput memory output controller Arthmetc Logc Unt (ALU) data/nstructon path control path Specfcaton Requrements + performance theory component mplementaton 3 4

2 5 Requrements Relatve to Applcaton Fastest CPU Intel Xeon Hgh-end verson of Intel x86-64 processor famly IA-32 nstructon set P6 mcro-archtecture + enhancements (Netburst Ivy Brdge) Pentum II Pentum III Pentum 4 Multcore 2 faster than best compettor Fastest supercomputer IBM Sequoa BlueGene/Q CPU Power BQC 6C.60 GHz 98,304 compute nodes,572,864 processor cores.6 PB memory.6 Mega GB (638 TB) Energy effcent 3000 Mflops/watt /3 of best compettor Smartphones ARM CPU Low power Hgher performance / Watt than x86 Fundamental Archtectural Abstractons Dgtal computer Machne that can be programmed to process symbols Symbol wth no ntrnsc meanng to machne User mposes meanng Integer, float, strng,... Operaton Symbol descrbng processng of data symbols Machne nterprets meanng transfer, ALU, control, OS,... Symbol descrbng operaton on data Machne language collecton of legal nstructons Addressng Mode Specfes data locaton as operand Source operand data nput to operaton Destnaton operand data output from operaton 6 Stages n Computer Desgn Typcal Operatons Set Archtecture (ISA). Defne unverse of problems to be solved 2. Study canddate operatons at level of system programmer Atomc operatons complete sequentally General operaton combnaton of atomc operatons 3. Specfy nstructon set for machne language Choose mnmum set of orthogonal operatons Not too many ways to solve same problem Implementaton. Desgn machne as mplementaton of ISA 2. Evaluate theoretcal performance 3. Identfy performance problem areas 4. Improve processor effcency transfer Load (r m), store (m r), move (r/m r/m), convert data types Arthmetc/Logcal (ALU) Integer arthmetc (+ compare shft) and logcal (AND, OR, NOR, XOR) Decmal Integer arthmetc on decmal numbers Floatng pont (FPU) Floatng pont arthmetc (+ sqrt trg exp ) Strng Strng move, strng compare, strng search Control Condtonal and uncondtonal branch, call/return, trap Operatng System System calls, vrtual memory management nstructons Graphcs Pxel operatons, compresson/decompresson operatons 7 8

3 9 Herarchy CPU and Herarchy locatons outsde CPU and RAM Stores data and nstructons of "all" programs Organzed by OS locaton outsde CPU Stores "all" data and nstructons of runnng programs Organzed by addresses locaton n or near CPU Fast access to mportant data and nstructons from RAM Copy of RAM secton locaton nsde CPU Fast access to small amount of nformaton Organzed by CPU CPU controller accesses L cache f (L cache ht) {access performed n clock cycle} else { L cache mss L cache accesses cache controller cache controller ntates access to L2 and man memory f (address n L2 cache) {controller copes contents to L from L2} else {controller copes locaton to L from man memory} } CPU Long Term Storage All Fles and Man (RAM) Runnng Programs and Cache Next Few s and Regster Current ALU Regsters access n CC L nstructons L data request update cache controller L2 I/O Dsk access latency >> clock cycle Man Cache mss penalty Address not n L delay n memory access 0 Specfyng Operands Addressng Modes Immedate Constant IMM numercal value coded nto nstructon Regster operands regster name a CPU storage locaton REGS[regster name] data stored n regster REGS[R3] data stored n regster R operands address a memory storage locaton 45 MEM[address] data stored n memory MEM[223344] data stored at address Effectve Address (EA) ponter arthmetc REGS[R3] &(varable) MEM[REGS[R3]+4] *(&(varable)+4) *(REGS[R3]+4) *( ) 45 R3 Mode Syntax Access Use Regster R3 Regs[R3] Regster data Immedate #3 3 Constant Drect (absolute) Regster deferred (00) Mem[00] Statc data (R) Mem[Regs[R]] Ponter Dsplacement 00(R) Mem[00+Regs[R]] Local varable Indexed (R + R2) Mem[Regs[R]+Regs[R2]] Array addressng ndrect Auto Increment Auto Mem[Mem[Regs[R3]]] Ponter to ponter (R2)+ -(R2) Mem[Regs[R2]] Regs[R2] Regs[R2]+d Regs[R2] Regs[R2]-d Mem[Regs[R2]] Stack access Stack access Scaled 00(R2)[R3] Mem[00+Regs[R2]+Regs[R3]*d] Indexng arrays PC-relatve (PC) Mem[PC+value] PC-relatve deferred 00(PC) Mem[PC+Mem[00]] Load nstructon to data regster Load nstructon to data regster 2

4 3 Commtment to State Internal regsters Temporary regsters used n executng machne nstructons Not vsble to programs Archtectural state CPU regsters vsble to programs System state All data resources vsble to programs Archtectural state + system memory Commtment to state Update of system state Wrte to archtectural state / system memory Complex Set Computer (CISC) Classc Machne Desgn 300 nstructon types 5 addressng modes 0 data types Complex machne mplementatons Manframes ( ) Large, expensve, centralzed computers for bg busness and government Manufacturers: IBM, Control, Burrows, Honeywell Mncomputers ( ) Smaller computers for smaller organzatons Manufacturers: Dgtal (PDP/VAX), General (Eclpse) CISC mcroprocessors ( ) 6800 (974) and 8086 (978) desgned as tny CISC on chp Apple II (977) 6502 (975) IBM PC (98) 8088 (979) Intel x86 for PC/Mac last CISC ISA stll manufactured. 4 Why CISC? Semantc Gap Argument Computer language should mtate natural language Large vocabulary + hgh redundancy flexblty + power Physcal Implementaton of CISC Generc Machne ALU Subsystem Terrble complers Lmted optmzaton Lmted error messagng Effcent code wrtten or optmzed n assembly language Regsters ALU Operaton ALU Result Flag IN 2 3 OUT Expensve memory RAM ~ $5000/MB wholesale n 977 RAM ~ $0.0/MB n 202 System Bus Implcatons for machne language Desgn for user-frendly programmng and small memory use Many hghly specfc nstructons usng many addressng modes Compact nstructon codes that perform a lot of work Status Word Decoder PC - program counter IR - nstructon regster IR PC + MAR - memory address regster MDR - memory data regster control MAR MDR Address Man 5 6

5 7 Decodng Machne s Machne Language SUB R, R2, 00(R3) Mcrocode Sequence (Mcroprogram) ALU_IN R3 ALU 00 ADD MAR OUT READ ALU_IN MDR ALU R2 SUB R OUT Mcrocode nstructon Hardware level atomc operaton 9 lnes 9 clock cycles Regsters Status Word Decoder PC - program counter IR - nstructon regster System Bus IR ALU Operaton ALU Result Flag PC IN + MAR - memory address regster MDR - memory data regster ALU Subsystem 3 2 control OUT MAR MDR Address Man Run Tme and Clock Cycles CPU s tmed by perodc sgnal called clock (CLK) clock cycle Clock Cycle (CC) tme seconds per cycle requres or more clock cycles to process Clock Rate cycles per second Hz (Hertz) Run tme clock cycles to run program seconds per clock cycles clock cycles to run program clock cycles per second Hgher clock rate shorter run tme More clock cycles (at constant clock rate) longer run tme 8 Intel 386 Mcroprocessor Basc Performance Measures Run Tme Elapsed tme T from start to fnsh of a defned program task Latency Excess response tme depends on context Throughput Number of defned tasks performed per unt tme Throughput T + latency between tasks Enhancement Change to system new run tme T ' Speedup T S S > T' < T T ' 9 20

6 2 Defntons T t IC N τ total run tme of program total run tme of nstructons n group number of nstructons n group ( Count) number of clock cycles to run nstructon n group ( C ycles Per ) R clock rate clock frequency clock cycles per second Hertz (Hz) τ IC N number of clock cycles to run all nstructons n group seconds per clock cycle total number of nstructons n program total number of clock cycles to run program quantty ' average number of clock cycles per nstructon for the program new value of quantty after archtectural change CPU Equaton Clock cycles to run all nstructons of type clock cycles nstructon of type N nstructons of type IC Total clock cycles to run all nstructons n program N N IC all groups Average number of clock cycles per nstructon for program total number of clock cycles to run program N total number of nstructons n program IC IC N IC IC IC IC Rato IC IC s proporton (percent) of nstructons n group weghted average IC IC 22 CPU Run Tme Run tme of one nstructon of type clock cycles seconds nstructon of type clock cycle Run tme for all nstructons of type t nstructons of type IC τ Total run tme for program τ clock cycles seconds nstructon of type clock cycle IC τ T t IC τ IC all groups IC So T IC τ clock cycles per nstructon number of nstructons clock cycle Amdahl Equaton t F relatve run tme of nstructons n group T t S speedup for nstructons n group t ' t t FT F T S T' t ' t F F F T S S S S Enhancement to group e S F F F + Fe + S S S e e e e e e Amdahl's "Law" Speedup lmted by F e Enhance maxmum F e Accept mparment to small F e 23 24

7 25 Amdahl Equaton n Parallel Processng F P n processors n P n n + P ( work can be parallelzed) ( work cannot be parallelzed) n n FP + ( FP) n Fracton of processng that can be performed ndependently n Number of processng unts n n IC τ S n processors n processors IC τ F P + n ( F ) P SPEC Benchmark Programs for system performance measurement + comparson Standard + repeatable Test system for realstc condtons Summary score for easy comparson Results posted at Specfc test sutes CINT CPU nteger nstructons CFP CPU FP nstructons Performance as fle server, web server, mal server Graphcs Other advanced features Updated every few years to reflect realstc condtons Based on current statstcal dstrbutons of computng tasks Current CPU test verson 2006 Reports speedup Run tme compared wth a standard machne 26 How SPEC Works User runs n programs on test machne Records run-tme condtons test T,,2,..., n Records program run-tme n seconds SPEC provdes run-tmes on reference machne Sun Ultra Enterprse 2 ref T 296 MHz UltraSPARC II processor Was powerful Unx workstaton n 997 User calculates speedup for each program ref T S test,, 2,..., n T User calculates geometrc mean of speedups n T S ( test machne on ref) T ref test S ( machne A compared to machne B) n S ( machne A on ref) S ( machne B on ref) Typcal SPEC Report Base standard confguraton SPEC(R) CINT2006 Summary Sun Mcrosystems Sun SPARC Enterprse M8000 Wed Mar 2 22:23: CPU2006 Lcense #6 Test sponsor: Sun Mcrosystems Tester: Fujtsu Lmted Test date: Mar-2007 Hardware aval: Apr-2007 Software aval: May-2007 Base Base Base Peak Peak Peak Benchmarks Ref. Run Tme Rato Ref. Run Tme Rato perlbench * * 40.bzp * * 403.gcc * * 429.mcf * * 445.gobmk * * 456.hmmer * * 458.sjeng * * 462.lbquantum * * 464.h264ref * * 47.omnetpp * * 473.astar * * 483.xalancbmk * * SPECnt(R)_base SPECnt Peak specalst confguraton 27 28

8 29 Typcal SPEC Report 2 HARDWARE CPU Name: SPARC64 VI CPU Characterstcs: CPU MHz: 2280 FPU: Integrated CPU(s) enabled: 32 cores, 6 chps, 2 cores/chp, 2 threads/core CPU(s) orderable: to 4 CMUs; each CMU contans 2 or 4 chps Prmary Cache: 28 KB I + 28 KB D on chp per core Secondary Cache: 5 MB I+D on chp per chp L3 Cache: None Other Cache: None : 64 GB (64 x GB, see notes for detals) Dsk Subsystem: 73 GB 0,000 RPM Fujtsu MAY2073RC SAS Other Hardware: None SOFTWARE Operatng System: Solars 0 /06 Compler: Sun Studo 2 (Early Access) Auto Parallel: No Fle System: ufs System State: Default Base Ponters: 32-bt Peak Ponters: 32-bt Other Software: None Representatve Cnt Results Sponsor Processor Clock (GHz) Auto Parallel Total Chps Total Cores Total Threads Hypertechnologes Intel Core X 4.5 Yes Supermcro Intel Core K 4.4 Yes NEC Intel Xeon E Yes Huawe Intel Xeon E Yes Supermcro Intel Core Yes Dell Intel Xeon E Yes Intel Intel Core 2 Duo E Yes Intel Intel Core 2 Duo E No Dell Pentum No.5 Intel Intel Pentum M No 0.7 Base 30 Representatve Cfp Results Sponsor Processor Clock (GHz) Auto Parallel Total Chps Total Cores Total Threads HPE Intel Xeon E Yes Hypertechnologes Intel Core X 4.5 Yes HPE Intel Xeon E Yes Dell Intel Xeon E Yes Supermcro Intel Core K 4.4 Yes Supermcro Intel Core Yes Intel Intel Core 2 Duo E Yes Intel Intel Core 2 Duo E No Dell Pentum No 2.2 Base Benchmarkng a Processor Desgn Specfy Set Archtecture (ISA) Specfes machne language for proposed CPU Provdes human-readable assembly language Determnes for each nstructon group Count clock cycles requred to mplement each nstructon n ISA Wrte complers for proposed machne language C, C++, Fortran Comple benchmark programs to machne language Programs from SPEC CINT and CFP Analyze compler output (executable programs) Sort machne nstructons nto groups Calculate relatve nstructon count IC /IC for each group Calculate average and overall run tme T Compare run tme wth reference machne 3 32

9 33 CISC Creates Ant CISC Revoluton General ntroduces Eclpse 32-bt CISC mncomputer Dgtal (DEC) ntroduces VAX 32-bt CISC mncomputer Frst serous nexpensve competton to manframe computers Serous computers became avalable to small organzatons UNIX developed as mncomputer operatng system TCP/IP developed to support networks of mncomputers Computer Scence emerged as separate academc dscplne Students needed topcs for projects, theses, dssertatons Research results on mncomputer performance CISC uses machne resources neffcently Most machne nstructons are rarely used n programs CISC machnes run slowly to support unnecessary features RISC "Phlosophy" Technologcal developments from 975 to 990 Prce of RAM drops from $5000 / MByte (975) to $5 / MByte (990) Complers become powerful and effcent wth extensve optmzaton Portable code made practcal by mncomputer, Unx, C, and TCP/IP Prncpal research results on CISC performance ~ 90% of run tme devoted to ~ 0% of nstructon set ~ 90% of nstructons n ISA rarely used Reduced Set Computer (RISC) Apply Amdahl's "Law" CISC ISA Speed up operatons accountng for most of run tme Ignore mparments to other nstructons RISC ISA only most mportant CISC nstructons Other CISC nstructons multple RISC nstructons RISC mplementaton executes ts ISA n fast dedcated hardware 34 Types Representatve nstructon dstrbuton Fve programs from SPECnt92 benchmark sute Comple for x86 nstructon set (ISA for Intel 386/486/Pentum) Relatve Proporton of Total Run Tme Load 22% Condtonal branch 20% Compare 6% Store 2% Add 8% And 6% Sub 5% Move reg-reg 4% Call % Return % Other 5% Total 00% Frst 0 nstructons account for 95% of run tme Amdahl's "Law" Fast mplementaton of 95% Other 5% wll not serously degrade performance Must nclude uncondtonal branch for completeness RISC Mcroprocessors Smpler ISA Small set of unform length machne nstructons Smpler hardware No mcrocode standard nstructon mplementaton No central system bus CPU process several nstructons at once Lower + hgher clock speed completes on (almost) every clock cycle All processors today use RISC technology Pure RISC (PowerPC, Sparc, MIPS, ARM, ) RISC technology for CISC language (Pentum II 4, Centrno, Core) Explctly parallel RISC (Intel Itanum, IBM manframes) Ref: Hennessy / Patterson, fgure

10 37 Typcal RISC ISA types 32-bt / 64-bt nteger and floatng pont Flat memory model wth 32-bt / 64-bt address Address mode: dsp(rn) ~ Mem[Regs[Rn] + dsp] Regster-regster operaton model nteger regsters FP regsters OS (kernel mode) regsters Result flags Read-only (value 0) and wrte-only (null) regsters types Load, store, move regster-regster Integer add, sub, mult, dv, shft, compare Boolean and, or, xor Floatng pont add, sub, mult, dv, sqrt, compare Jump, jump regster, jump and lnk, condtonal branch Typcal Encodng types for Alpha 64-bt RISC processor Opcode Number PALcode type Opcode Ra Dsp Branch type Opcode Ra Rb Dsp type Opcode Ra Rb Functon Rc Operate type Opcode (6 bts) dentfes operaton to CPU Ra, Rb (5 bts) dentfy regster names (R0 to R32) PALcode (Prvleged Archtecture Lbrary) hardware support for OS Branch test Ra, true Ra PC, PC PC + Dsp move between Ra and Mem[Regs[Rb] + Dsp] Operate R/R Rc Ra functon Rb (regster name) Operate R/I Rc Ra functon Imm (n Rb and 3 bts of functon) 38 Smple RISC Physcal Implementaton Stage Stage 2 Stage 3 Stage 4 Fetch Decode Execute Access Wrte Back Ppelnng The RISC Advantage Level Parallelsm (ILP) Hardware starts second nstructon before frst completes Typcally 4 nstructons n varous stages of executon at one tme Stage Stage 2 Stage 3 Stage 4 Address Address Early PowerPC mplementaton Wrte Fetch Decode Execute Access Address Address Wrte Back No system bus nstructons proceed from left to rght (assembly lne) Wrte Separate cache memory for nstructons and data Smple repettve operatons CC Stage Stage 2 Stage 3 Stage 4. Fetch unform-length nstructons 2. decode read source operands from regsters 3. Execute ALU nstructons and calculate addresses 4. Access memory and/or wrte destnaton operands (commt to state) I I 5 I I I One CC per stage per nstructon 4 clock cycles per nstructon 6 I 6 I

11 4 Orented Vew s N I W I 5 I 6 Clock Cycles IC+ (ppelne length ) deal N IC IC + ( ppelne length ) ppelne length + IC large IC IC nstructons T IC τ IC τ IC large clock rate deal deal W W W Fetch Decode Execute Wrte Ppelne Imbalance Stage Stage 2 Stage 3 Stage 4 Fetch Decode Execute Access Address Address executes n 4 clock cycles Clock cycle tme determned by LOAD nstructon Longest executon tme τ τ τ τ τ τ τ >τ +τ 2 τ Most nstructons do not access data memory n stage 4 Only LOAD and STORE access data memory Only LOAD performs both memory access and regster wrte-back Most operatons can complete n tme Wrte Back fetch decode execute memory access regster wrte-back mnmum clock cycle memory access regster wrte-back mnmum τ mnmum Wrte 42 Superppelnng Stage Fetch Stage 2 Decode Stage 3 Execute Dvde stage 4 nto two stages Only load/store do useful work n MEM Stage Dvde clock cycle tme (double clock rate) Stage 4 MEM Access Address Address ττ ' τ/2 mnmum IC τ IC τ S 2 ' IC ' τ ' IC τ/2 Programs can run twce as fast I 5 F Stage 5 WB Wrte Back I F D E M W deal D F E D F M E D F W M E D deal ' W M E Ppelne Hazards dependences Result of one nstructon s source for later nstructon Hazard condton Processor runs unnterrupted but provdes ncorrect answers Ppelne hazard Several nstructons n varous stages of executon Ppelne uses a resource value before update by earler nstructon Example ADD R,R2,R3 SUB R4,R5,R ; hazard f SUB reads R before ADD wrtes R Hazard Types Structural Hazard Hazard Control Hazard conflct over access to resource nstructon result not ready when needed branch address and condton not ready when needed 43 44

12 45 Dealng wth Hazards Avod error Pause ppelne and wat for resource to be avalable Called WAIT STATE or PIPELINE STALL Degrades processor performance Adds stall clock cycles (wasted tme) to nstructon executon processng clock cycles (deal) + stalled clock cycles completed nstructon deal stall deal stall N + N N N IC large IC IC IC Elmnate cause of stall Improve mplementaton based on analyss of stalls Man actvty of hardware archtects deal stall stall stall deal performance degradaton + + stall deal stall Structural Hazards Conflct over access to resource Typcal structural hazard unfed cache hazard s and data n same memory devce Cannot access data and fetch nstructon on same clock cycle To prevent hazard Stall INSTRUCTION FETCH durng data MEMORY ACCESS CC CC2 CC3 CC4 CC5 Fetch Decode Execute and Access Address Address unfed cache Wrte Back 46 Stall Implementaton for Cache Hazard MEM WB CC I CC2 LW I CC3 LW I CC4 LW I CC5 φ LW I CC6 φ LW CC7 φ CC8 φ CC9 φ CC0 On CC5 Load Word (LW) nstructon blocks Fetch () No nstructon s fetched on CC5 No nstructon (NOP) s forwarded to on CC6 NOP bubble Φ forwarded to on CC7, etc CC CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 CC0 I MEM WB LW MEM WB MEM WB MEM WB MEM WB Calculatng Effect of Cache Hazard on stall stall cycles nstructons stall cycles stall stalls stall cycles stalls nstructon nstructons types stall nstructon nstructon stall cycle stall load IC cycle stall data memory load stall stall IC + IC data memory store IC load store stall cycle stall IC IC + stall data memory access IC IC stall cycle stall 0.25 loads 0.5 stores + stall data memory access nstructon nstructon stall cycles 0.40 nstructon deal stall (degradaton 29%).4 Assume: Loads ~ 25% Stores ~ 5% Other ~ 60% store 47 48

13 49 Hazards result not ready when needed Classfcaton (named for correct order of operatons) Read After Wrte (RAW) Correct I2 reads regster after I wrtes to t Hazard I2 reads regster before I wrtes to t I2 uses ncorrect value Wrte After Wrte (WAW) Correct I2 wrtes to regster after I wrtes to t Hazard I2 wrtes to regster before I wrtes to t Incorrect value stays n regster Wrte After Read (WAR) Correct I2 wrtes to regster after I reads t Hazard I2 wrtes to regster before reads I t I uses ncorrect value Read After Read (RAR) No hazard reads do not affect regsters To prevent hazard stall ppelne untl result s ready Control Hazards Branch outcome affects program counter (PC) Taken Branch condton s true and PC PC + Dsp Not taken Branch condton s false and PC not changed Target Result of calculaton PC PC + Dsp Branch hazard Outcome not known untl branch executon fnshes Ppelne automatcally fetches (default) nstructon followng branch Default nstructon not correct f branch taken To prevent hazard Flush default nstructons Stall ppelne untl branch condton and branch target are ready Delay n processng branch nstructons s called branch penalty 50 Excepton Hazards Precse Excepton Excepton Hardware or software condton requrng specal servce routne Interrupt Servce response to external hardware event Usually asynchronous Not trggered by program nstructons Does not affect valdty of runnng nstructons Trap Servce response to software condton n runnng program Usually synchronous Trggered by program nstructons May stall or affect valdty of runnng nstructons Hazard Multple nstructons n varous stages of executon n ppelne How/where/when to nterrupt ppelne Where s return-pont? Return-pont Follows atomc operaton Prevous operatons commt all results to state No followng operatons commt any results to state Precse excepton Excepton wth well-defned return-pont Servce excepton followng atomc operaton Restart executon at return pont wthout error I Return-pont I 5 commts no state I 5 I 6 I 7 I 8 commts all state Interrupt Servce Routne 5 52

14 53 Excepton Hazards n 5 Stage Ppelne Exceptons specfc to each stage access excepton n or MEM excepton n Arthmetc excepton n 5 nstructons n varous stages of executon Where s return-pont? How to handle subsequent partally executed nstructons? Berkeley Soluton Attach excepton status feld and source PC to nstructon n rases excepton Mark status feld wth excepton Contnue ppelne untl pror nstructon completes (reaches WB) RETURN-POINT PC of nstructon that rases excepton Flush ppelne (mark nstructons n MEM as NOP to cancel WB) PC CEPTION SERVICE ROUTINE (ESR) Return from ESR depends on excepton type I I 5 CC CC2 CC3 CC4 MEM CC5 WB MEM error CC6 WB MEM CC7 WB MEM CC8 WB MEM CC9 WB CC CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 CC0 I MEM WB I completes atomcally error φ return pont φ φ φ φ φ I 5 φ φ φ φ ESR MEM WB Ref: 54