CONTROL UNIT CONTROL UNIT. CONTROL vs DATA PATH. Instruction Sequencing. Two main operations of Control Unit can be identified:
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1 CONTROL UNIT CONTROL UNIT of the Microprocessor Two main operations of Control Unit can be identified: Instruction sequencing - the methods by which instructions are selected for execution or, the manner in which control of the processor is transferred from one instruction to another Instruction interpretation - the methods used for activating the control signals that cause the data processing unit to execute the instruction. 2 CONTROL vs DA PATH Digital system: data path control path The data processing path is a network of functional units capable of performing certain operations on data The control unit issues control signals to the data processing part These control signals select the functions to be performed at specific times and route the data through the appropriate functional units The data processing path is logically reconfigured by the control unit to perform certain sets of (micro) operations Instruction Sequencing The simplest method of controlling the sequence in which instructions are executed is to have each instruction explicitly specify the address of its successor (or successors, if more than one possibility exists) Explicit inclusion of instruction addresses in all instructions has the disadvantage of substantially increasing instruction length Most instructions in a typical program have a unique successor If an instruction Ii is stored in memory location A, and I i has a unique successor I i+1, then it is natural to store I i+1 in the location that immediately follows A (A+1 or A+k, where k is the length in words of I i ). 3 4
2 Instruction Sequencing Use of a Program Counter (PC) or instruction address register The address of instruction I i+1 can then be determined by incrementing PC thus: PC PC + k where k is the length in words of Ii If I i must be fetched from main memory one word at a time, then PC is automatically incremented by one (k) before each new instruction word is read Consequently, after all words of I have been fetched, PC points to I i+1 A program counter (PC) makes it unnecessary for an instruction to specify the address of its successor, if the program is a linear sequence of instructions 5 Instruction Sequencing Branch instructions specify implicitly an instruction address X. An unconditional branch always alters the flow of program control by causing the operation PC X A conditional branch instruction first tests for some condition C within the processor; C is typically a property of a result generated by an earlier instruction and stored in a status register. If C is true, then PC X, otherwise PC is incremented to point to the next consecutive instruction. 6 INSTRUCTION INRPRETION Instruction interpretation Control Unit (CU) decodes an instruction and generates control signals. Type of control signals (outputs from CU): Controls that select the functions to be performed by data-path at specific times - main job of CU. Controls with other processors (state controls, synchronization, request for control of buses, etc.) There are also synchronization signals (inputs to CU): State and condition information from the datapath and memory interface unit that can modify the sequence of controls generated by CU. State and condition information from other processors (start, stop, acknowledge, busy, etc.) C out directly control data-path. The main purpose of the CU C in feedback from data-path. Can modify the sequence of C out (Conditions, interrupts, and state) C sout to other control unites (State, synchronization, (busy), bus request, confirmations) C sin from others controllers (State, start, stop. Similar to Csout) Data Input C sin C out Control Unit Data-path Cin C sout Data Output 7 8
3 Control Unit Instruction interpretation The control unit tells the data-path what to do every clock cycle during the execution of instructions This is typically specified by a finite-state diagram Every state corresponds to one clock cycle, and the operations to be performed during the clock cycle are written within the state. Each instruction takes several clock cycles to complete MAR PC IR M[MAR] PC PC+k Decode Op-code Memory access not complete Memory access complete Two methods for Control Unite implementation: hardwired control microprogrammed control 9 10 Hardwired control Hardwired control Turning a state diagram into hardware is the next step. The alternatives for doing this depend on the implementation technology. One way to bound the complexity of control is by the product States * Control inputs * Control outputs where: States = the number of states in the finite-state machine controller; Control inputs = the number of signals examined by the control unit; Control outputs = the number of control outputs generated for the hardware, including bits to specify the next state. Example: the finite-state diagram contains 50 states (requiring 6 bits to represent the state) 3 bits to select conditions from the data-path and memory interface unit 12 bits for the op-code of an instruction Control Hardwired logic 40 bits wide 2 (12+3+6) =2 21 entries 12 Instruction Register 3 6 State Control Lines Data-path 11 12
4 Hardwired control Control can be specified as a big table Each row of the table contains the values of the control lines to perform the operations required by the state and supplies the next state number. In figure we assume that there are 40 control lines. The straightforward implementation of a table is with a read only memory (ROM) ROM will require: 2 21 words, each 40 bits wide (10 MB of ROM!) But, little of this table has unique information, so its size can be reduced by keeping only the rows with unique information - at the cost of more complicated address decoding Such a hardware construct is called a programmed logic array (PLA) The solution, introduced by Maurice Wilkes, was to turn the control unit into a miniature computer by having two tables: a table to specify control of the data-path and a table to determine control flow at the micro level Wilkes called his invention microprogramming and attached the prefix "micro" to traditional terms used at the control level: microinstruction, microcode, microprogram Microinstructions specify all the control signals for the data-path, plus the ability to conditionally decide which microinstruction should be executed next Once the data-path and memory for the microinstructions are designed, control becomes essentially a programming task; that is the task of writing an interpreter for the instruction set The invention of microprogramming enabled the instruction set to be changed by altering the contents of control store without touching the hardware Control Microprogram memory Control Lines Datapath The structure of a microprogram is very similar to the state diagram, with a microinstruction for each state in the diagram. While it doesn't matter to the hardware how the control lines are grouped within a microinstruction, control lines performing related functions are traditionally placed next to each other for ease of understanding Groups of related control lines are called fields and are given names in a microinstruction format: 1 Microinstruction PC + Destination ALU operation Source 1 Source 2 Misc Cond Jump address Address select logic Instruction register 15 16
5 Reducing hardware costs by encoding control lines Instrrctions Microsequencer Instructions Microsequencer For example If no more than one of 8 lines is set simultaneously in the same microinstruction, then they can be encoded into a 3-bit field Extra hardware cost of a 3-to-8 decoder Extra time needed... Field... Field B... (3 bits) (2 bits) Decoder 1:8... Decoder 1:4 A0 A1 A7 B0 B1 B2 B3 8 resorces controlled 4 resources controlled Vertical ui Pipeline structures seqvencing Microinstruction no. µi(n+2) µi(n+1) µi(n) Control memory (microprograms) (a) control Time (c) seqvencing Microinstruction no. µi(n+2) µi(n+1) µi(n) Control memory (microprograms) Microinstruction register control Time 17 (b) (d) 18 Nanoprogramming Orders µs ns nmc µmc nri µri sequencing Controls CPU internal hardware sequencing 19
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