Advanced Microprocessors

Transcription

1 Advanced Microprocessors Notes #1 Introduction EE 467/567 Winter 2012 Avinash Kodi, EECS Introduction.1 Lecture Path Introduction x86 Assembly Memory & Security Use inline assembly to evaluate various concepts I/O & Interrupts Architecture Details Introduction.2 1

2 Background Materials Textbook(s): Intel Microprocessors Architecture, Programming, and Interfacing, 8 th Edition, Sections 1.1, 1.2, 1.3, 1.4, 1.5 Other: Intel-64 and IA-32 Intel Architecture Software Developer s Manual Volume 1: Basic Architecture Sections 2.1, 2.3 Introduction.3 Computer Architecture Software Application Operating System Compiler & Assembler Hardware Control Unit Program Storage Data Storage Memory Datapath Input Output Micro Processor Unit (MPU) Input/Output (I/O) Introduction.4 2

3 Control Unit and Datapath Program & Data Storage Hardware Input & Output Introduction.5 Programming the Computer Concepts Programming concepts: Completely describe how the computer needs to perform a task in terms of a sequence of simple basic procedures or instructions! This description is the computer program. Program: A sequence of instructions, For each instruction the computer performs an arithmetic/logical/data transfer/etc. operation. Why? Hardwired systems are inflexible, General purpose hardware can do different tasks, given correct control signals, Introduction.6 3

4 Programming the Computer The instruction pipeline simple case Fetch: Read an instruction from the memory Decode: Interpret the instruction in terms of logical and arithmetic operations (micro-code) Execute: Carry out the instruction (the micro-code) Write: F1 Write data back to memory or registers D1 if necessary E1 W1 : Fetch cycle (instruction # 1) : Decode cycle (instruction # 1) : Execute cycle (instruction # 1) : Write cycle (instruction # 1) Start : F1 D1 E1 W1 F2 D2 E2 W2 Etc. Clock cycles Introduction.7 Programming the Computer Example: the 8086 instruction pipeline F1 : Fetch cycle: BIU W1 : Write cycle: BIU E1 : Execute cycle: EU R1 : Read cycle: BIU EU E1 E2 E3 BIU F1 F2 F3 W1 R3 F5 Etc. Bus Busy Busy Busy Busy Busy Busy Clock cycles Note: Either of the 8086 units (EU or BIU) can perform only one task at a time!! Introduction.8 4

5 General Registers Temporary Registers AH AL BH BL CH CL DH DL SP BP DI SI ALU Data Bus 16 CS DS SS ES IP Internal Communications Registers Address Bus 20 Data Bus 16 Bus Control Logic Fetch Write Read Random Access Memory (RAM) ALU Flags EU Control System Execution Unit (EU) Q Bus Bus Interface Unit (BIU) Intel CPU Input/ Output (I/O) Introduction.9 Increasing the CPU processing Power 1. Increase the clock frequency, Problem: more power dissipation required 2. Increase the number of data busses (code and data) to bring information into the CPU, Problem: packaging 3. Change the internal architecture of the CPU to overlap the execution of more instructions: Problem: data dependency 4. New Technologies in chip manufacturer Introduction.10 5

6 Instruction-level Parallelism Changing the Internal Architecture Methods: Pipelined architecture Superpipelined architecture Superscalar architecture Superpipelined superscalar architecture F1 D1 E1 : Fetch cycle (instruction # 1) : Decode cycle (instruction # 1) : Execute cycle (instruction # 1) W1 : Write cycle (instruction # 1) Introduction.11 Non-pipelined F1 D1 E1 W1 F2 D2 E2 W2 Etc. Pipelined F1 D1 F2 E1 D2 F3 W1 E2 D3 W2 E3 W3 Superpipelined F1 F2 D1 E1 W1 D2 E2 W2 F3 D3 E3 W3 Superscalar F1 F2 F3 D1 D2 D3 E1 E2 E3 W1 W2 W3 F4 F5 F6 D4 D5 D6 E4 E5 E6 W4 W5 W6 Superpipelined superscalar F1 F2 F3 F4 F5 F6 D1 E1 D2 E2 D3 E3 D4 D5 D6 W1 W2 W3 E4 E5 E6 W4 W5 W Clock cycles Introduction.12 6

7 Address Bus Pipelining AH AL 20 BH BL Data Bus General Registers CH DH SP CL DL CS 16 BP DS DI SS SI ES ALU Data Bus 16 IP Internal Communications Registers Bus Control Logic 8086 Bus Temporary Registers ALU EU Control System Q Bus Flags Execution Unit (EU) Bus Interface Unit (BIU) Intel 8086 Introduction.13 Control DP logic Branch target buffer Prefetch address TLB Code cache 8k bytes Superscalar 256 Instruction pointer Prefetch buffers Control Instruction decode ROM 64-bit Branch data verification bus and target address 32-bit Control Unit address bus Bus unit Page unit Address Generate (U pipeline) Address Generate (V pipeline) Floating point unit Control Control Register file Integer register file 32-bit address bus ALU (U pipeline) ALU (V pipeline) 64 Barrel shifter) Add 64-bit data bus 32 Divide Data 32 Multiply 80 Control APIC 32 Data cache 8k bytes TLB 32 Intel Pentium Introduction.14 7

8 PowerPC MPC750 G3 Instruction Unit Fetcher Branch Processing Unit BTIC BHT Instruction (64 Entry) (512 Entry) Queue (6 Word) LR CTR Instruction MMU SRs (Shadow) IBAT Array 128-Entry ITLB Data MMU 128-Bit (4 Instructions) 32-Kbyte Tags i Cache 64-Bit 2 Instructions Dispatch Unit 64-Bit (2 Instructions) PA EA SRs (Original) 128-Entry DTLB DBAT Array Tags 32-Kbyte D Cache Station Station Station GPR File Station (2 Entry) Load/Store Unit FPR File Station Integer Unit 1 Integer Unit 2 System Register Unit 6 Rename Buffers. 32-Bit + (EA Calculation) Store Queue 6 Rename Buffers. Floating- Point Unit + x + x + CR 64-Bit 64-Bit FPSCR 32-Bit 32-Bit Completion Unit Completion Queue (8 Entry) 60x Bus Interface Unit Instruction Fetch Queue 64-Bit L1 Castout Queue L2 Bus Interface Unit L2 Castout Queue 32-Bit Address Bus 32-/64-Bit Data Bus Data Load Queue 17-Bit L2 Address Bus 64-Bit L2 Data Bus L2 Controller L2 Tags L2CR Introduction.15 PowerPC MPC7400 G4 Instruction Unit Fetcher Branch Processing Unit BTIC BHT Instruction (64 Entry) (512 Entry) Queue (6 Word) LR CTR Instruction MMU SRs (Shadow) IBAT Array 128-Entry ITLB Data MMU 128-Bit (4 Instructions) 32-Kbyte Tags i Cache 2 Instructions Dispatch Unit 64-Bit (2 Instructions) EA PA SRs (Original) 128-Entry DTLB DBAT Array Tags 32-Kbyte D Cache Station Station VR File Station Station Station GPR File Station (2 Entry) Load/Store Unit FPR File Station Vector Permute Unit VSCR Vector ALU VSIU VCIU VFPU 128-Bit 6 Rename Buffers. Integer Unit 1 + x 128-Bit 32-Bit Integer Unit 2 + System Register Unit 32-Bit 6 Rename Buffers. Vector Touch Queue 32-Bit + (EA Calculation) Finished Load Fold Stores Completed L1 Stores Operations 6 Rename Buffers. 64-Bit 64-Bit Floating- Point Unit + x FPSCR Completion Unit Completion Queue (8 Entry) L2 Controller L2 Data Transaction L2 Tags L2CR Bus Interface Unit L2 Miss Data Transaction Memory Subsystem Data Reload Data Reload Transaction Queue Table Queue Ability to complete up to two instructions per clock L2 Castout 19-Bit L2 Address Bus 64-/128-Bit L2 Data Bus 32-Bit 60x/MAX Address Bus 64-Bit 60x Data Bus/ 128-Bit MAX Data Bus Instruction Instruction Reload Queue Reload Table Introduction.16 8

9 Improved Performance 8086: 2 Pipelined stages (EU and BIU) 80486: 5 Pipelined stages Pentium: Two parallel pipelines (superscalar) Pentium Pro (II, III, IV also): Three parallel pipelines (superscalar) Introduction.17 Microprocessor Core Introduction.18 9

10 mov mov add bx, [si] ax, [var1] ax, bx Intel P4 Core D A1 66 D increasing memory address From: Introduction.19 Intel Core Core Introduction.20 10

11 PowerPC G5 From: Introduction.21 Pre-requisite EE395A 13 8 PORTA Program Bus EPROM Program Memory Up to 8k x Program Counter 8-Level Stack (13-bit) RAM File Registers Up to 368 x 8 RA0 RA1 RA2 RA3 RA4 RA5 PORTB Instruction Register Instruction Decode & Control Timing Generation Internal RC Clock 8 7 Power-Up Timer Oscillator Startup Timer Power-On Reset Watchdog Timer Brown-out Reset 8 Address MUX FSR Register STATUS Register 3 MUX ALU W Register PORTC RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 Introduction.22 11

12 Code and System-level Compatibility Core Pentium / 8088 Features offered by Pentium are a superset of those offered by the 286 Machine code (program) written for the 8086 will work on Pentium 80286, 80386, 80486, and Pentium can run in real-mode or protected mode; real-mode: processor operates as a high-performance 8086 Introduction.23 Intel Generations Generation Model Other 1st Generation nd Generation rd Generation th Generation th Generation 6th Generation Pentium Pentium Pro Pentium II Pentium III 7th Generation Pentium 4 Pentium D 6th Generation Pentium M Intel Core Yonah 8th Generation Intel Core 2 Conroe (desk), Merom (mobile), Kentsfield (quad) Introduction.24 12

13 Evolution of the Intel Microprocessors Pentium P Pro P II P III Year Introduced Clock rate (Hz) # Transistors Physical Memory Internal Data Bus External Data Bus Address Bus G 4.5k 6.5k 29k 29k 130k 275k 1.2M 3.1M 5.5M 7.5M 8.2M 64k 64k 1M 1M 16M 4G 4G 4G 64G 64G 64G Data type (bits) 8 8 8,16 8,16 8,16 8,16,32 8,16,3 2 8,16,32 8,16,32 8,16,32 8,16, 32 Introduction.25 From: Intel 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture Introduction.26 13

14 From: Intel 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture Introduction.27 Introduction.28 14

15 Competitor AMD Introduction.29 Miscellaneous Introduction.30 15

16 History of the Computer In general we distinguish two Eras: Mechanical Era (1600s 1940s) Mechanical computers were designed to reduce the time required for calculations and increase accuracy of the results Wheels, gear, pulleys Punch cards Electronic Era (1945 present) Tubes, transistors, integrated circuits Introduction.31 History of the Computer Mechanical Era - 1 Babylonians (500 BC) Abacus Mechanical calculator: uses strings of beads Wilhelm Schickhard (1623) Astronomer and mathematician Automatically add, subtract, multiply, and divide Blaise Pascal (1642) Mathematician Mechanical calculator: designed with gears and wheels Capable of addition and subtraction Help his father Introduction.32 16

17 History of the Computer Mechanical Era - 2 Gottfried Leibnitz (1673) Mathematician and inventor Improved Pascal s machine Add, subtract, multiply, and divide Charles Babbage (1830s) Mathematician (University of Cambridge) Difference engine Addition/subtraction, performed finite difference on polynomials Automatic computation of math tables Government / Science agreement Punched results into a copper engraver s plate (I/O) Introduction.33 History of the Computer Mechanical Era - 3 Charles Babbage (1830s) - Continued Analytical engine Addition/subtraction/multiply/divide General purpose via punch cards instructions could be input Modern structure - consists of 4 components: memory, computational unit, input unit (punch card), output unit (punch card and print) Failed to work due to mechanical problems George Boole (1847) Mathematical analysis of logic (Boolean logic) Herman Hollerith (1889) Modern day punch card machine Formed the Tabulating Machine Company (later: IBM) Hollerith s tabulation machine reduced the 7.5 census tabulation estimate to 2 months Introduction.34 17

18 History of the Computer Mechanical Era - 4 Konrad Zuse (1938) Built the Z1 First working mechanical computer Binary machine Development was not pursued by the German government WW II already started Howard Aiken (1944) Designed the Harvard Mark I Build up withy relays Implementation of Babbage s machine Instruction time: 6 seconds) Introduction.35 History of the Computer Electronic Era - 1 Generation 1 COLOSSUS Invented by Alan Turin - first electronic computer Built by British during WW II to break the coded German messages generated by the ENIGMA machine Declassified in the mid-1970s ENIAC (Electronics Numerical Integrator and Calculator) Designed by Mauchly and Echart of the University of Pennsylvania Meant to be used for ballistics (firing tables) during WW II 18,000 vacuum tubes, 1,500 relays, weigth 30 tons, 140kW of power required Instructions for a program could be input with multi-position switches and jumper cables Serial decimal arithmetic 30,000 times faster than the Mark I Introduction.36 18

19 History of the Computer Electronic Era - 2 Generation 1 - continued John von Neumann IAS (Institute of Advanced Studies) machine (Princeton) Program can be represented in digital form in the computer s memory along with the data Serial decimal arithmetic replaced by parallel binary arithmetic (easier to implement using switches) Basic Architecture: Memory, control unit, arithmetic and logic unit, input, output Von Neumann Machine Introduction.37 History of the Computer Electronic Era - 3 Generation 2 (Transistors, ) Transistors Smaller / cheaper / less heat dissipation Solid state device (no moving parts or inert gas), silicon (sand) Invented at Bell labs (1947) by William Shockley, John Bardeen, Walter Brattain TX-0 (Transistorized experimental computer 0) First transistor computer Built be MIT Lincoln Labs High-level languages (Burroughs B5000), Floating-point arithmetic DEC PDP1 10 m 2 DEC PDP-8 First single bus: collection of wires used to connect the components of a computer CDC (Control Data Corporation) 6600 Seymour Gray Highly parallel computer Introduction.38 19

20 History of the Computer Electronic Era - 4 Generation 3 (ICs, ) Invention of the silicon integrated circuit (IC) by Robert Noyce (1959) Many transistors on one chip Semiconductor memory Microprogramming 1971: Ted Hoff of Intel Multiprogramming designs the 4004 Generation 4 (LSI / VLSI, 1974-present) Large scale integration (LSI) / Very LSI (VLSI) Single board computers Generation 5 (ULSI,?-?) VLSI / Ultra LSI (ULSI) (what amount of transistors) Computer communications networks Artificial intelligence (AI) Massive parallel machines Introduction.39 Generations of Computer Vacuum tube Transistor Small scale integration (SSI) on Up to 100 devices on a chip Medium scale integration (MSI) - to ,000 devices on a chip Large scale integration (LSI) , ,000 devices on a chip Very large scale integration (VLSI) to date 100, ,000,000 devices on a chip Ultra large scale integration (ULSI) Over 100,000,000 devices on a chip Introduction.40 20