Intel Architecture: Features & Futures

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1 Inte Architecture: Features & Futures For Servers & Workstations Stephen L. Smith Corporate Vice President, Microprocessor Products Group Genera Manager, Santa Cara Processor Division Inte Corporation

2 Agenda High End IA Roadmap overview Foster Processor preview Merced TM Processor features & status McKiney Processor preview Summary

3 High End IA Roadmap Performance Extends IA Headroom with 64 bit capabiity and scaabiity for high performance computing Merced TM Processor Foster McKiney Madison IA-64 Perf Future IA Deerfied IA-64 Price/Perf Perf Pentium II Xeon TM Processor Tanner Cascades Outstanding performance for 32 bit voume apps m.18m.13m Word cass Server and Workstation Roadmap *Inte code name

4 Soutions Focus Server Apps Workstation Apps Data Warehouse/DSS High Capacity OLTP LOB/ERP Security Directory Services Message Transaction Coaborative Pubication Fie & Print IA-32 deivers outstanding performance and price-performance High end DCC MDA EDA DCC creation/design Entry DCC Desktop Pubishing Mechanica Design IA-32 Software Eng *Inte code name

5 Soutions Focus Server Apps High performance technica computing Very arge memory DB Highest-capacity OLTP Highest end DSS Soutions Data Warehouse/DSS High Capacity OLTP LOB/ERP Security Directory Services Message Transaction Coaborative Pubication Fie & Print IA-64 extends IA features into highest performance commercia & technica computing IA-32 deivers outstanding performance and price-performance Workstation Apps Highest end CAE Anaysis High end Software Eng EDA verification/synthesis High end technica anaysis High end DCC MDA EDA DCC creation/design Entry DCC Desktop Pubishing Mechanica Design IA-32 Software Eng Compementing IA-32 and IA-64 products enabe fu range of Server/Workstation soutions *Inte code name

6 Continuous IA-32 Innovations Performance Foster Greater IPC Dua Independent Bus Architecture Katmai New Instructions Fu speed cache bus Extended memory arch Frequency Boost

7 Continuous IA-32 Innovations New 32-bit microarchitecture Impements trace cache for for instruction decode Enhances branch prediction Performance Faster frequency targeting 1GHz and beyond Foster Large on-chip L1 L1 and L2 L2 cache Greater IPC Dua Independent Bus Architecture Improved system throughput Bus bandwidth of of GB/sec Cache bandwidth increases Katmai L1 New at at Instructions GB/sec, L2 L2 at at 8 GB/sec Fu speed cache bus Extended memory arch Frequency Boost

8 Merced Processor FPU Mutipe read ports Memory 128 FP Register Fie Mutipe write ports 2 Extended Precision (EP) FMACs,, 2 SP FMACs Execution of up to 8 SP FLOPs / cyce 4 EP FLOPs / cyce > 20x Pentium Pro processor and ~3x Tanner performance on 3D graphics

9 IA-32 Hardware Execution Instruction Cache IA-64 Instruction Deivery & Contro IA-32 Instruction Deivery & Contro Execution Resources IA-32 Engine: IA-32 Instruction set decoder Dynamic execution Shared resources: ALUs Registers Data cache The ony 64-bit processor with compete IA-32 binary compatibiity

10 Merced Processor Manages Memory Latency Innovative three eve cache hierarchy Separate instruction & data L0 caches Larger, unified L1 cache on die L2 off die provides arge overa capacity Highy efficient bus and memory utiization Enhanced deferred transaction support Cache ine size optimized to conserve bandwidth Dedicated, fu speed L2 bus frees system bus for MP Increased page size up to 256MB

11 Merced Processor Error Handing Extensive ECC coverage on processor and bus L1 cache, L2 cache, L2 bus, system bus data Fu hardware support for correcting singe bit ECC errors Enhanced machine check architecture Processor and patform error correction via HW/ FW handshake and OS Data poisoning provides greater system avaiabiity through process eve error containment Comprehensive error ogging Error type, cache eve, cache tag/data, corrected errors, transaction type, etc. Suppements numerous processor, patform and OS features for enterprise-cass RAS

12 Merced TM Processor Progress Microarchitecture definition compete Fina stages of functiona RTL vaidation- booting OS kerne Timing convergence exceeding goas Vaidation of circuit design making good progress Comprehensive pre-siicon MP vaidation using thorough RTL co-simuation environment On-track for sampes targeted for mid-1999

13 Merced TM Cartridge Preview Efficient heat dissipation technoogy Separate signa & power connections for signa integrity Cost effective, performance substrate Inte designed static cache RAM Fu speed cache bus

14 Merced TM Patform Program Key server & workstation vendors with mutipe designs Faut toerant, massivey parae and technica computing designs 4 to 512 MP servers and 2/4 MP workstations Mutipe OSes making good progress: UNIX and NT HP-UX, Soaris, SCO, SGI IRIX, Digita Unix, Nove Modesto, Win64 Inte and industry shipping 64 bit SDKs and pre-siicon software deveopment toos Top ISVs porting server and workstation appications Executing on Pan Compier optimization meeting key miestones Mutipe IA-64 OSes and apps booting on Merced simuator Chipsets and systems designs on track for first sampes Industry converging on IA to reap common hardware foundation benefits

15 McKiney Processor McKiney extends Merced TM processor technoogy Enhanced microarchitecture doubes IA-64 software performance > Frequency : Target > 1 GHz > IPC : Increased number of execution units > Very arge, high speed on chip caches Bus is superset of Merced bus: ~3X bus bandwidth Fu Merced & IA-32 software compatibiity Target production : Late 01 McKiney extends Merced processor benefits

16 Summary High performance IA server and workstation roadmap Foster deivers outstanding performance for 32- bit apps Merced TM processor adds 64 bits, increased headroom/ scaabiity McKiney extends Merced processor benefits with 2X performance Future IA-64 proiferations panned for.13m technoogy Merced processor is on track for mid 2000 production Systems, OS, Appications, Toos aigned Common IA foundation brings greater choice to high performance segments Variety of hardware, software and channe choices IA is the Unifying Architecture