Petascale Computing Research Challenges

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1 Petascale Computing Research Challenges - A Manycore Perspective Stephen Pawlowski Intel Senior Fellow GM, Architecture & Planning CTO, Digital Enterprise Group

2 Yesterday, Today and Tomorrow in HPC ENIAC 20 Numbers in Main Memory CDC 6600 First successful Supercomputer 9MFlops ~2008 Beyond Climate Astrophysics Cell-base Community Simulation ASCI Red (word fastest on top500 till 2000) First Teraflop Computer, 9298 Intel Pentium II Xeon Processors Intel ENDEAVOR 464 Intel Xeon Processors 5100 series, 6.85 Teraflop MP Linpack,, #68 on top500 Petascale Platforms Yesterday s s Supercomputing is Today s s Personal Computing

3 The Top500: Reaching Petascale PF on all Top500 reached 04 PF on a single system at ~ NASA - Columbia Earth Simulator Blue Gene IBM ASCI White Intel 1TF barrier to entry to Top500 in It takes merely 8 years to move from #1 to being off the list! Source: top500.org

4 Applications Demand Petascale Example: HPC in Climate Computing Many believe that global warming will produce more extremes weather (drought/flooding). Current models are too coarse for predicting climate change at the national level. To predict regional climate change: Community climate model resolution goal is 10 km Currently can simulate 50 days/day on Red Storm at 10 km using NCAR/SNL SEAM Typical climate simulation is for 100 yrs. To Simulate 100 Year Climate: 1.6 PFlops in 6 Month of Computing; 40 PFlops per Week

5 Highly Multi-threaded Apps and Primitives Rigid body game physics Fluid simulation Portfolio management Text mining Signal / image processing primitives Derivative pricing suite Stochastic optimization suite Partitioning structure collision tests Dense and Sparse matrix primitives

6 Embarrassingly Parallel Applications Computational (GFLOPs GFLOPs) Applications Computer Vision: : Body tracking, 4 DV cameras Ray Tracing: : Beetle car scene, 1 mega-pixel Physical Simulation: : Computational Fluid Dynamics (CFD), 150x100x100, 30 fps Financial Analytics: Asset Liability Management, 8 time-steps steps,, 6 assets,, 10 branches, 1 sec Research Challenge: Develop parallel software applications, languages, tools, OS, Firmware

7 Scalability with Cores 64 48x-57x Speedup x-33x Ray Tracing (Avg.) Mod. Levelset FB_Est Body Tracker Gauss-Seidel Sparse Matrix (Avg.) Dense Matrix (Avg.) Kmeans SVD SVM_classification Cholesky (watson) Cholesky (mod2) Forward Solver (pds-10) Forward Solver (world) Backward Solver (pds-10) Backward Solver (watson) # of cores Source: Intel Labs

8 Exploding Demand for Data Processing Example: HPC in Medical Imaging 10 9 Images/Exam (K) 2MB / Image Single slice in 96: 100 images 64 slice in 05: 3,000 images 256 slice in 07: 10,000 images Source: Intel Digital Health 3-D renderings of the images Computer aided diagnostic algorithms Fusions of images from different modalities MRI, CT, PET, and SPECT Real-time applications are appearing Full Body CT 256 slice/10,000 images: a 20GB file

9 Processor Performance 1.E+15 Peta Flops 1.E+14 1.E+13 1.E+12 Tera Projected Multi/Many Core Performance 1.E+11 1.E+10 1.E+09 1.E+08 1.E+07 Giga 386 Pentium III Architecture 486 Intel Core uarch Pentium II Architecture Pentium Architecture Pentium 4 Architecture 1.E Source: Intel Reaching Petascale with ~3,000 Processors in 2010

10 A Sample Many Core System 10mm 45nm 10mm 32nm 10mm Core Cache 50% 50% 8 Cores, 1V, 3GHz 3.5mm each core Total: 400MT 16 Cores, 1V, 3GHz 2.5mm each core Total: 800MT 65nm, 4 Cores 1V, 3GHz 10mm die, 5mm each core Core Logic: 6MT, Cache: 44MT Total transistors: 200M Note: the above pictures don t t represent any current or future Intel products 22nm 10mm 32 Cores, 1V, 3GHz 1.8mm each core Total: 1.6BT 16nm 10mm 64 Cores, 1V, 3GHz 1.3mm each core Total: 3.2BT Research Challenge: Asymmetric vs. symmetric, Homogenous vs. heterogeneous What kind of applications will benefit?

11 Intra-chip Interconnect Bus for Future Many Core Chip? Issues: Slow Shared, limited scalability? Benefits: Power? Simpler cache coherency Traditional Bus is Not a Good Interconnect Option

12 Intra-chip Interconnect Options to Evaluate Bandwidth, Link Bandwidth and Power 10 Topology Effect on Bandwidth Normalized B/W 0.6 Energy Iso-Bandwidth Energy per bit (J) xbar mesh ring Number of nodes xbar Interconnect Area Iso-Bandwidth Relation to Compute Area ring Clustered ring mesh Number of cores ring Clustered ring mesh 0.0 xbar Number of cores

13 Performance within the Power Envelope Voltage Frequency Rule of thumb Power Performance 1% 1% 3% 0.66% Cache Cache Core Core Core Voltage = 1 Freq = 1 Power = 1 Perf = 1 Voltage = -20% Freq = -20% Power = 1 Perf = ~1.7

14 How Do We Feed the Machine? How Do We Feed the Machine? RMS Workload - Bandwidth and Computation Requirements Soda 1MP Bar 1MP Soda 4MP Bar 4MP Beetle 1MP FB_Est in Video Surv, 2Camera, Webcam, 30fps Ray Tracing: B/Flop 1 TFLOP 150 GB/sec Computer Vision: 0.45 B/Flop Physical Sim: 0.17 B/Flop Memory Bandwidth Computation Financial Analytics: 8.5 B/Flop FB_Est in Video Surv, 4Camera, Webcam, 30fps FB_Est in Video Surv, 4Camera, DV, 30fps FB_Est in Body Tracking, 4Camera, Webcam, 30fps FB_Est in Body Tracking, 4Camera, DV, 30fps CFD (Splash, 75x50x50, 10fps) CFD (Splash, 75x50x50, 30fps) CFD (Splash, 150x100x100, 10fps) CFD (Splash, 150x100x100, 30fps) Medium ALM - 6 Assets, 7 Ways, 8 Timesteps, in 1min Small ALM - 6 Assets, 4 Ways, 8 Timesteps, in 1s Small ALM - 6 Assets, 5 Ways, 8 Timesteps, in 1s Large ALM - 6 Assets, 10 Ways, 8 Timesteps, in 1min Medium ALM - 6 Assets, 7 Ways, 8 Timesteps, in 1s Large ALM - 6 Assets, 10 Ways, 8 Timesteps, in 1s Bandwidth (GB/s) or Computation (GFlops/s) Source: Intel Labs Memory Bandwidth and Processor Performance Need to Keep Pace

15 Memory Bandwidth Vision: 3D Die Stacking Heat-sink Power and IO signals go through DRAM to CPU Thin DRAM die CPU DRAM Through DRAM vias Package DRAM, Voltage Regulators, and High Voltage I/O All on the 3D integrated die

16 Memory Performance for Balanced Computing 0.7 Bytes Per FLOP Source: Intel Byte : Flop Ratio has been Consistent and Steady

17 HPC and Data Center Fabrics Silicon Photonics Future I/O Vision Chip-to to-chip Interconnects Backplane and Display Interconnects Chemical Analysis Medical Lasers Research Challenge: Intra-chip and Inter-chip I/O Architecture and Topology Options

18 System Power/Cooling Efficiency Packages Silicon: Moore s s law, Strained silicon, Transistor leakage control techniques, Clock gating Silicon Heat Sinks Processor: Policy-based power allocation Multi-threaded threaded cores System Power Delivery: Fine grain power management, Ultra fine grain power management Transistors Facilities Systems Facilities: Air cooling and liquid cooling options Vertical integration of cooling solutions Research Challenge: OS, VMM, manageability software take control of system and facility level power management

19 Reliable Systems With Unreliable Components Architectural Techniques Micro Solutions Macro Solutions Detect, Correct, Log and Signal the errors Parity SECDED ECC bit Device Param Tuning Circuit Techniques Process Techniques Lockstepping Redundant multithreading (RMT) Redundant multi-core CPU Rad-hard Cell Creation State-of of-art Processes Research Challenge: From software (Apps, OS, VMM, etc.) to hardware a reliable Petascale HPC system needs management top down

20 1 ZFlops 100 EFlops 10 EFlops 1 EFlops What can we expect! SUM Of Top500 #1 100 PFlops 10 PFlops 1 PFlops 100 TFlops 10 TFlops 1 TFlops 100 GFlops 10 GFlops 1 GFlops HPC Aerodynamic Analysis: Laser Optics: Molecular Dynamics in Biology: Aerodynamic Design: Computational Cosmology: Turbulence in Physics: Computational Chemistry: 100 MFlops Petaflops 10 Petaflops 20 Petaflops 1 Exaflops 10 Exaflops 100 Exaflops 1 Zettaflops Source: Dr. Steve Chen, The Growing HPC Momentum in China,, June 30 th, 2006, Dresden, Germany Reaching Petascale and Beyond with Energy Efficiency

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