Rich Sevcik Executive Vice President, Xilinx APAC: RS _January 05

Transcription

1 System on a Chip Technologies Rich Sevcik Executive Vice President, Xilinx

2 A Top-Ranking Company Forbes Best Managed Semiconductor Company (2004) FORTUNE Best Companies to Work For ( ) Highest ranking public company Highest ranking high-technology company Top Top Top Top Xilinx has been recognized for setting a new standard for managing a high technology business 2

3 Programmability is Mainstream Logic ASIC/FPGA Vendor Ranking Lucent 1. IBM 1. IBM 1. IBM 1. IBM 1. IBM 2. IBM 2. Lucent 2. Lucent 2. Agere 2. NEC 2. NEC 3. NEC 3. NEC 3. LSI Logic 3. LSI Logic 3. Agere LSI Logic 4. LSI Logic 4. NEC 4. NEC Fujitsu 5. Fujitsu Altera Source: Gartner Dataquest Note: Lucent spun-off their semiconductor division in 2001 creating Agere Systems 3

4 Programmable Logic Market Share 100% 80% 60% 40% 20% $2.1B $2.6B $4.1B $2.6B $2.3B $2.6B $3.1B 32% 28% 24% 20% 18% 14% 39% 34% 31% 32% 32% 34% 33% 31% 52% 49% 50% 44% 38% 35% 30% 0% CY98 CY99 CY00 CY01 CY02 CY03 CY04 Forecast Xilinx Altera Other 4 Source: Gartner Dataquest; CY 04 Internal Estimates

5 Fundamental Law of VLSI Technology The number of transistors in an integrated circuit will double every 18 months Source: Intel web site 5 Today s chips have close to 1 Billion transistors!

6 Moore s Law is Alive and Well for FPGAs Moore's Law Intel MPU # of Transistors (000s) TI DSP XLNX (Normalized Logic Cells) 486 DX Pentium Pro Pentium Pentium III Pentium IV Prescott Source: Morgan Stanley, Xilinx 6

7 FPGA Design Trend Relative to ASICs Design Starts Number of Designs (thousands) Source: Gartner Group X FPGA ASIC 7

8 System On A Chip Key Engineering Factors Cost Design cycle time / Time-To-Market Performance/Speed Density/Size Production volume Ease of fixing bugs, making changes 8

9 Simplified FPGA Slice An FPGA slice has 2 LUTs with 4, 5 or 6 inputs 2 registers Carry logic for fast adders 4 outputs, 2 registered + 2 non-registered Slice 0 PRE LUT Carry D Q CE CLR LUT Carry D PRE CE Q CLR 9

10 A Decade of Progress 1000x 200x More Logic Plus memory, µp, DSP, MGT 40x Faster 50x Lower Power 500x Lower Cost 100x 10x CLB Capacity Speed Power per MHz Price XC4000 & Spartan Virtex-II & Virtex-II Pro Virtex & Virtex-E Spartan-2 Virtex-4 XC4000 Spartan-3 1x '91 '92 '93 '94 '95 '96 '97 '98 '99 '00 '01 '02 '03 '04 Year 10

11 Xilinx at the Forefront of Process and Wafer Technology 180 nm 150 nm 130 nm 90 nm First to 150nm and 300mm 1 Year FPGA Leadership First to 130nm and 300mm SIA First to 90nm and 300mm Xilinx 200 mm wafers 300 mm copper wafers

12 FPGA vs. ASIC Cost ASIC: High volumes needed to recover design cost Total cost ASIC Design Cost is much higher (and increasing)!! ASIC.09µ ASIC.13µ FPGA.13µ FPGA.09µ ASIC cost/part is lower For each technology advance, crossover volume moves higher Volume 12

13 13 The Platform FPGA Programmable MGTs Logic DSP Memory PowerPC I/Os Custom Logic Communication Port DSP Accelerator Internal Memory External Memory Port µp

14 IP-Immersion Technology Enabled by 9-Layer Metal Metal 9 Metal 8 Metal 7 Metal 6 Metal 5 Metal 4 PPC PPC Metal 3 Metal 2 Metal 1 Advanced hard-ip block (e.g. PowerPC CPU) Poly Silicon Substrate Active Interconnect Segmented Routing Metal Headroom 14

15 Highest Feature Performance 200,000 LCs 500 MHz Differential Clocking 500 MHz BRAM with FIFO & ECC 500 MHz XtremeDSP slice 622 Mbps Gbps Rocket IO >1 Gbps diff I/O with ChipSync 450 MHz PowerPC with APU 10/100/1000 Ethernet MAC AES design security 15

16 FPGA vs. ASIC Time-To-Market FPGA is 9 months vs. 18 months for ASIC ASIC Spec Design & verification Silicon Prototype System Integration Silicon Production First Ship 50% less time FPGA Spec Design & Verification System Integration First Ship FPGA allows late changes, higher chance of meeting customer needs 16

17 Relative Cost of ASIC Bug Verify Verify Verify!!! Arch Design Test System Customer Note: Verification now takes longer than design!! 17

18 New Approach Standard FPGA with Application Specific Test Traditional ASIC Conversion Time-to-Market Development with FPGA EASYPATH SOLUTIONS Design Frozen Design Conversion 6 to 18 months App. Test Conversion 6 to 8 weeks NO risk NO Engineering Resource NO Prototype Build Board Certification Time-To To-Cost Reduction Volume Production Up to 80% cost reduction Volume Production 18

19 * 8 # PRO LIAN T E SC DL T SD Major Application Areas Communication - Wireless -Wired Radio tower Automotive Storage, Server and Computing Consumer Electronics Disk array FPGAs ASICs Examples: Mars Rover BMW Cars Industrial Networking Satellite dish Satell ite Aerospace, Military, Mission Critical 19

20 Multi-Platform Offering Reduces Cost By Up To 10X Traditional FPGA Family Virtex-4 Multi-platform FPGA Family Device Capability & Cost Feature D Feature C Feature B Feature A Device cost Feature A Feature B Enabled by the Xilinx ASMBL architecture 20

21 Domain Optimized Platforms One Family Multiple Platforms Virtex-4 LX Virtex-4 SX Virtex-4 FX Column based features Platform A Platform B Platform x... Logic Memory DSP Processing High-speed I/O Logic Domain Domain A Highest logic density DSP Domain Domain B Highest DSP performance Enables hard IP Mix Logic, DSP, BRAM, I/O, MGT, DCM, PowerPC Enabled by Flip-Chip Packaging I/O Columns Distributed Throughout Connectivity Domain Embedded Processors High-speed Serial I/O 21

22 Both Hard & Soft IP Necessary for Programmable Systems Programmable hard IP Up to 10x less area Up to 10x lower power Up to 2x performance Customizable soft IP Most flexible Widest selection IP Processing DSP Connectivity Hard PowerPC DSP slice (MAC) PHY (ser./par.) Timing critical I/O logic & clocking Soft Peripherals Accelerators Additional µps Algorithms Protocols Example: Virtex-4 FX platform FPGA 22

23 Combined with IP Solutions DSP Domain System Generator for DSP DSP Cores/Algorithms Connectivity Domain Connectivity IP Source Synch Design Kits Processing Domain Platform Studio & EDK MicroBlaze processor Processing IP Front-to-back design flow LogiCORE IP Design Kits Reference Designs ChipScope Pro Third-party EDA Design Services Support Customer Education 23

24 Complete Design Environment Processor Cores, IP and Silicon Development Tools Development Boards OS Support 24 Breakthrough Performance At Lowest Cost

25 Platform Studio Design Wizards Extreme ease-of-use Configure a new platform in minutes Minimal user-input default system Conceptual Mockup 25

26 Accelerate Performance Beyond the Processor Core Auxiliary Processing Unit (APU) Direct interface from CPU pipeline to FPGA logic Simplifies hardware accelerators Increase performance by over 20X 26

27 Built for Debug IO Pads ILA IP Core PPC405 Core IO IO Pads Pads IBA ILA Custom Logic Embedded System Bus Custom Core ILA IO Pads FPGA provides full internal visibility Debug occurs at system speeds Never too late in an FPGA Hardware fixed during development or after product deployment Enables on-chip co-verification Memory Array ILA ICON Boundary Scan TAP Controller 27

28 The Ultimate Programmable System Platform Auxiliary Processing Unit Auxiliary Processing Unit Auxiliary Processing Unit memory interface, peripherals,... APU Control PowerPC Processor Block D-Cache 405 PPC I-Cache OCM Control Auxiliary Processing Unit APU Control PowerPC Processor Block D-Cache 405 PPC I-Cache OCM Control on-chip memory Processor Local Bus Memory Controller Bridge user logic user logic FIFO user logic user logic Memory Controller user-defined link Peripheral user logic user logic On-chi p Per. Bus User-designed Systems GPP Auxiliary Multiple APUs Network general-purpose may can APUs of processing leverage communicate access communicating interacting perform logic, processor speed units interacting user different using and (APUs) APUs, logic (e.g. (GPP), predictability arbitrary functions with modules. enhance orchestrated its the connected cache user-defined outside. (e.g. of and on-chip I/O), by accelerate to registers). the user concurrently. mechanisms. memory. processor. logic. GPP. 28

29 Connectivity Standards Customer challenges Plethora of interfacing protocols Differing electrical compliance requirements Bridging between parallel and serial devices Storage Networking Telecom Computing OC GFC 2GFC 4GFC SATA SATA2 SATA GbE XAUI 10GbE OBSAI OC GbE PCI Express SATA CPRI SATA PCIE Gen GFC 8.5 CEI (OIF) GFC CEI (OIF) 11G Video HD-SDI 1.45 Support Rate (Gb/s)

30 Example: Virtex-4 Enables PCI Express Compliant Add-in Cards 4x PCI Express 64-bit, 133 MHz PCI-X PCI Express requires Support for power management features Spread spectrum clocking support 30

31 Advanced Switching Industry Rollout Final 1.0 spec Compliance checklist st 4 PI s issues 1 st Pre-silicon Product Announcements Deploy Wired Wired Wireless Wireless Storage Storage Converged Converged Services Services Develop BFM, IP, FPGA Simulation Tools White Papers ATCA based ASI ref design Switches, Bridges early 05 Software Implementations Design Industries 1 st HW demo s ASI 1.1 Specification PCI Express, SLS, SQ, SDT Compliance Tools Ethernet, FC, ATM & other PI s Compliance workshops Gen 2 PHY Advanced Switching for the PCI Express architecture

32 Xilinx University Program Report to the CTO Seeking to enable students Provides donations to Universities Manages external research partnerships 32

33 Summary FPGAs and ASICs are 2 complimentary approaches to SOC Driven by Moore s law, low design cost and shorter design cycle time, FPGAs are becoming dominant! ASICs remain solution of choice only for very high performance or increasingly higher volumes 33