Power Considerations in High Performance FPGAs. Abu Eghan, Principal Engineer Xilinx Inc.

Transcription

1 Power Considerations in High Performance FPGAs Abu Eghan, Principal Engineer Xilinx Inc.

2 Agenda Introduction Trends and opportunities The programmable factor 4 focus areas for power consideration Silicon design & Fabrication Programmability & flexibility in implementation with Software The Package choices The end-user contribution Thermal Management Enabling tools Summary 2

3 Trends & Opportunities in FPGA Process shrinks & Increased level of integration: Allows: More traditional Programmable logic Arrays Embedded Blocks 450Mhz PowerPC, SERDES Multigigabit Transceivers BRAMs, DCM, Xtreme DSP, Ethernet MAC Impact general and may not be unique to FPGA Increased leakage current and static power Heat flux (watts/cm2) trend is up. Higher clock speeds capability The increased frequency imply high performance & higher dynamic power Challenges Shared with Industry Reliability limitation & lower operating temperatures Performance & Cost Trade-offs Lower thermal budgets 3

4 FPGA Attributes Programmability & Uniqueness Factor: More programmable transistors to deal with The challenge to Packaging Flexibility means power needs are largely unknown There is no single tailored thermal solution for all applications The upside Die size is relatively large power density is not at the edge More standby or passive transistors reduced power density Menu of packages offered - with broad heat handling capability, Closer OEM collaboration, to get real world feedback Opportunity to deal with power beyond packages into silicon, software etc. 4

5 Power Considerations Reduced Need for Heat Sinks Smaller Power Supplies Critical for equipment with high T j and little or no cooling Wired/wireless equipment - outdoor Modular racks in storage/servers Automotive Telematics & entertainment Mil/Aero battle tanks, fighter planes, etc Ideal & common requirement Bigger, faster, cheaper! Reduce the need for heatsinks or at least the cost of thermal solution Lower power supply overhead & complexity 5

6 The 4 Prong Approach The 4 focus areas Silicon design & Fabrication Software implementation of design Programmability, flexibility & choices The Packages FCBGA consistent TIM The end-user contribution Thermal Management Enabling tools 6

7 Considerations - 1 The Silicon: Design & Implementation contribution to Heat generation 7

8 FPGA-101: FPGA Terms Logic Blocks used to implement a wide range of arbitrary digital functions. Programmable I/O Blocks Routing resources Switch matrix and interconnects/pass gates Key FPGA attribute regardless of what heterogeneous functions and elements are incorporated - is the ability to implement arbitrary digital logic circuit. 8

9 The 3 common Power Components 1. Transient Inrush current 2. Static 3. Dynamic Inrush TOTAL Dynamic Power Static Time 9

10 Addressing The 1st Power Components 1. Transient Inrush current 2. Static 3. Dynamic Inrush TOTAL Dynamic Power Static Time 10

11 Transient - Inrush Current While Vcc rises from 0 V to nominal voltage Internal circuits can go through states of confusion Configuration storage latches can wake up at random states Without proper handling of this wake phase, this confusion may lead to internal contention In older generation FPGAs the inrush current spike (multiple amps) were sources of concern prior to the elimination by sequential house-cleaning Inrush current is almost eliminated in Xilinx devices through innovative configuration features & protocols Impact on Power: This was more of a power supply issue than a sustained heat management issue due to its transient nature and the associated large heat capacity of the large chips where this phenomena can be significant. 11

12 The 2nd Power Components 1. Transient Inrush current 2. Static 3. Dynamic Inrush TOTAL Dynamic Power Static Time 12

13 Static Power Increases Dramatically with Temperature 7 I CCINTQ vs Junction Temperature 6 gate I CCINTQ Normalized Leakage Current source I GATE I S D 25 C drain 85 C 100 C Junction Temp C 13

14 Xilinx 90nm Triple-Oxide Technology Leakage current increases as channel length and gate oxide thickness decrease Same oxide thickness is not needed in all the transistors Two oxide thicknesses are commonly used in the industry Thin oxide in the fast core logic Thick oxide in the versatile I/O 90nm implementation adds a third medium thickness oxide to selected structures to reduce leakage current without compromising performance Source Metal Connection Source Gate Channel Drain Metal Connection Drain Gate Oxide varying thicknesses on die 14

15 Optimizing Performance and Leakage High speed and low power: Low VT transistors LUTs, LUTs, I/O, I/O, Interconnect, Interconnect, Configuration Configuration Memory Memory Cells Cells used only where necessary for speed Choose different oxide thicknesses Select transistor size for performance and function Threshold Oxide Transistor Voltage (VT) Thickness Size Optimal transistor mix for minimizing leakage and maximizing performance 15

16 Reducing Leakage Current Function Oxide Thickness Threshold Voltage (V T ) Channel Length Speed Leakage I/O Thick High Longest Fast Lowest Configuration Memory Medium Medium Long Slow Low Interconnect Pass Gates Medium Low/Medium Short Fast Low Logic & Interconnect Thin Low Short Very Fast Medium/High Careful management of various process parameters Enables low leakage current; hence, low static power without a negative impact on performance Triple-oxide technology, threshold voltage, channel lengths are tuned Triple-oxide technology yields biggest gains 16

17 Multi-oxide Technology Reduces Static Power 6 Relative Static Power (Worst Case process & 85 ºC) nm Trend 50 % Lower Power 90nm FPGA Trend 25K 50K 75K 100K 125K 150K 175K 200K Logic Cells 90nm has 50% lower static power than equivalent 130nm 17

18 Xilinx 90nm FPGA Power 1 to 5 Watts lower power per FPGA 50% reduction in 90nm static and dynamic power vs 130nm devices at the 100K Gate Enabled through multi-oxide technologies 90nm triple-oxide technology deployment High-performance embedded IP Design choices made to meet power budget without compromising FPGA performance 18

19 Addressing The 3rd Power Components 1. Transient Inrush current 2. Static 3. Dynamic Inrush TOTAL Dynamic Power Static Time 19

20 Dynamic Power Dynamic Power P = kcv 2 f where k = Nodes switching C = Capacitance per node V = Voltage switching f = switching frequency or toggle rate Reduced Core dynamic power Internal operating voltage is the dominant factor Secondary scaling by frequency and node capacitance Even at 50% higher operating frequency, the 90nm implementation reduces dynamic power by 20% Constant I/O dynamic power Similar capacitance, voltage and frequency to support industry I/O standards Relative Core Power % FPGA Core Dynamic Power Trend 130nm 90nm Node Capacitance drops Voltage drops Relative Capacitance or Voltage 20

21 Process Shrink Reduces Dynamic Power 130 nm 90 nm % Change Power Ratio V ccint % 0.64 C tot (rel.) % 0.80 same frequency % 0.51 f max (rel.) % 1.5 Max f (k*cv 2 f) % E.g., Virtex-4 (90nm) has 50% lower dynamic power than Virtex-II Pro (130nm)

22 Low Power by Design Hard IP 500 MHz Logic Array 500 MHz Differential Clocking 1 Gbps diff I/O with ChipSync 450 MHz PowerPC with APU 10/100/1000 Ethernet MAC 500 MHz XtremeDSP Slice 500 MHz BRAM and FIFO 22

23 Why Hard-IPs Reduced Static Power No extra transistors as in programmable logic No programmable interconnect transistors Reduced Dynamic Power Metal Interconnects vs. Metal and programmable interconnects Reduced trace lengths No extra node capacitance because of lack of pass transistors Minimized layers of logic 23

24 Considerations - 2 ISE Contribution to Total Thermal management Placement Implementation 24

25 Optimizations for Power Designs may be placed with Optimizations Optimized For performance Optimized for lower power Feature selection, including power conservation features, impacts power Dynamic Power varies linearly with frequency Implement non-critical functions to run on a low speed clock rather than an arbitrary high speed clock in the design Your actual mileage will depend on the course you take and your driving habits 25

26 Power Reduction Techniques Through Switching Nodes and Capacitance Reduction Reducing number of nodes switching into a capacitive load Minimize Logic Levels through better logic packing (ex. Use a packed Relationally Placed Macro - RPM) Increase design speed target for routing purpose to minimize interconnect length and reduce interconnect capacitance Use an RPM or other placement method to guide tighter placement and help reduce routing length, especially on repeated macros Bump up performance target for XST router May be able to gain 5-10 % power improvement lower capacitance by minimizing path length and interconnect hops 26

27 Dynamic Power Reduction Techniques Through Embedded Functions Significant reduction when implementing embedded functions OSERDES, ISERDES, FIFOs, DSP48, PPC, EMAC 5 12x Reduction on power over FPGA fabric and FPGA programmable interconnects Interconnect length is reduced and interconnect transistors eliminated Not dependent on programmable paths or non-optimized placement Direct metal connection reduce lumped node capacitance Logic is reduced Minimal logic layers are present and minimal logic size Significant fewer transistor being switched Able to use a smaller Virtex-4 FPGA due to logic saving Reduce both static power and dynamic power with Embedded functions 27

28 Considerations - 3 The Package implementation Contribution to Thermal Management 28

29 Xilinx Package Features that Enhance Thermal Performance Built on the heat efficient Flipchip BGA (FCBGA) offerings Enhance thermal performance beyond standard FCBGA packages Enable very low θ JC through the top Void free, thin and low resistance thermal Interface material (TIM) consistently applied to ensure lower θ JC from the back of the die Deliver a low resistance platform for heat sink applications Offer up to 20% lower θ JB compared to past generation product ( see next slide) Enhanced power and ground plane arrangement through Xilinx unique SparseChevron technology Improved electrical return path boosts copper density and overall thermal conductivity through the package Increase vertical thermal conductivity through a denser and distributed via field Silicon VCCINT GND SIO VCCO GND CORE (600 um) VCCINT GND VCCO GND VCCAUX 29

30 FPGA SparseChevron Pinnout New IO/Vcco/GND pattern Better IO to GND/Vcco pair ratio Every SelectIO adjacent to Vcco & GND Vcco GND Vccint Vccaux I/O FF1513 Pin-out Thermal Performance Impact Increased via density 18-20% improvement in Theta-JB 30

31 Considerations - 4 The Programmability Challenge Supporting the End-user in their system Thermal management using FPGAs. 31

32 Managing System Level Heat 32 FPGA dilemma: Application environment is unknown. Some guesses are possible When thermal margins are low the Ja, Jc (figure of merit) thermal data is inadequate. Addressing the unknown Efficient packages - inherently low Theta-JC & Theta-JB Predetermine some known environments Natural Air Heatsinks with Forced air fans (1 rack, 2 rack unit H/S) Box/Container design, Board as a heatsink, Conducting plates Application specific thermal design - OEM contribution Thermal Implementation Enablers: Xpower Power estimations BCI-CTM library for these product

33 Post-Implementation XPower in ISE software Integration in Design Flow Considers device data, along with the user's design files Report estimated device power consumption at high level of accuracy customized to specific design Enables FPGA designers to perform detailed power analysis Tool extracts utilization from ISE and toggle rates from test vectors and simulation Output Use the GUI or detailed report to see what is consuming the power FPGA nets can be highlighted in XPower and shown in FPGA Editor Power Analysis 33

34 CTM for Thermal Budget Planning Accurate temperature prediction of IC components at the system level has become critical due to the shrinking thermal budget Xilinx provide Compact Thermal Models (CTMs) for system thermal budget planning These behavioral models predict package temperature at the selected nodes (e.g., junction, case, and balls) when integrated with other ICs. CTM libraries are Downloadable (pdml and taz format) on Xilinx.com for usage in conjunction with customers thermal simulation tools. 34 Two model types offered by Xilinx

35 Summary Process shrinks & Increased level of integration offer some challenges for FPGA at leading edge CMOS technologies. Improvements in system and device reliability through significant power reduction and package enhancements are still possible. The following are some of the specific activities making those incremental improvements possible Static power reduced by >40% through innovative choices in process and circuit design Dynamic power reduced by 50% at a given frequency general voltage reduction Use of Embedded functions reduce power by a factor of 5x to 10x Enhanced package thermal performance through Xilinx unique via field arrangement - SparseChevron technology applied to FCBGA Lowered θ JC and θ JB to further reduce thermal concerns Comprehensive software tools for placement and power optimization. Thermal model libraries support for system design, power estimation and system thermal analysis 35

36 Thanks for your attention Acknowledgements: Matt Klein, Xilinx Inc. for his inputs & contribution 36