Introduction. ECE/CS 5780/6780: Embedded System Design. Memory-Mapped I/O. Isolated I/O. Expanded Mode. Multiplexed Address and Data Lines
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1 Introduction ECE/CS 5780/6780: Embedded System Design Chris J. Myers Lecture 20: Memory Interfacing Most embedded systems use only the memory built-in to the microcontroller. Memory interfacing and bus timing is important to understanding internal microcontroller architecture. Sometimes internal memory insufficient, and external memory needed. Sometimes external devices are interfaced using memory-mapped I/O. Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 1 / 41 Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 2 / 41 Memory-Mapped I/O Isolated I/O Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 3 / 41 Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 4 / 41 Expanded Mode Multiplexed Address and Data Lines Select R/W Function 0 0 Off 0 1 Off 1 0 Write 1 1 Read Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 5 / 41 Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 6 / 41
2 Full-Address Decoding Address Decoder for 1K RAM at $4000-$43FF Slave selected only when slave s address is on the bus. Design using the following steps: 1 Write specified address using 0,1,X: 0100,00XX,XXXX,XXXX for 1K RAM at $4000-$43FF 2 Write equation using all 0s and 1s: select = A15 A14 A13 A12 A11 A10 3 Build circuit using gates. Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 7 / 41 Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 8 / 41 An Address Decoder for I/O Device at $5500 Minimal-Cost Address Decoding Use don t cares for unspecified addresses to simplify. Example: 4K RAM $0000 to $0FFF 0000,XXXX,XXXX,XXXX Input $ ,0000,0000,0000 Output $ ,0000,0000, K ROM $C000 to $FFFF 11XX,XXXX,XXXX,XXXX Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 9 / 41 Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 10 / 41 An Address Decoder Karnaugh Maps Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 11 / 41 Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 12 / 41
3 Special Cases Programmable Address Decoder Size of the memory is not a power of 2. 20K RAM with address range $0000 to $4FFF 00XX,XXXX,XXXX,XXXX Range $0000 to $3FFF 0100,XXXX,XXXX,XXXX Range $4000 to $4FFF Start address divided by memory size not an integer. 32K RAM with address range $2000 to $9FFF 001X,XXXX,XXXX,XXXX Range $2000 to $3FFF 01XX,XXXX,XXXX,XXXX Range $4000 to $7FFF 100X,XXXX,XXXX,XXXX Range $8000 to $9FFF In Mn An Vn Out 0 X X X X X Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 13 / 41 Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 14 / 41 Timing Intervals Available and Required Time Intervals ( Y, Y) = ( A, A)+10 ( Y, Y) = ( A, A)+[5,15] ( Y, Y) = ( A+[8,15], A+[5,12]) DA = ( G +[10,20], G +[0,15]) DA = ( G + 20, G ) worst-case DR = ( Clk 30, Clk + 5) Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 15 / 41 Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 16 / 41 Timing Diagrams Example Timing Diagrams Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 17 / 41 Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 18 / 41
4 Read Cycle Circuit Write Cycle Circuit Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 19 / 41 Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 20 / 41 Synchronous Bus Timing Partially Asynchronous Bus Timing (6809/680x0/x86) Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 21 / 41 Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 22 / 41 Fully Asynchronous Read Cycle Fully Asynchronous Write Cycle Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 23 / 41 Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 24 / 41
5 Four Types of Control Signals MC9S12C32 Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 25 / 41 Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 26 / 41 MC9S12C32 Modes of Operation MC9S12C32 Modes of Operation BKGD MODB MODA Description Port A Port B MODx write Special In/Out In/Out Write anytime, Single chip not peripheral Emulation A15-A8/ A7-A0 Cannot change Exp. narrow D7-D Special test A15-A8/ A7-A0 Write anytime, Exp. narrow D15-D8 D7-D0 not peripheral Emulation A15-A8/ A7-A0 Cannot change Exp. wide D15-D8 D7-D Normal In/Out In/Out Write once, Single chip Norm exp N/W Normal A15-A8/ A7-A0 Cannot change Exp. narrow D7-D Peripheral Cannot change Normal A15-A8/ A7-A0 Cannot change Exp. wide D15-D8 D7-D0 BKGD MODB MODA Description Port A Port B MODx write Normal In/Out In/Out Write once, Single chip Norm exp N/W Normal A15-A8/ A7-A0 Cannot change Exp. narrow D7-D Normal A15-A8/ A7-A0 Cannot change Exp. wide D15-D8 D7-D0 Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 27 / 41 Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 28 / 41 MC9S12C32 Clock Circuit MC9S12C32 Expanded Mode Bus Timing Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 29 / 41 Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 30 / 41
6 Address Latch for MC9S12C32 General Approach to Memory Interfacing Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 31 / 41 Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 32 / 41 Wide Expanded Mode 8K RAM Read Timing Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 33 / 41 Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 34 / 41 8K RAM Write Timing 8K RAM Write Timing Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 35 / 41 Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 36 / 41
7 8K RAM Interface ($8000-$9FFF) 8K RAM Interface Read Timing Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 37 / 41 Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 38 / 41 8K RAM Interface Write Timing 8K by 16-bit RAM Interface Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 39 / 41 Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 40 / 41 Dynamic RAM (DRAM) DRAMs High density One xtor, one cap./bit Slower High fixed cost (refresh) Low incremental cost Address multiplexing SRAMs Low density 3-4 xtors/bit Faster Low fixed cost (address decoder) Higher incremental cost Direct addressing Chris J. Myers (Lecture 20: Memory Interfacing) ECE/CS 5780/6780: Embedded System Design 41 / 41
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